JP2006119830A - Storage device, data processing system and storage control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device having superior response in writing. <P>SOLUTION: Blocks including a plurality of memories are controlled respectively to conduct register transfer processing RP at continued different time periods in which each memory has resister transfer time TR. The resister transfer process is applied in parallel to the plurality of memories included in the same block. After completing the register transfer processing, then writing processing to a memory cell array starts. After elapsing the maximum writing time, the control is applied to the plurality of memories for re-register transfer processing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a storage device, a data processing system, and a storage control method for performing a write operation on a plurality of memories each including a register and a storage area in which data read from the register is written.

For example, a semiconductor storage device such as a Memory Stick (registered trademark) or an SD (Secure Digital) memory card (registered trademark) is detachably attached to an electronic device such as a personal computer or a portable playback device, and the electronic device There is a system for accessing a semiconductor memory device.
As a semiconductor memory device used in such a system, for example, a plurality of flash memories are connected in parallel, and an IO (Input Output) bus (input / output) is used for input / output between the plurality of flash memories and an electronic device. Some buses are shared from the viewpoint of downsizing.
The semiconductor memory device includes a register transfer process for transferring data input from an electronic device via an IO bus to a register in a flash memory and a program for writing the data read from the register in the flash memory to a memory cell in a write operation. Process.
At this time, in the semiconductor memory device, after executing register transfer processing for all of the plurality of flash memories in different time zones, program processing for the plurality of flash memories is started at the same time, and predetermined processing required for the program processing is determined. After the maximum program time, which is the maximum time, has elapsed, the next register transfer process is performed again.

JP 2000-122923 A

However, in the conventional semiconductor memory device described above, after executing register transfer processing for all of the plurality of flash memories in different time zones, program processing for the plurality of flash memories is started at the same time, and after the maximum program time has elapsed, Since the transfer process is performed again, the electronic device cannot transfer the write data to the semiconductor memory device during the maximum program time until the program process ends (the register transfer process cannot be performed).
As a result, there is a problem that the responsiveness of the semiconductor memory device as viewed from the electronic device is poor.

  In order to solve the above-described problems of the prior art, the present invention can be used even when an interface for inputting data to be written to the memory area from the outside is shared between a plurality of memories to which data read from the register is written to the memory area. Another object of the present invention is to provide a storage device, a data processing system, and a storage control method that are excellent in responsiveness at the time of writing as viewed from the outside.

  In order to solve the above-described problems of the prior art and achieve the above-described object, a storage device according to a first aspect of the present invention includes a plurality of memories each having a register and a memory area, an interface for inputting data, and A register transfer process for transferring data input from the interface to the register of the memory and a memory write process for reading the data from the register and writing to the memory area are performed for each of the plurality of memories. A control circuit that controls the data input from the interface when the plurality of sets including one or a plurality of the memories are defined so that each of the control circuits does not overlap with another set. Output to each of the plurality of sets at different consecutive time periods of one time length, and include the output data in the same set For the memory to perform the register transfer process for transferring in parallel to the registers of the plurality of memories, and to cause the memory to start the memory write process after the time period has elapsed. The memory is caused to perform the next register transfer processing after the elapse of a second time length defined in common for the plurality of memories.

The operation of the storage device of the first aspect of the invention is as follows.
When the control circuit defines a plurality of the sets including one or a plurality of the memories so as not to overlap each other, in the register transfer process, the data input from the interface is set to the same first time length. Are output for each of the plurality of sets at different time periods.
Then, in the register transfer process, the control circuit causes the memory to perform a process of transferring the output data in parallel to the registers of the plurality of memories included in the same set.
Then, the control circuit causes the memory to start the memory write process after the elapse of the time period, and continues after the elapse of a second time length defined in common for the plurality of memories for the memory write process. Then, the next register transfer process is performed in the memory.

  A data processing system according to a second aspect of the present invention is a data processing system having a storage device and a data processing device for writing data into the storage device, each of the storage device having a register and a memory area. A plurality of memories; an interface for inputting data to be written from the data processing device; and a register transfer process for transferring data input from the interface to the registers of the memory for each of the plurality of memories; A control circuit that performs a memory write process of reading the data from the register and writing the data in the memory area, and the control circuit includes one or more of the memories so that each does not overlap with another set When a plurality of the sets are defined, the same first data is input from the interface. The register transfer process for outputting to each of the plurality of sets in different time zones having consecutive inter-lengths and transferring the output data in parallel to the registers of the plurality of memories included in the same set And the memory write processing is started after the elapse of the time period, and after the elapse of a second time length defined in common for the plurality of memories for the memory write processing. The register transfer process is performed in the memory.

The operation of the data processing system according to the second aspect of the invention is as follows.
When the control circuit defines a plurality of the sets including one or a plurality of the memories so as not to overlap each other, in the register transfer process, the same data is input from the data processing device via the interface. Output to each of the plurality of sets in consecutive different time zones of the first time length.
Then, in the register transfer process, the control circuit causes the memory to perform a process of transferring the output data in parallel to the registers of the plurality of memories included in the same set.
Then, the control circuit causes the memory to start the memory write process after the elapse of the time period, and continues after the elapse of a second time length defined in common for the plurality of memories for the memory write process. Then, the next register transfer process is performed in the memory.

  A storage control method according to a third aspect is a register transfer in which each of a plurality of memories each having a register and a memory area and sharing an interface transfers data input via the interface to the register of the memory. A storage control method for performing a process and a memory writing process for reading the data from the register and writing the data to the memory area, each of which includes a plurality of the memory including one or more of the memories so as not to overlap each other When a set is defined, the data input from the interface is output to each of the plurality of sets in different time zones having the same first time length, and the output data is included in the same set A first step of causing the memory to perform the register transfer processing for transferring in parallel to the registers of the plurality of memories; A second step of causing the memory to start the memory write processing after the elapse of the time period from the start of the register transfer processing in the first step; and starting the memory write processing in the second step. And a third step of causing the memory to perform the next register transfer processing after the second time length defined in common for the plurality of memories has elapsed.

  According to the present invention, even when a plurality of memories that write data read from a register to a memory area share an interface for inputting data to be written to the memory area from the outside, the response at the time of writing viewed from the outside A storage device, a data processing system, and a storage control method excellent in performance can be provided.

Hereinafter, a data processing system to which the present invention is applied will be described with reference to FIGS.
First, the correspondence between the components of the present embodiment and the components of the present invention will be described.
The memory card 3 corresponds to the storage device of the present invention.
The computer 2 corresponds to the data processing apparatus of the present invention.
The memories 53_1 to 53_8 shown in FIGS. 5 and 6 correspond to the memory of the present invention, the data register 66 shown in FIG. 7 corresponds to the register of the present invention, and the memory cell array 72 corresponds to the memory area of the present invention. .
Also, the SP conversion circuits 60_1 to 60_4 in FIG. 6 correspond to the conversion circuit of the present invention.
The bus B_DIO shown in FIGS. 3, 4 and 5 corresponds to the interface of the present invention.
A control circuit 35 shown in FIG. 3 corresponds to the control circuit of the present invention.
Further, the set including the memories 53_1 and 53_2, the set including the memories 53_3 and 53_4, the set including the memories 53_5 and 53_6, and the set including the memories 53_7 and 53_8 illustrated in FIG. 6 respectively correspond to the set of the present invention. is doing.
The register transfer time TR corresponds to the first time length period of the present invention.
The maximum program time TPmax corresponds to the second time length of the present invention.
In the present embodiment, a case where the number n of memories is “8” will be described as an example.

FIG. 1 is an overall configuration diagram of a data processing system 10.
As shown in FIG. 1, the data processing system 10 includes, for example, a computer 2 and a memory card 3.
First, the outline of the data processing system 10 will be described.
The computer 2 includes a mounting unit (slot) for mounting the memory card 3, and writes and reads data to and from the memory card 3 mounted in the mounting unit.
In the data processing system 10, as will be described later with reference to FIGS. 3 and 5, the bus B_DIO used for data transfer between the control circuit 35 and the memory circuit 36 is shared by the memories 53_1 to 53_8 in the memory circuit 36. . Therefore, compared with the case where the bus is not shared, the number of pins of the interface 16 shown in FIG. 1 can be reduced and the scale can be reduced.
In the data processing system 10, as shown in FIGS. 6 and 8, the control circuit 35 sends write data for two pages to the bus B_DIO within each register transfer time TR. Then, the SP conversion circuits 60_1 to 60_4 take in serial data, which is write data sent to the bus B_DIO by the control circuit 35, in consecutive different time zones assigned to the SP conversion circuits 60_1 to 60_4.
That is, only a single SP conversion circuit among the SP conversion circuits 60_1 to 60_4 takes in serial format write data from the bus B_DIO in each time slot.
Thereafter, the SP conversion circuits 60_1 to 60_4 convert the fetched write data into a parallel format and transfer the converted data to the data registers 66 of the subsequent memories 53_1 to 53_8 in parallel.
Thereby, according to the data processing system 10, the responsiveness of the write operation of the memory card 3 can be improved as compared with the conventional case when viewed from the computer 2.

<Computer 2>
The computer 2 is a personal computer, a portable audio playback device, a portable video playback device, a mobile phone, or the like.

As shown in FIG. 1, the computer 2 includes, for example, a signal processing circuit 11, a reader / writer 13, and an interface 14.
The signal processing circuit 11 operates based on the clock signal PCLK to generate predetermined data, and outputs the data to the reader / writer 13 via a PCI (Peripheral Component Interconnect) bus.
The interface 14 includes the above-described mounting portion for mounting the memory card 3.
The interface 14 outputs the clock signal SCLK generated in the computer 2 and the data WR_DATA input from the reader / writer 13 to the interface 16 of the memory card 3. Data WR_DATA is data that the computer 2 writes to the memory card 3.
The interface 14 outputs the data RD_DATA input from the interface 16 to the reader / writer 13. Data RD_DATA is data read from the memory card 3 by the computer 2.

The reader / writer 13 controls data writing and data reading with respect to the memory card main body 17.
FIG. 2 is a block diagram of the reader / writer 13 shown in FIG.
As shown in FIG. 2, the reader / writer 13 includes, for example, an SP conversion / 8-10 decoding circuit 21, an ECC (Error Correcting Code) decoder 22, a bus interface 23, a CRCC (Cyclic Redundancy Check Code) encoder 24, an ECC. It has an encoder 25, a switch 26, and an 8-10 encode / PS conversion circuit 27.

The SP conversion / 8-10 decode circuit 21 operates based on the clock signals PCLK and SCLK input from the signal processing circuit 11.
The SP conversion / 8-10 decoding circuit 21 inputs read data RD_DATA output from the memory card body 17 of the memory card 3 shown in FIG.
The SP conversion / 8-10 decode circuit 21 converts the input read data RD_DATA from the serial format to the parallel format, and then converts it into the original 8 bits, and converts the converted data DATA8 [7: 0] to the ECC decoder 22. Output to.
The ECC decoder 22 performs ECC processing on the data DATA8 [7: 0] input from the SP conversion / 8-10 decode circuit 21 to generate data RDATA [7: 0], and outputs this to the bus interface 23. .

The bus interface 23 is a PCI bus interface provided between the signal processing circuit 11 and the bus interface 23.
The bus interface 23 outputs, to the CRCC encoder 24, a command COMMAND [7: 0] that defines control over the memory card 3 among the data input from the signal processing circuit 11 via the PCI bus.
The bus interface 23 outputs data WDATA [7: 0] to be written to the memory card 3 among the data input from the signal processing circuit 11 via the PCI bus to the ECC encoder 25.
Further, the bus interface 23 outputs a switching signal MODE of the switch 26 to the switch 26.

The CRCC encoder 24 generates a command ENC_CMD [7: 0] in which CRCC parity data is added to the command COMMAND [7: 0] input from the bus interface 23, and outputs this to the switch 26.
The ECC encoder 25 generates write data ENC_DATA [7: 0] by adding an ECC code to the data WDATA [7: 0] input from the bus interface 23 and outputs this to the switch 26.

The switch 26 selects one of the command ENC_CMD [7: 0] input from the CRCC encoder 24 and the write data ENC_DATA [7: 0] input from the ECC encoder 25 from the bus interface 23. Is selected and output to the 8-10 encode / PS conversion circuit 27 as data ECC_ENC_DATA.
The 8-10 encoding / PS conversion circuit 27 performs 8-10 conversion on the data ECC_ENC_DATA input from the switch 26 to convert it into data from which the DC component (DC) has been removed, and then converts the data from the parallel format to the serial format. Then, data WD_DATA to which the synchronization code is added is generated, and this is output to the memory card 3 via the interface 14 shown in FIG.

<Memory card 3>
The memory card 3 is, for example, a Memory Stick (registered trademark) or an SD memory card (registered trademark).
As shown in FIG. 1, the memory card 3 has an interface 16 and a memory card body 17.
The interface 16 is connected to the interface 14 of the computer 2 in a state where the memory card 3 is mounted on the computer 2, and receives the clock signal SCLK from the interface 14 and outputs it to the memory card main body 17.
Further, the interface 16 receives data WR_DATA from the interface 14 and outputs it to the memory card body 17 when the computer 2 performs a write operation on the memory card 3.
The interface 16 outputs read data RD_DATA output from the memory card body 17 to the interface 14 of the computer 2 when the computer 2 performs a read operation on the memory card 3.

FIG. 3 is a block diagram of the memory card body 17 shown in FIG.
As shown in FIG. 3, the memory card body 17 includes, for example, a clock frequency dividing circuit 31, an SP conversion / 8-10 decoding circuit 32, an 8-10 encoding / PS conversion circuit 33, an error detection circuit 34, a control circuit 35, and A memory circuit 36 is included.
The clock divider circuit 31 divides the clock signal SCLK input via the interface 16 to generate a clock signal PCLK, which is converted into an SP conversion / 8-10 decode circuit 32 and an 8-10 encode / PS conversion circuit 33. To the error detection circuit 34 and the control circuit 35.

The SP conversion / 8-10 decode circuit 32 converts the data WR_DATA input via the interface 16 from the serial format to the parallel format, and then converts the data to the original 8 bits to generate the data DATA8 [7: 0]. This is output to the error detection circuit 34.
The SP conversion / 8-10 decode circuit 32 operates based on the clock signals SCLK and PCLK.
The 8-10 encode / PS conversion circuit 33 receives the read data RDATA [7: 0] read from the memory circuit 36 by the control circuit 35, performs 8-10 conversion on the read data RDATA [7: 0], and generates a DC component (DC). After conversion to the removed data, the data is converted from the parallel format to the serial format, and data RD_DATA to which the synchronization code is added is generated and output to the interface 16.
The 8-10 encode / PS conversion circuit 33 operates based on the clock signals SCLK and PCLK.

The error detection circuit 34 detects an error in the data DATA [7: 0] input from the SP conversion / 8-10 decoding circuit 32 and outputs the result to the control circuit 35.
Specifically, when the data DATA [7: 0] input from the SP conversion / 8-10 decode circuit 32 is the command ENC_CMD [7: 0], the error detection circuit 34 converts the data DATA [7: 0] into the command COMMAND [7 : 0] to the control circuit 35.
Further, when the data DATA [7: 0] input from the SP conversion / 8-10 decode circuit 32 is the write data ENC_DATA [7: 0], the error detection circuit 34 writes the write data WDATA [7: 0] to the control circuit 35.
Further, the error detection circuit 34 detects data ECC_SYNC [7: 0], which is a syndrome of the data DATA [7: 0] input from the SP conversion / 8-10 decode circuit 32, and outputs this to the control circuit 35. .
Further, the error detection circuit 34 detects data CRCC_SYNC [7: 0], which is a syndrome of the data DATA [7: 0] input from the SP conversion / 8-10 decoding circuit 32, and outputs this to the control circuit 35. .

The control circuit 35 performs a write operation and a read operation on the memory circuit 36 based on the command COMMAND [7: 0] input from the error detection circuit 34.
Specifically, when the command COMMAND [7: 0] indicates writing, the control circuit 35 writes the write data WDATA [7: 0], the data ECC_SYNC [7: 0], and the data CRCC_SYNC that are input from the error detection circuit 34. Data [7: 0] is generated in association with [7: 0], and is output to the memory circuit 36 via the bus B_DIO.
When the command COMMAND [7: 0] indicates writing, the control circuit 35 writes the data DIO [7: 0] to a predetermined address in the memory circuit 36 according to a predetermined rule.
Further, when the command COMMAND [7: 0] indicates reading, the control circuit 35 reads data from the predetermined address in the memory circuit 36 specified based on the command COMMAND [7: 0] via the bus B_DIO. This is output to the 8-10 encoding / PS conversion circuit 33 as data RDATA [7: 0].

FIG. 4 is a block diagram of the control circuit 35 shown in FIG.
As shown in FIG. 4, the control circuit 35 includes, for example, a decoder 41, a FIFO (First In First Out) circuit 42, an input / output circuit 43, and eight memory control circuits 45_1 to 45_8.
In the present embodiment, as shown in FIG. 5 to be described later, the case where the memory circuit 36 includes eight memories 53_1 to 53_8 is illustrated, and the memory control circuits 45_1 to 45_8 correspond to the memories 53_1 to 53_8, respectively. Is provided.

The decoder 41 controls the FIFO circuit 42, the input / output circuit 43, and the memory control circuits 45_1 to 45_8 based on the command COMMAND [7: 0] input from the error detection circuit 34.
Specifically, the decoder 41 outputs the data DIO [7: 0] generated as described above to the FIFO circuit 42 when the command COMMAND [7: 0] indicates writing.
Then, the decoder 41 controls the FIFO circuit 42 and the input / output circuit 43 and outputs data DIO [7: 0] to the memory circuit 36 via the bus B_DIO provided between the decoder 41 and the memory circuit 36.
In addition, when the command COMMAND [7: 0] indicates writing, the decoder 41 controls the memory control circuits 45_1 to 45_8 so that a writing operation described later in the memory card body 17 is performed.
Based on the control from the decoder 41, the memory control circuits 45_1 to 45_8 generate control signals CTL1 to CTL8 for causing the memory circuit 36 to perform a write operation to be described later, and output this to the memory circuit 36.
In addition, the decoder 41 generates control signals CTL 11, 12, 13, and 14 for causing the memory circuit 36 to perform a write operation to be described later, and outputs this to the memory circuit 36.

When the command COMMAND [7: 0] indicates reading, the decoder 41 controls the memory control circuits 45_1 to 45_8 so as to realize a reading operation from the memory card body 17.
In addition, the decoder 41 controls the input / output circuit 43 so that the data RDATA0 [7: 0] read from the memory card body 17 via the bus B_DIO is input via the input / output circuit 43.
The decoder 41 outputs the data RDATA0 [7: 0] read from the memory card body 17 to the 8-10 encode / PS conversion circuit 33 shown in FIG. 3 as read data RDATA [7: 0].

5 and 6 are configuration diagrams of the memory circuit 36 shown in FIG.
The memory circuit 36 is, for example, a flash memory.
As illustrated in FIG. 5, the memory circuit 36 includes, for example, a signal line 51, memories 53_1 to 53_8, and a signal line 55.
As shown in FIG. 6, the memory circuit 36 further includes SP conversion circuits 60_1, 60_2, 60_3, and 60_4.

The signal line 51 outputs control signals CTL1 to CTL8 from the memory control circuits 45_1 to 45_8 of the control circuit 35 illustrated in FIG. 4 to the memories 53_1 to 53_8, respectively.
The memories 53_1 to 53_8 receive the control signals CTL1 to CTL8 through the signal lines 51, respectively, and perform data writing and reading operations based on the control signals CTL1 to CTL8, respectively.
The memories 53_1 to 53_8 receive write data from the control circuit 35 via the SP conversion circuits 60_1 to 60_4 and the bus B_DIO.
Further, the memories 53_1 to 53_8 output the read data to the control circuit 35 via the bus B_DIO.
In the present embodiment, the bus B_DIO is shared between the memories 53_1 to 53_8.

The SP conversion circuits 60_1 to 60_4 take in the serial data transmitted through the bus B_DIO based on the control signals CTL11 to 14 input from the control circuit 35, respectively, and convert them into a parallel format.
At this time, the SP conversion circuits 60_1 to 60_4 take in the serial data, which is the write data sent to the bus B_DIO by the control circuit 35, in successive different time zones assigned to the SP conversion circuits 60_1 to 60_4. That is, only one SP conversion circuit among the SP conversion circuits 60_1 to 60_4 takes in the serial data from the bus B_DIO in each time zone.
In the write operation, the SP conversion circuit 60_1 converts write data, which is serial data transmitted through the bus B_DIO, into a parallel format, and writes the converted write data in the memories 53_1 and 53_2 in parallel.
In the write operation, the SP conversion circuit 60_2 converts the write data that is serial data transmitted through the bus B_DIO into a parallel format, and writes the converted write data in the memories 53_3 and 53_4 in parallel.
In the write operation, the SP conversion circuit 60_3 converts write data, which is serial data transmitted through the bus B_DIO, into a parallel format, and writes the converted write data in the memories 53_5 and 53_6 in parallel.
In the write operation, the SP conversion circuit 60_4 converts the write data, which is serial data transmitted through the bus B_DIO, into a parallel format, and writes the converted write data in the memories 53_7 and 53_8 in parallel.

FIG. 7 is a configuration diagram of the memory 53_1 shown in FIGS.
The memories 53_2 to 53_8 have the same configuration as the memory 53_1 except that the control signals CTL2 to CTL8 are input.
As shown in FIG. 7, the memory 53_1 includes, for example, a control circuit 61, an address register 63, a data register 66, a column buffer 67, a column decoder 68, a row address buffer 69, a row address decoder 70, a sense amplifier 71, and a memory cell array 72. And a high voltage generation circuit 73 and a status generation circuit 75.

The control circuit 61 controls writing and reading to the memory cell array 72 based on the control signal CTL1 input from the memory control circuit 45_1 shown in FIG.
The address register 63 is set with address data of a storage element that is accessed (read or written) in the memory cell array 72 by the control circuit 61.
Data written to the memory cell array 72 or data read from the memory cell array 72 is written to the data register 66.
During the write operation, the write data sent to the data register 66 from the input / output circuit 43 shown in FIG. 4 to the bus B_DIO and converted into the parallel format by the SP conversion circuit 60_1 is transferred.
At this time, in the decoder 41 shown in FIG. 4, the SP conversion circuits 60_1 to 60_4 take in the write data in consecutive different time zones by the control signals CTL11 to 14, convert them into the parallel format, and convert the memory 53_1 in the subsequent stage. To 53_8.
That is, the time period during which the SP conversion circuit 60_1 takes in the write data from the bus B_DIO is the register transfer time TR of the memories 53_1 and 53_2.
In addition, a time period during which the SP conversion circuit 60_2 takes in write data from the bus B_DIO is a register transfer time TR of the memories 53_3 and 53_4.
The time zone in which the SP conversion circuit 60_3 takes in the write data from the bus B_DIO is the register transfer time TR of the memories 53_5 and 53_6.
The time zone in which the SP conversion circuit 60_4 takes in the write data from the bus B_DIO is the register transfer time TR of the memories 53_7 and 53_8.

In the column buffer 67, data defining a column address of the memory cell array 72 among the address data stored in the address register 63 is read from the address register 63.
The column decoder 68 decodes the data read from the column buffer 67 and activates the data line to be read in the memory cell array 72.
The row address buffer 69 reads data defining the row address of the memory cell array 72 from the address register 63 among the address data stored in the address register 63.
The row address decoder 70 decodes the data read from the row address buffer 69 and activates the word line to be read in the memory cell array 72.
In the memory 53_1, the data stored in the data register 66 is written to the storage element defined by the data line and the word line activated by the column decoder 68 and the row address decoder 70 during the write operation.
In the memory 53_1, data is read from the storage element defined by the data line and the word line activated by the column decoder 68 and the row address decoder 70 to the data register 66 by the action of the sense amplifier 71 during the read operation.

At the time of reading, the sense amplifier 71 amplifies the potential of the word line corresponding to the storage data of the storage element defined by the activated data line and word line in the memory cell array 72 and stores it in the data register 66 as read data. Write.
The memory cell array 72 forms storage elements at matrix positions defined by word lines and data lines.
The high voltage generation circuit 73 supplies a driving voltage to the row address decoder 70, the sense amplifier 71, and the memory cell array 72.
The status generation circuit 75 generates a status signal STATUS indicating BUSY while the control circuit 61 writes data from the data register 66 to the memory cell array 72 and indicating READY in other time zones, and this is shown in FIG. Output to the control circuit 35.

The data processing system 10 is characterized in that the writing operation to the memories 53_1 to 53_8 in the memory card 3 is performed by pipeline processing in units of parallel writing to two memories.
In the pipeline processing, the control circuit 35 of the memory card 3 shown in FIG. 3, specifically, the decoder 41 shown in FIG. 4 controls the memories 53_1 to 53_8 shown in FIG. 5 and the SP conversion circuits 60_1 to 60_4 shown in FIG. Done.
Hereinafter, a process in which the decoder 41 writes write data for one block to the memory cell array 72 of the memories 53_1 to 53_8 will be described.
In the present embodiment, the block is a unit for performing the memory erasure process of the memory cell array 72 in each of the memories 53_1 to 53_8. One block is composed of a plurality of pages, for example, “4” pages. One page is 2048 bytes of data, for example.
In this embodiment, the number of pages constituting one block is also referred to as BLK. The number of memories 53_1 to 53_8 is also denoted as n. The number of memories 53_1 to 53_8 connected to each of the SP conversion circuits 60_1 to 60_4 is denoted as k. Here, in the following example, BLK = 4, n = 8, and k = 2.

That is, each of the control circuits 61 of the memories 53_1 to 53_8 performs storage erasure of storage areas corresponding to BLK pages in the memory cell array 72 based on the control of the decoder 41 (control signals CTL1 to CTL8, respectively) ( Memory erasure process). As a result, the entire memory 53_1 to 53_8 is erased from the storage area of n * BLK pages.
Specifically, the control circuit 61 writes a first logical value (for example, “1”) in a storage area corresponding to BLK pages in the memory cell array 72, and reads and verifies it. If it is determined that the erasure has failed in the verification, the erasure process is performed again. When the erasure fails, the status generation circuit 75 outputs a status signal STATUS indicating failure to the decoder 41 to the decoder 41 shown in FIG. On the other hand, if the erase is successful, the status generation circuit 75 outputs a status signal STATUS indicating success to the decoder 41 to the decoder 41 shown in FIG.
The maximum number of repetitions of the erasing process is defined in advance as a predetermined number (eg, “4”).
As described above, the time required for the memory erasing process by the decoder 41 depends on the number of times the erasing process is repeated and is uncertain. In the present embodiment, the time required when the erasing process is performed the maximum number of times is defined in advance as the one-block maximum erasing time TEmax, and this is assigned to the memory erasing process EP. The maximum erase time TEmax is, for example, 4 ms.

Next, the decoder 41 sends write data for two pages to the bus B_DIO via the FIFO circuit 42 and the input / output circuit 43.
At this time, the decoder 41 transfers two pages to the two memories 53_1 to 53_8 associated with the SP conversion circuit that takes in data from the bus B_DIO among the SP conversion circuits 60_1 to 60_4 during one register transfer time TR. Are sent to the bus B_DIO in a serial format.
Specifically, of the two memories 53_1 to 53_8, the decoder 41 alternately sends the page byte data transferred to one memory and the page byte data transferred to the other memory to the bus B_DIO.

Then, the SP conversion circuits 60_1 to 60_4 convert the serial data, which is the write data sent from the control circuit 35 to the bus B_DIO, into consecutive different time zones (register transfer time TR) assigned to each of the SP conversion circuits 60_1 to 60_4. Capture with. That is, the SP conversion circuits 60_1 to 60_4 take in the write data from the bus B_DIO in mutually different time zones.
The SP conversion circuit 60_x (x is an integer satisfying 1 ≦ x ≦ 4) that takes in the write data from the bus B_DIO converts the fetched write data into a parallel format, and performs two writes for each converted page. The data is output to each of the two memories 53_y (y is an integer satisfying 1 ≦ y ≦ 8) connected to the SP conversion circuit 60_x.
The memory 53_y transfers write data for one page input from the SP conversion circuit 60_x to the data register 66 by the control circuit 61 illustrated in FIG.
In the present embodiment, the process in which the control circuit 35 sends write data to the bus B_DIO and writes it to the data register 66 of the corresponding memory 53_x is referred to as register transfer process. The time required for the register transfer process is fixed, and is described as a register transfer time TR (a time zone of the first time length of the present invention).
In the decoder 41, the SP conversion circuits 60_1 to 60_4 take in the write data from the bus B_DIO and transfer them to the data registers 66 of the subsequent memories 53_1 to 53_8 in different time zones each having a register transfer time TR. The control signals CTL1 to 8 and CTL11 to 14 are generated.
As a result, as shown in FIG. 8, the register transfer processing RP for the memories 53_1 and 53_2 is performed in the same time zone, the register transfer processing RP for the memories 53_3 and 53_4 is performed in the same time zone, and the registers for the memories 53_5 and 53_6 are performed. The transfer process RP is performed in the same time zone, and the register transfer process RP for the memories 53_7 and 53_8 is performed in the same time zone.
In FIG. 8, P (number) indicates a page transferred during each register transfer time TR.

Next, the decoder 41 controls the memories 53_1 to 53_8 so that each control circuit 61 reads out the write data from the data register 66 and writes it into the memory cell array 72 (program processing).
For each of the memories 53_1 to 53_8, the decoder 41 writes the data read from the data register 66 to the storage elements for the designated page of the memory cell array 72, and reads and verifies the data. If it is determined that writing has failed in the verification, the writing process is performed again. The maximum number of repetitions of the writing process is defined in advance (for example, “7”). When writing fails, the status generation circuit 75 outputs a status signal STATUS indicating failure to the decoder 41 to the decoder 41 shown in FIG. On the other hand, if the writing is successful, the status generation circuit 75 outputs a status signal STATUS indicating success to the decoder 41 to the decoder 41 shown in FIG.
In the present embodiment, the time required for the program process PP by the decoder 41 depends on the number of repetitions of the write process and is uncertain. In the present embodiment, the time required when the write process is performed the maximum number of times is defined in advance as the maximum program time TPmax (second time length of the present invention), and this is assigned to the program process PP. The maximum program time TPmax is 700 μs, for example.

As shown in FIG. 8, the decoder 41 shown in FIG. 4 assigns the maximum erase time TEmax to the memory erase process for each of the memories 53_1 to 53_8 shown in FIGS. Is assigned a register transfer time TR, and a maximum program time TPmax is assigned to program processing.
Further, as described above, the decoder 41 controls the SP conversion circuits 60_1 to 60_4 to take in the write data from the bus B_DIO in consecutive different time zones each having the register transfer time TR, as shown in FIG. To do.
Further, for example, as shown in FIG. 8, the decoder 41 performs the register transfer process RP within the register transfer time TR assigned to each of the memories 53_1 to 53_8, and subsequently performs the program process PP after the end. Thus, the memory control circuits 45_1 to 45_8 are controlled.
In addition, the decoder 41 controls the memory control circuits 45_1 to 45_8 to start the next register transfer process RP when the maximum program time TPmax elapses after the program process PP is started.
When the decoder 41 starts the program process PP after the end of the register transfer process RP four times in succession, the decoder 41 performs the memory erase process EP after the end of the maximum program time TPmax after the start of the fourth program process PP. .

As a result, the decoder 41 can perform pseudo-pipeline processing between the memory erase circuit EP and the program process PP between the memory control circuits 45_1 to 45_8.
That is, under the control of the decoder 41 described above, as shown in FIG. 8, during the write operation, data for one page is transferred from the control circuit 35 shown in FIG. 3 to the memories 53_7 and 53_8 shown in FIGS. Immediately after this, the control circuit 35 can transfer the data for one page to the memories 53_1 and 53_2, and no waiting time due to the program processing PP occurs from the viewpoint of the control circuit 35.

Hereinafter, a case where data for one block is written in the memory circuit 36 after the memory erasing process EP will be considered.
In this case, there is no waiting time due to the program processing PP, so that one page is viewed from the control circuit 35 shown in FIG. 3 until the next storage erasure processing EP is started after the storage erasure processing EP is started. The time interval (hereinafter also referred to as the minimum data arrival interval) Ta at which the data can be written in the memory circuit 36 is expressed by the following equation (1).

[Equation 1]
Ta = (BLK * TR + TEmax) / (k * BLK)
... (1)

  Since the waiting time due to the program processing PP does not occur due to the pipeline processing, TPmax does not appear in the equation (1). In the above-described embodiment, since BLK = 4 and k = 2, according to the above equation (1), the minimum data arrival time interval Ta is represented by the following equation (2).

[Equation 2]
Ta = (4 * TR + TEmax) / (2 * 4)
... (2)

In an actual flash memory, for example, BLK = 64. By connecting these two in parallel, the waiting time due to the program processing PP is eliminated as seen from the control circuit 35.
In this case, when TR = 0.1 ms, TPmax = 0.3 ms, and TEmax = 4 ms, the minimum data arrival time interval Ta is 0.081 ms.
The write rate RATE from the control circuit 35 to the memory circuit 36 is defined by the following equation (3).
In the following formula (3), PAGE indicates the bit amount of one page (2048 * 8 = 16384 bits).

[Equation 3]
RATE = PAGE / Ta
... (3)

  Further, when the memory erasing process EP is performed in advance, the minimum data arrival time interval Ta is obtained by dividing the register transfer time TR by the parallel number k. Therefore, when two memories 53_1 to 53_8 are connected in parallel, Ta = TR / 2 = 0.05 ms and RATE = 328 Mbs.

<Example of Overall Operation of Data Processing System 10>
Hereinafter, an example of the overall operation when data is written from the computer 2 to the memory card 3 in the data processing system 10 will be described.
Data generated by the signal processing circuit 11 of the computer 2 shown in FIG. 1 performing predetermined processing is output to the reader / writer 13 via the PCI bus.
Based on the data input from the signal processing circuit 11, the reader / writer 13 uses the memory card 3 via the interface 14 as a command ENC_CMD [7: 0] indicating writing, write data ENC_DATA [7: 0], and data WR_DATA. Output to.
Further, the computer 2 outputs a clock signal SCLK to the memory card 3.

The memory card 3 receives the data WR_DATA and the clock signal SCLK input from the computer 2 through the interface 16 and outputs them to the memory card body 17.
Then, the following processing is performed in the memory card main body 17 shown in FIG.

The clock frequency dividing circuit 31 divides the clock signal SCLK input via the interface 16 to generate a clock signal PCLK, which is converted into an SP conversion / 8-10 decode circuit 32 and an 8-10 encode / PS conversion circuit 33. To the error detection circuit 34 and the control circuit 35.
The SP conversion / 8-10 decode circuit 32 converts the data WR_DATA input via the interface 16 from the serial format to the parallel format, and then converts the data to the original 8 bits to convert the data DATA8 [7: 0]. It is generated and output to the error detection circuit 34.
When the data DATA [7: 0] input from the SP conversion / 8-10 decode circuit 32 is the command ENC_CMD [7: 0], the error detection circuit 34 converts the data DATA [7: 0] into the command COMMAND [7: 0]. To the control circuit 35.
Further, when the data DATA [7: 0] input from the SP conversion / 8-10 decode circuit 32 is the write data ENC_DATA [7: 0], the error detection circuit 34 writes the write data WDATA [7: 0] to the control circuit 35.
Further, the error detection circuit 34 detects data ECC_SYNC [7: 0], which is a syndrome of the data DATA [7: 0] input from the SP conversion / 8-10 decode circuit 32, and outputs this to the control circuit 35. .
Further, the error detection circuit 34 detects data CRCC_SYNC [7: 0], which is a syndrome of the data DATA [7: 0] input from the SP conversion / 8-10 decoding circuit 32, and outputs this to the control circuit 35. .

  Then, the control circuit 35 controls the memory circuit 36 so that the operation described above with reference to FIGS. 5 to 8 is performed in the memory circuit 36 according to the command COMMAND [7: 0] indicating writing.

As described above, according to the data processing system 10, as shown in FIGS. 3 and 6, the bus B_DIO used for data transfer between the control circuit 35 and the memory circuit 36 is used as the memory 53_1 in the memory circuit 36. Shared by ~ 53_8. Therefore, compared with the case where the bus is not shared, the number of pins of the interface 16 shown in FIG. 1 can be reduced and the scale can be reduced.
Further, according to the data processing system 10, as described with reference to FIGS. 6 and 8, the control circuit 35 sends write data for two pages to the bus B_DIO within each register transfer time TR. Then, the SP conversion circuits 60_1 to 60_4 take in serial data, which is write data sent to the bus B_DIO by the control circuit 35, in consecutive different time zones assigned to the SP conversion circuits 60_1 to 60_4. That is, only a single SP conversion circuit among the SP conversion circuits 60_1 to 60_4 takes in serial format write data from the bus B_DIO in each time slot. Thereafter, the SP conversion circuits 60_1 to 60_4 convert the fetched write data into a parallel format and transfer the converted data to the data registers 66 of the subsequent memories 53_1 to 53_8 in parallel.
As a result, as shown in FIG. 8, the data processing system 10 sets the two memories 53_1 to 53_8 as a set, performs the register transfer processing RP of the two memories belonging to the set within the register transfer time TR, and performs the register transfer processing. The program processing PP is started immediately after RP, and the next set of register transfer processing RP is performed after the lapse of the maximum program time TPmax, thereby eliminating the waiting time for writing to the memory circuit 36 as seen from the control circuit 35 shown in FIG. Can do.

  In other words, as described above, after executing register transfer processing for all of the plurality of flash memories in different time zones, program processing for the plurality of flash memories is started simultaneously, and register transfer is performed after the maximum program time has elapsed. Since the process has been performed again, the electronic device cannot transfer the write data to the semiconductor memory device during the maximum program time until the program process is completed (the register transfer process cannot be performed). On the other hand, the data processing system 10 described above can improve the responsiveness of the write operation as compared with the conventional case by performing the write operation described above.

The present invention is not limited to the embodiment described above.
In the above-described embodiment, as illustrated in FIG. 5, the case where the memory circuit 36 includes eight memories 53_1 to 53_8 is illustrated. However, the number n of memories included in the memory circuit 36 is expressed by the following equation (4). If it satisfies, it will not be specifically limited.

[Equation 4]
n ≧ (TR + TPmax) / TR
(4)

By defining the number n of memories included in the memory circuit 36 as in the above equation (4), when the bus B_DIO shown in FIGS. 3, 4, and 5 is shared by the n memories, the program processing PP Compared to the conventional method in which the timing of starting the program processing is the same for all the memories, the timing of starting the program processing PP can be advanced in (n−1) memories.
Here, when “n = (TR + TPmax) / TR” is the best mode and “n> (TR + TPmax) / TR”, register transfer processing via the bus B_DIO becomes a bottleneck, and “n = (TR + TPmax) / TR "and the response at the time of writing viewed from the computer 2 are the same.

In the above-described embodiment, each of the SP conversion circuits 60_1 to 60_4 writes data in the two memories 53_1 to 53_8 in parallel (when k = 2). However, the SP conversion circuits include three or more SP conversion circuits. Data may be written to the memory. That is, k ≧ 3 may be satisfied.
Further, the number of memories for writing data in parallel may be different among a plurality of SP conversion circuits.

Hereinafter, the description of the memory card main body 17 shown in FIG. 3 will be supplemented.
When flash memories are used as the memories 53_1 to 53_8, a defective block exists in the memory cell array 72 from the time of shipment, and an alternative block is used. Therefore, a logical address and a memory cell array used by the computer 2 (user) shown in FIG. The physical address on 72 does not match and a conversion table for converting the address is required. Address conversion using such a conversion table is called logical physical address conversion. The control circuit 35 shown in FIG. 3 performs the logical-physical address conversion. The logical / physical address conversion may be performed by the computer 2 instead of the memory card 3.
Further, the memory element of the memory cell array 72 has a finite number of rewrites because its storage characteristics gradually deteriorate when rewrite is repeated. Therefore, it is necessary to perform management (wear leveling processing) so that only the same block is not rewritten and to equalize it. Further, since a read error occurs, error correction is necessary. The control circuit 35 shown in FIG. 3 performs such wear leveling processing and error correction processing.

The error correction performed by the control circuit 35 uses, for example, an error correction code called “Simple ECC”, for example, a Hamming code. Further, the control circuit 35 may use a code capable of multiple correction of byte errors, such as a Reed-Solomon code, as the error correction code.
That is, the control circuit 35 uses an error correction code that covers all of these error factors, using an advanced error correction code, an initial failure block, a block that deteriorates with time, a read error, a lack of time for reading and writing, Error correction of writing and reading to the memories 53_1 to 53_8 which are flash memories is performed.
In this case, there is an advantage that initial defective block detection of the memory cell array 72, logical / physical address conversion, wear leveling processing, and write / erase status monitoring are not required.
Note that this method is particularly effective when the data processing system 10 handles only data having a large unit size, such as image data, because a highly functional error correction code can be easily formed.

  The present invention can be applied to a system that performs a write operation on a plurality of memories each including a register and a storage area in which data read from the register is written.

FIG. 1 is an overall configuration diagram of a data processing system. FIG. 2 is a block diagram of the reader / writer shown in FIG. FIG. 3 is a block diagram of the memory card body shown in FIG. FIG. 4 is a block diagram of the control circuit shown in FIG. FIG. 5 is a block diagram of the memory circuit shown in FIG. FIG. 6 is a block diagram of the memory circuit shown in FIG. FIG. 7 is a configuration diagram of the memory shown in FIGS. 5 and 6. FIG. 8 is a diagram for explaining a process in which the decoder shown in FIG. 4 writes the write data to the memory shown in FIG. 5 under the control of the control circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2 ... Computer, 3 ... Memory card, 11 ... Signal processing circuit, 13 ... Reader / writer, 14 ... Interface, 16 ... Interface, 17 ... Memory card main body, 21 ... SP conversion / 8-10 decoding circuit, 22 ... ECC decoder 23 ... Bus interface, 24 ... CRCC encoder, 25 ... ECC encoder, 26 ... Switch, 27 ... 8-10 encoding / PS conversion circuit, 31 ... Clock frequency division circuit, 32 ... SP conversion / 8-10 decoding circuit, 33 ... 8-10 encoding / PS conversion circuit, 34 ... error detection circuit, 35 ... control circuit, 36 ... memory circuit, 41 ... decoder, 42 ... FIFO circuit, 43 ... input / output circuit, 45_1 to 45_8 ... memory control circuit, 51 ... Signal line, 53_1 to 53_8 ... Memory, 55 ... Signal line, 60_1 to 60_4 ... SP Conversion circuit 61 ... Control circuit 63 ... Address register 66 ... Data register 67 ... Column buffer 68 ... Column decoder 69 ... Row address buffer 70 ... Row address decoder 71 ... Sense amplifier 72 ... Memory cell array 73 ... high voltage generation circuit, 75 ... status generation circuit, B_DIO ... bus

Claims (8)

A plurality of memories each having a register and a memory area;
An interface for entering data;
Each of the plurality of memories is caused to perform a register transfer process for transferring data input from the interface to the register of the memory and a memory write process for reading the data from the register and writing the data to the memory area. Control circuit and
When the control circuit defines a plurality of the sets including one or a plurality of the memories so that each does not overlap with another set, the control circuit continuously and differently inputs the data input from the interface with the same first time length. Outputting to each of the plurality of sets in a time zone, causing the memory to perform the register transfer processing for transferring the output data in parallel to the registers of the plurality of memories included in the same set, The memory writing process is started in the memory continuously after the elapse of a time zone, and the next register transfer process is continued after the elapse of a second time length defined in common for the plurality of memories for the memory writing process. A storage device for causing the memory to perform. A plurality of conversion circuits provided corresponding to each of the plurality of sets, converting serial format data input via the interface into parallel format, and outputting in parallel to the plurality of memories included in the set The storage device according to claim 1, further comprising: A bus that is shared by the plurality of conversion circuits and transmits data input through the interface to the plurality of conversion circuits;
3. The serial format data transmitted through the bus in the first time zone is input to the single conversion circuit associated with the first time zone and converted into the parallel format. 4. Storage device. The storage device according to claim 3, wherein the bus transmits data to be written by the memory write process once in the plurality of memories included in the single set in the first time zone. The control circuit writes the data read from the register to the memory area, reads the written data from the memory area, compares the data read from the register with the data read from the memory area, and When the writing to the memory area is inappropriate, the memory is controlled to perform the memory writing process by rewriting the data read from the register to the memory area. The second time length is It is the maximum time length allocated in advance for the memory writing process,
The storage device according to claim 1, wherein the number n of the plurality of memories is an integer equal to or greater than a value obtained by dividing the sum of the first time length and the second time length by the first time length. The control circuit causes the plurality of memories to perform the register transfer processing of data for a total of n pages in a continuous time zone composed of the time zones assigned to the plurality of sets,
The register transfer process and the memory write process are performed on the predetermined BLK * n pages to the plurality of memories, and the first page allocated to the memory write process of the last page of the BLK * n pages is performed. After the elapse of the time length of 2, the memory erasure process for the BLK * n pages in total for the memory areas of the plurality of memories is performed on the plurality of memories, and the memory erasure process previously assigned to the memory erasure process is performed. The storage device according to claim 1, wherein the register transfer process is started in the memory after the elapse of 3 time. A storage device;
A data processing system having a data processing device for writing data to the storage device,
The storage device
A plurality of memories each having a register and a memory area;
An interface for inputting data to be written from the data processing device;
Each of the plurality of memories is caused to perform a register transfer process for transferring data input from the interface to the register of the memory and a memory write process for reading the data from the register and writing the data to the memory area. Control circuit and
When the control circuit defines a plurality of the sets including one or a plurality of the memories so that each does not overlap with another set, the control circuit continuously and differently inputs the data input from the interface with the same first time length. Outputting to each of the plurality of sets in a time zone, causing the memory to perform the register transfer processing for transferring the output data in parallel to the registers of the plurality of memories included in the same set, The memory writing process is started in the memory continuously after the elapse of a time zone, and the next register transfer process is continued after the elapse of a second time length defined in common for the plurality of memories for the memory writing process. A data processing system for causing the memory to perform. Each of a plurality of memories each having a register and a memory area and sharing an interface transfers a data input via the interface to the register of the memory, and reads the data from the register And a memory control method for performing a memory write process for writing to the memory area,
When a plurality of the sets including one or more of the memories are defined so that each does not overlap with another set,
Data input from the interface is output to each of the plurality of sets in different time zones having the same first time length, and the output data is stored in the registers of the plurality of memories included in the same set A first step of causing the memory to perform the register transfer process of transferring in parallel with
A second step of causing the memory to start the memory write processing after the time period has elapsed since the start of the register transfer processing in the first step;
A third step of causing the memory to perform the next register transfer processing after the second time length defined in common for the plurality of memories has elapsed since the memory writing processing was started in the second step. And a storage control method.

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