TWI835027B - Method and computer program product and apparatus for updating host-to-flash address mapping table - Google Patents

Abstract

The invention is related to a method, a computer program product, and an apparatus for updating a Host-to-Flash address mapping (H2F) table. The method includes: allocating apace in a random access memory (RAM) for a first H2F sub-table, and for intermediary information for updating a second H2F sub-table stored in a flash module; when executing a host write command for programming data into the flash module, or when executing a host discard command for discarding data from the flash module, updating the first H2F sub-table and the intermediary information stored in the RAM; and in a table update procedure, programming the first H2F sub-table temporarily stored in the RAM into a system block of the flash module, and updating the second H2F sub-table according the intermediary information temporarily stored in the RAM, and programming updated second H2F sub-table into the system block of the flash module.

Description

Methods and computer program products and devices for updating host and flash memory address comparison tables

The present invention relates to storage devices, and in particular, to a method, computer program product and device for updating a host and flash memory address comparison table.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processor (Host) can provide any address to access the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in a timely manner. material. On the contrary, NAND flash memory does not have random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write a sequence of Bytes values into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory).

In order to improve the data writing and reading performance of the flash memory module, the flash memory controller performs data writing and reading in parallel through multiple channels. In order to achieve the purpose of parallel processing, a continuous piece of data will be distributed and stored in the flash memory units connected to multiple channels, and recorded using the Host-to-Flash Address Mapping Table (H2F table). The correspondence between the logical address of user data (managed by the host) and the physical address (managed by the flash controller). However, the update of the H2F table also affects the overall system performance. Therefore, the present invention proposes a method, product computer program and device for updating the address comparison table between the host and the flash memory, so as to improve the overall performance of the system.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

This description relates to a method for updating a host and flash memory address comparison table, which is executed by a processing unit and includes: configuring space in a random access memory for the first host and flash memory address comparison table, and updating the flash memory model. The intermediate information of the second host in the group and the flash memory address comparison table; when executing a host write command to write data to the flash memory module or executing a host discard command to discard data in the flash memory module , update the first host and flash memory address comparison sub-table and the intermediate information temporarily stored in the random access memory; and in the table update procedure, update the temporarily stored in the random access memory The first host and flash memory address comparison table is written into the system block in the flash memory module, and the second host and flash memory address are updated based on the intermediate information temporarily stored in the random access memory. Compare the sub-table and write the updated second host and flash memory address comparison sub-table into the system block in the flash memory module.

This manual also relates to a computer program product, including program code. When the processing unit executes the program code, the above-mentioned method of updating the host and flash memory address comparison table is implemented.

This specification further relates to a device for updating a host and flash memory address comparison table, including: a random access memory; a flash memory interface; and a processing unit. The flash memory interface is coupled to the flash memory module, and the processing unit is coupled to the random access memory and the flash memory interface. The processing unit is configured to configure space in the random access memory for the first host and flash memory address comparison sub-table, and to update the second host and flash memory address comparison sub-table in the flash memory module. Intermediate information; when executing a host write command to write data to the flash memory module or executing a host discard command to discard data in the flash memory module, update all temporarily stored data in the random access memory The first host and flash memory address comparison subtable and the intermediate information; and in the table update procedure, write the first host and flash memory address comparison subtable temporarily stored in the random access memory. The system block in the flash memory module updates the second host and flash memory bits according to the intermediate information temporarily stored in the random access memory. The address comparison subtable is generated and the updated second host and flash memory address comparison subtable are written into the system block in the flash memory module.

One of the advantages of the above embodiment is that by checking random write conditions, it is possible to avoid delaying the execution of subsequent host read commands and/or host write commands due to a large number of host and flash memory address comparison subtable updates.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

10: Electronic devices

110: Host side

130:Flash controller

131:Host interface

132:Bus

134: Processing unit

136: Random access memory

138: Direct Memory Access Controller

139:Flash memory interface

150:Flash memory module

151:Interface

153#0~153#15: NAND flash memory unit

CH#0~CH#3: Channel

CE#0~CE#3: enable signal

310,330: Data plane

310#0~310#m,330#0~330#m: solid block

P#0~P#n: Entity page

410: Advanced comparison table

430#0~430#15:H2F subtable

510: Sections in entity pages

530:Physical address information

530-0: Entity block number

530-1: Entity page number and section number within it

S610~S660: Method steps

S710~S740: Method steps

S810~S840: Method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a NAND flash memory unit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the association between the high-level comparison table and the host and flash memory address comparison sub-table according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of the association between the host and the flash memory address comparison subtable and the physical page according to an embodiment of the present invention.

Figure 6 is a flow chart of a method for executing a host write command according to an embodiment of the present invention.

Figure 7 is a flow chart of a method for executing a host discard command according to an embodiment of the present invention.

FIG. 8 is a flowchart of a method for executing a table update program according to an embodiment of the present invention.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate priority, precedence, or precedence between them. It is the time sequence in which one component precedes another, or the execution of method steps. It is only used to distinguish components with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The host interface (Host Interface) 137 between the host 110 and the flash controller 130 can be a Universal Serial Bus (USB), an advanced technology attachment (ATA), or a serial advanced technology attachment (ATA). Communication protocols such as SATA), peripheral component interconnect express (PCI-E), Universal Flash Storage (UFS), and embedded multi-media card (eMMC) communicate with each other. The flash interface (Flash Interface) 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other using a double data rate (Double Data Rate, DDR) communication protocol, such as Open NAND Flash (Open NAND Flash Interface, ONFI), dual Double data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware instructions, the functions described later are provided. The processing unit 134 receives host commands, such as read commands, through the host interface 131 (Read Command), Write Command (Write Command), Discard Command (Discard Command), Erase Command (Erase Command), etc., schedule and execute these commands. The flash memory controller 130 also includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, is used to configure space as a data buffer to store user data (also called host data) read from the host 110 and about to be written to the flash memory module 150, and from the flash memory module. The group 150 reads and outputs the user data to the host 110 . The random access memory 136 can also store data needed during execution, such as variables, data tables, host-to-Flash Address Mapping Table (H2F table for short), flash memory and host addresses. Comparison table (Flash-to-Host Address Mapping Table, referred to as F2H table), etc. The flash memory interface 139 includes a NAND Flash Controller (NFC), which provides functions required to access the flash memory module 150, such as a command sequencer (Command Sequencer) and a low density parity check (LDPC). wait.

The flash memory controller 130 can be configured with a bus architecture (Bus Architecture) 132 for coupling components to each other to transmit data, addresses, control signals, etc. These components include the host interface 131, the processing unit 134, the RAM 136, Direct Memory Access (DMA) controller 138, flash memory interface 139, etc. In some embodiments, the host interface 131, the processing unit 134, the RAM 136, the DMA controller 138, and the flash memory interface 139 may be coupled to each other through a single bus. In other embodiments, the flash memory controller 130 may be configured with a high-speed bus for coupling the processing unit 134, the DMA controller 138 and the RAM 136 to each other, and a low-speed bus may be configured for the processing unit 134, the DMA The controller 138, the host interface 131 and the flash memory interface 139 are coupled to each other. The DMA controller 138 can move data between components through the bus architecture 132 according to the instructions of the processing unit 134, for example, transferring special data in the host interface 131 or the flash memory interface 139. The data in the specific data buffer (Data Buffer) is moved to a specific address in the RAM 136, and the data in the specific address in the RAM 136 is moved to a specific data register in the host interface 131 or the flash memory interface 139, etc.

The bus includes parallel physical lines that connect two or more components in the flash memory controller 130 . The bus is a shared transmission medium. At any time, only two devices can use these lines to communicate with each other and transfer data. Data and control signals can propagate in both directions between components along data and control lines respectively, but on the other hand, address signals can only propagate in one direction along address lines. For example, when the processing unit 134 wants to read data at a specific address of the RAM 136, the processing unit 134 transmits the address to the RAM 136 on the address line. Then, the data at this address will be returned to the processing unit 134 on the data line. In order to complete the data reading operation, control signals are transmitted using control lines.

The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (GB) or even several terabytes (TB), for storing a large amount of user data. For example, high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array may include Single Level Cells (SLCs), Multiple Level Cells (MLCs), or Triple Level Cells (Triple Level Cells). Level Cells (TLCs), Quad-Level Cells (QLCs), or any combination of the above. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and reads user data from a specified address (source address) in the flash memory module 150. The flash memory interface 139 uses several electronic signals to coordinate the transmission of data and commands between the flash memory controller 130 and the flash memory module 150, including data lines (Data Line), clock signals (Clock Signal) and control signals (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory units, for example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11. , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in a parallel manner, or write user data to the enabled NAND flash memory unit.

Each NAND flash memory unit can include multiple data planes (Data Planes), each data plane can include multiple physical blocks (Physical Blocks), and each physical block can include multiple physical pages (Physical Pages). Referring to the embodiment of FIG. 3 , NAND flash memory cell 153#0 includes two data planes 310 and 330 . Data plane 310 includes physical blocks 310#0 to 310#m, and data plane 330 includes physical blocks 330#0 to 330#m. Each entity block contains n+1 entity pages. NAND flash memory cells, physical blocks and physical pages can be identified using logical block number (LUN), block number (Block Number) and page number (Page Number) respectively, and any combination of the above numbers can be called a flash memory module 150's physical address.

Each entity block can be divided into a data block (Data Block), current block (Current block) or system block (System block) according to its function. The processing unit 134 may select an empty physical block for each plane in each NAND flash memory unit as the current block for preparing to write the user data received from the host 110 . In order to improve the efficiency of data writing, the user data provided by the host 110 can be written in parallel to specific pages in multiple current blocks of multiple planes in multiple NAND flash memory cells. The processing unit 134 may maintain the F2H table of each current block in the RAM 136, including a plurality of records, and store the information of the logical address to which the user data of each page in the current block is associated in the order of the page number. The logical address can use the logical block address (Logical Block Address, LBA), host page number (Host Page Number) or other means, managed by the host side 110. For example, each logical block address is associated with 512B of user data, and each master page number is associated with 4KB of user data. After all pages in a current block are filled with user data, or after the remaining pages in a current block are filled with false values, the processing unit 134 can drive the flash memory interface 139 to write the corresponding F2H table in the RAM 136 into the current block. The specified page (such as the last page), or the empty page in other specified entity blocks. After the corresponding F2H table has been written into the flash memory module 150, the current block is changed into a data block. In other words, the user data stored therein will not change. Then, the processing unit 134 may select another empty physical block as a new current block. In addition, the processing unit 134 can set a specific physical block as a system block for storing management information, such as a flash identifier (Flash Identifier, ID), bad block table (Bad Block Table), bad row table (Bad Column Table), H2F table etc. The F2H table can also be called the Physical-to-Logical Address Mapping Table (P2L table for short), and the H2F table can also be called the Logical-to-Physical Address Mapping Table (Logical-to-Physical Address Mapping Table, referred to as L2P table).

In addition to writing the F2H table to the corresponding physical page in the flash memory module 150, the processing unit 134 also needs to update the H2F table according to the content of the F2H table of the current block, so that when executing the host read command in the future, the user data associated with a specific logical address can be quickly found from the H2F table. The H2F table contains multiple records, storing information about which physical address the user data of each logical address is actually stored in according to the order of the logical addresses. However, since RAM 136 cannot provide enough space to store the entire H2F table for the processing unit 134 to quickly search in the future during data reading operations, the H2F table can be divided into multiple H2F sub-tables and stored in the flash memory module 150, so that in the future during data reading operations, only the corresponding H2F sub-table needs to be read from the flash memory module 150 to RAM 136. Referring to FIG. 4, the entire H2F table can be divided into H2F sub-tables 430#0~430#15. The processing unit 134 further maintains a high-level lookup table 410, which includes multiple records, storing the physical address information of the H2F sub-table associated with each logical address segment in the order of the logical address. For example, the H2F sub-table 430#0 associated with the 0th to 4095th main pages is stored in the 0th physical page in a specific physical block of a specific LUN (the letter "Z" may represent the number of the LUN and the physical block), and the H2F sub-table 430#1 associated with the 4096th to 8191th main pages is stored in the 1st physical page in a specific physical block of a specific LUN, and so on. Although FIG. 4 only includes 16 H2F sub-tables, a person skilled in the art may set more H2F sub-tables according to the capacity of the flash memory module 150, and the present invention is not limited thereto.

The space required for each H2F subtable can be 4KB, 8KB, 16KB, 32KB, etc. Refer to Figure 5. For example, the H2F subtable 430#0 stores the physical location information corresponding to each logical location in the order of logical addresses. The logical location can be represented by a main page number. Each main page number corresponds to a fixed-size physical storage space, such as 4KB. Those skilled in the art also use LBA to represent logical locations, and the present invention is not limited thereby. For example, H2F subtable 430#0 stores entity address information from H#0 to H#4095 in sequence. The physical address information 530 can be represented by four bytes: the first two bytes 530-0 record the physical block number (Physical Block Number); the last two bytes 530-1 record the physical page number (Physical Page Number) and the segment number in the entity page. For example, the physical address information 530 corresponding to the main page H#2 may point to the physical page 510 in the physical block 310#1. Byte 530-0 records the number of the physical block 310#1, and byte 530-1 records the number of the physical page and the section 510 therein.

After executing the host write command to write user data to the flash memory module 139, or executing the host discard command (Host Discard Command) to discard the data at a specific logical address stored in the flash memory module 139, the corresponding H2F The subtable needs to be updated accordingly so that subsequent data reading operations can be performed efficiently. Different from the execution of the host erase command, the processing unit 134 does not need to erase the memory unit that originally stored the data at the specific logical address when executing the host discard command. In some system architectures, RAM 136 may be configured with enough space to temporarily store all H2F subtables. Whenever the processing unit 134 drives the flash memory interface 139 to write user data, or when the flash memory module 139 stores After the stored data at a specific logical address is discarded, the contents of the corresponding H2F subtable can be updated to reflect the previous write or discard operation. At regular intervals or when preset conditions are met, the processing unit 134 drives the flash memory interface 139 to write all H2F subtables in the RAM 136 to the designated system block of the flash memory module 150 . However, in other system architectures, RAM 136 cannot be configured with enough space to temporarily store all H2F subtables. Therefore, the processing unit 134 can only temporarily store the F2H table in the RAM 136 which requires much less space. Whenever all the pages in a current block are filled with user data, or after the remaining pages in a current block are filled with false values, the processing unit 134 updates the corresponding H2F table according to the contents of the F2H table of the current block. Whenever a preset number of host discarding commands are executed, the processing unit 134 updates the corresponding H2F table to reflect the previous discarding operations. Since the previously executed host write command and host discard command may involve multiple H2F sub-tables, in detail, the processing unit 134 first searches the contents of the high-level lookup table 410 to find the entity address associated with the H2F sub-table, and The driver flash memory interface 139 reads the associated H2F subtable from these physical addresses of the flash memory module 150 and stores it in the RAM 136 . Next, the processing unit 134 updates the physical address information of the associated record of the H2F subtable in the RAM 136 based on the contents of the F2H table of the current block and the previously discarded logical address, and drives the flash memory interface 139 to write the updated H2F subtable to Designated system block of flash memory module 150 . However, in the above embodiment, when the host side 110 performs random write (Random Write), the execution of subsequent host read commands and/or host write commands is delayed due to too many H2F subtables that need to be updated. To make matters worse, the subsequent host write command may time out due to waiting for a long time for the H2F subtable to be updated, causing the host 110 to spend time and computing resources to regenerate and transmit the host write command to the flash memory controller 130 .

In order to solve the problems of the above embodiments, the present invention proposes a method, computer program product and device for updating the host and flash memory address comparison table, configuring space in the RAM 136 for several H2F sub-tables, and updating the flash memory. Intermediate information for other H2F subtables in module 150. In some embodiments, the system architecture may be configured with enough space for RAM 136 to temporarily store the current block's F2H table and a portion of the H2F sub-table. In other embodiments, The system architecture can be configured with enough RAM 136 to temporarily store the discard queue and a portion of the H2F subtable. In still other embodiments, the system architecture may be configured with enough space for RAM 136 to temporarily store the F2H table of the current block, the discard queue, and a portion of the H2F sub-table. The number of temporarily stored H2F sub-tables mentioned above depends on the size of the configuration space in RAM 136. When executing a host write command to write data to the flash memory module 150 or executing a host discard command to discard data in the flash memory module 150, the H2F subtable and intermediate information temporarily stored in the RAM 136 are updated. In the table update procedure (Table Update Procedure), the H2F subtable temporarily stored in the RAM 136 (which can be called the first H2F subtable) is written into the designated system block in the flash memory module 150. According to the temporarily stored in the RAM 136 The intermediate information updates the H2F subtable in the flash memory module 150 (which may be called the second H2F subtable) and writes the updated H2F subtable into the designated system block in the flash memory module 150 .

The embodiment of the present invention proposes a method for executing a host write command, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method updates the H2F subtable temporarily stored in RAM 136 and the F2H of the current block after each execution of the host write command, which is used to store the latest comparison information between logical and physical addresses and the update of the H2F subtable. condition. Referring to Figure 6, the detailed steps are as follows:

Step S610: Execute the first (next) host write command. The processing unit 134 can drive the flash memory interface 139 to write the user data of the host 110 to the specified page of the current block in the flash memory module 150 according to the parameters of the host write command (including logical address, length, etc.).

Step S620: Update the F2H table of the current block temporarily stored in the RAM 136 to store the comparison information corresponding to the logical address of the written page in the current block.

Step S630: Determine whether the H2F subtables associated with these logical addresses are temporarily stored in the RAM 136. If yes, the flow continues with the processing of step S640; otherwise, the flow continues with the processing of step S660.

Step S640: Update the H2F subtable temporarily stored in RAM 136 for storing comparison information of which physical addresses these logical addresses correspond to.

Step S650: Set the update flag (Update Flag) of the corresponding record in the F2H table temporarily stored in RAM 136 to "1".

Step S660: Set the update flag of the corresponding record in the F2H table temporarily stored in RAM 136 to "0".

第一至第三筆紀錄指出當前塊的頁面P#0至P#2分別儲存了邏輯位址LBA#64~95(也就是主頁面H#2)、LBA#96~127(也就是主頁面H#3)和LBA#128~159(也就是主頁面H#3)的使用者資料，並且它們的對照資訊已經更新到RAM 136中暫存的H2F子表。第四至第六筆紀錄指出當前塊的頁面P#3至P#5分別儲存了邏輯位址LBA#192000~192031(也就是主頁面H#6000)、LBA#192032~192063(也就是主頁面H#6001)和LBA#192064~192095(也就是主頁面H#6002)的使用者資料，並且它們的對照資訊不能更新到RAM 136中暫存的H2F子表。第四至第六筆紀錄可稱為用於更新閃存模組150中的相應H2F子表的中間資訊。換句話說，關聯於邏輯位址LBA#192000~192031、 LBA#192032~192063和LBA#192064~192095的H2F子表430#1尚未從閃存模組150讀出，需要進一步執行表格更新程序。 The following examples illustrate that in addition to storing logical address information, each record in the F2H table of the current block also stores an update flag, which is used to indicate whether the comparison information of this record has been updated to the temporary storage in RAM 136. H2F subtable, "1" means updated, "0" means not updated. Table 1 describes the sample contents of the F2H table for the current block:

The first to third records indicate that pages P#0 to P#2 of the current block store logical addresses LBA#64~95 (that is, the main page H#2) and LBA#96~127 (that is, the main page) respectively. H#3) and LBA#128~159 (that is, the main page H#3) user data, and their comparison information has been updated to the H2F subtable temporarily stored in RAM 136. The fourth to sixth records indicate that pages P#3 to P#5 of the current block store logical addresses LBA#192000~192031 (that is, the main page H#6000) and LBA#192032~192063 (that is, the main page) respectively. H#6001) and LBA#192064~192095 (that is, the main page H#6002) user data, and their comparison information cannot be updated to the H2F subtable temporarily stored in RAM 136. The fourth to sixth records can be referred to as intermediate information used to update the corresponding H2F sub-table in the flash memory module 150 . In other words, the H2F subtable 430#1 associated with the logical addresses LBA#192000~192031, LBA#192032~192063, and LBA#192064~192095 has not been read from the flash memory module 150, and the table update procedure needs to be further executed.

The embodiment of the present invention proposes a method for executing a host discard command, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method updates the H2F subtable and discard queue temporarily stored in RAM 136 after each execution of the host discard command, which is used to store the latest comparison information between logical and physical addresses and the update status of the H2F subtable.

Referring to Figure 7, the detailed steps are as follows:

Step S710: Execute the first (next) host discard command. The processing unit 134 can extract parameters of the host write command (including logical address, length, etc.).

Step S720: Determine whether the H2F subtables associated with these logical addresses are temporarily stored in the RAM 136. If yes, the flow continues with the processing of step S730; otherwise, the flow continues with the processing of step S740.

Step S730: Update the H2F subtable temporarily stored in the RAM 136 to delete the comparison information of the physical addresses corresponding to these logical addresses. Assuming that the host discard command instructs to discard the user data of LBA#64 to LBA#127, the processing unit 134 can associate the corresponding H2F subtable with LBA#64 to LBA#127 (that is, the main page H#2 to the main page H# The physical address field of 3) is filled with dummy values, which means that the user data of LBA#64 to 127 does not exist in the flash memory module 150.

Step S740: Push the logical addresses indicated by the host discard command into the discard queue, indicating that the discard information of these logical addresses has not been updated to the corresponding H2F subtable.

丟棄佇列的內容可稱為用於更新閃存模組150中的相應H2F子表的中間資訊。 The following are some examples. Suppose the host discard command instructs to discard the user data at the logical addresses LBA#192032~192095 (that is, the main pages H#6001 to H#6002), and the H2F associated with the logical addresses LBA#192032~192095 The subtable is not temporarily stored in RAM 136. Since each entity page can store user data of 32 LBAs, the logical addresses LBA#192032~192095 are divided into logical addresses LBA#192032~192063 and LBA#192064~192095, and the divided logical addresses are pushed into the discard queue. Table 2 describes sample contents of the drop queue:

The contents of the discard queue may be referred to as intermediate information used to update the corresponding H2F sub-table in the flash memory module 150 .

In general, the F2H table or discard queue of the current block stores information on whether the H2F subtable associated with a specific logical address needs to perform a table update procedure. For example, each record with an update flag of "0" in the F2H table of the current block stores information that the H2F subtable associated with a specific logical address needs to perform a table update procedure. Each node in the discard queue stores information that the H2F subtable associated with a specific logical address needs to perform the table update procedure.

The embodiment of the present invention provides a method for executing a table update program, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. Whenever the current block is full or when a preset condition is met, a table update program is executed to write the H2F subtable temporarily stored in the RAM 136 to the flash memory module 150 and to discard the queue according to the F2H table. The unupdated information of the H2F table of the indicated specific logical address is updated to the corresponding H2F sub-table in the flash memory module 150 . Referring to Figure 8, the detailed steps are as follows:

Step S810: Write the H2F subtable temporarily stored in the RAM 136 to the designated system block in the flash memory module 150. Assume that the H2F subtable 430#0 is temporarily stored in the RAM 136: the processing unit 134 drives the flash memory interface 139 to write the H2F subtable 430#0 temporarily stored in the RAM 136 into the designated system block in the flash memory module 150.

Step S820: Read the H2F subtable associated with the unupdated logical address from the flash memory module 150 according to the contents of the F2H table of the current block and the discard queue temporarily stored in the RAM 136 and store it in the RAM 136. Following the example of the F2H table for the current block described in Table 1 and the example of the discard queue described in Table 2, the unupdated logical addresses are LBA#192000 to LBA#192031, and their associated H2F subtable is 430# 1. Therefore, the processing unit 134 drives the flash memory interface 139 H2F subtable 430#1 is read from the designated system block and stored in RAM 136.

Step S830: Update the newly read H2F subtable (for example, H2F subtable 430 #1) in RAM 136 according to the contents of the F2H table of the current block and the discard queue temporarily stored in RAM 136.

Step S840: Write the updated H2F subtable in the RAM 136 to the designated system block in the flash memory module 150.

The above method can be applied to a system architecture in which the RAM 136 cannot allocate space to all H2F sub-tables, and the execution time of the table update program can be saved by pre-storing a part of the H2F sub-tables in the RAM 136 .

In order to make it easier for readers to understand, although the above embodiment uses a current block as an example to illustrate the operation details, those skilled in the art can apply it to a flash memory interface capable of writing multiple current blocks in parallel after appropriate modifications. The present invention It is not limited by this.

All or part of the steps in the method of the present invention can be implemented by computer instructions, such as a firmware translation layer (FTL) in a storage device, a driver for a specific hardware, etc. In addition, it can also be implemented in other types of programs. Those with ordinary skill in the art can write the methods of the embodiments of the present invention as computer instructions, which will not be described again for the sake of simplicity. Computer instructions implemented according to the methods of the embodiments of the present invention can be stored in appropriate computer-readable media, such as DVD, CD-ROM, USB disk, hard disk, or can be placed in a computer that can be accessed through a network (for example, the Internet, or A web server accessible by other appropriate vehicles).

Although Figures 1 and 2 contain the components described above, it does not rule out the use of more other additional components to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts of Figures 6 to 8 are executed in a specified order, those skilled in the art can modify the order of these steps without violating the spirit of the invention and achieving the same effect. Therefore, The present invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

S810~S840: Method steps

Claims (13)

A method for updating a host and flash memory address comparison table, executed by a processing unit, including: configuring space in a random access memory for a first host and flash memory address comparison table, and updating the address comparison table in a flash memory module. The intermediate information of the second host and flash memory address comparison table; when executing the host write command to write data to the flash memory module or executing the host discard command to discard the data in the flash memory module, update all The first host and flash memory address comparison sub-table and the intermediate information temporarily stored in the random access memory; and in the table update procedure, the third host temporarily stored in the random access memory A host and flash memory address comparison sub-table is written into the system block in the flash memory module, and the second host and flash memory address comparison sub-table is updated based on the intermediate information temporarily stored in the random access memory. And write the updated second host and flash memory address comparison table into the system block in the flash memory module. The method for updating the host and flash memory address comparison table as described in claim 1, wherein the intermediate information is stored in the flash memory and host address comparison table of the current block, and the method includes: executing the host write When a command is entered, update the flash memory and host address comparison table of the current block temporarily stored in the random access memory to store multiple write pages in the current block corresponding to multiple logical Comparison information of addresses, wherein the plurality of logical addresses include a first logical address associated with the first host and flash memory address comparison subtable and a first logical address associated with the second host and flash memory address comparison subtable. the second logical address of the table; for the first logical address, update the first host and flash memory address comparison sub-table to store the comparison information of which physical address the first logical address corresponds to, and Set the corresponding update flag in the flash memory and host address comparison table of the current block to a first value; and for the second logical address, compare the flash memory and host address of the current block The corresponding update flag in the lookup table is set to the second value. The method for updating the host and flash memory address comparison table as described in claim 2, wherein the update flag in the flash memory and host address comparison table of the current block is used to indicate whether the corresponding comparison information has been updated to all The first host and flash memory address comparison subtable. The method for updating the host and flash memory address comparison table as described in claim 2, which includes: in the table update procedure, setting the second The comparison information associated with the update flag of the value updates the second host and flash memory address comparison sub-table. The method for updating the host and flash memory address comparison table as described in claim 1, wherein the intermediate information is stored in a discard queue, and the method includes: when executing the host discard command, determining that the host Whether the logical address pointed out by the discard command is associated with the first host and flash memory address comparison sub-table; when the logical address pointed out by the host discard command is associated with the first host and flash memory address comparison sub-table, Update the first host and flash memory address comparison table to store information that the user data of the logical address has been discarded; and when the logical address indicated by the host discard command is associated with the second host and flash memory When the address comparison subtable is used, the logical address is pushed into the discard queue, and the information representing that the user data of the logical address has been discarded needs to be updated to the second host and flash memory address comparison subtable. . The method of updating the host and flash memory address comparison table as described in claim 5, including: in the table update procedure, updating the second host and flash memory bits according to the logical address in the discard queue. Address comparison subtable. A computer program product includes program code, wherein when the processing unit executes the program code, the method for updating the host and flash memory address comparison table as described in any one of claims 1 to 6 is implemented. A device for updating a host and flash memory address comparison table, including: a random access memory; a flash memory interface coupled to a flash memory module; and a processing unit coupled to the random access memory and the flash memory interface for Configuring space in the random access memory for the first host and flash memory address comparison sub-table, and providing intermediate information for updating the second host and flash memory address comparison sub-table in the flash memory module; in When executing a host write command to write data to the flash memory module or executing a host discard command to discard data in the flash memory module, update the first host temporarily stored in the random access memory. and the flash memory address comparison subtable and the intermediate information; and in the table update procedure, write the first host and the flash memory address comparison subtable temporarily stored in the random access memory into the flash memory module. The system block in the group updates the second host and flash memory address comparison sub-table based on the intermediate information temporarily stored in the random access memory and compares the updated second host and flash memory address comparison sub-table Write to the system block in the flash memory module. The device for updating the host and flash memory address comparison table as described in request item 8, wherein the intermediate information is stored in the flash memory and host address comparison table of the current block, and wherein the processing unit executes the host When a command is written, the random memory is updated Obtain the flash memory and host address comparison table of the current block temporarily stored in the memory to store comparison information corresponding to multiple logical addresses of multiple write pages in the current block, wherein: The plurality of logical addresses include a first logical address associated with the first host and flash memory address comparison sub-table and a second logical address associated with the second host and flash memory address comparison sub-table; for The first logical address, updating the first host and flash memory address comparison sub-table to store the comparison information of which physical address the first logical address corresponds to, and converting the current block of the flash memory The corresponding update flag in the host address comparison table is set to a first value; and for the second logical address, the corresponding update flag in the flash memory and host address comparison table of the current block is set to a first value. is the second value. The device for updating the host and flash memory address comparison table as described in claim 9, wherein the update flag in the flash memory and host address comparison table of the current block is used to indicate whether the corresponding comparison information has been updated to the The first host and flash memory address comparison subtable. The device for updating the host and flash memory address comparison table as described in claim 9, wherein the processing unit, in the table update procedure, sets the value of each address comparison table between the flash memory and the host to the The comparison information associated with the update flag of the second value updates the second host and flash memory address comparison subtable. The device for updating the host and flash memory address comparison table as described in request item 8, wherein the intermediate information is stored in a discard queue, and wherein the processing unit determines that when executing the host discard command, Whether the logical address pointed out by the host discard command is associated with the first host and flash memory address comparison sub-table; when the logical address pointed out by the host discard command is associated with the first host and flash memory address comparison sub-table , update the first host and flash memory address comparison table to store the information that the user data of the logical address has been discarded; to And when the logical address pointed out by the host discard command is associated with the second host and flash memory address comparison sub-table, push the logical address into the discard queue, representing the use of the logical address The discarded information of the host data needs to be updated to the second host and flash memory address comparison table. The device for updating the host and flash memory address comparison table as described in claim 12, wherein the processing unit updates the second logical address according to the logical address in the discard queue in the table update procedure. Host and flash memory address comparison table.

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