TWI795680B - Method and apparatus for data reads in host performance acceleration mode - Google Patents

Abstract

The invention relates to a method, and an apparatus for data reads in host performance acceleration (HPA) mode. The method is performed by a host side to include: issuing a switch command to a flash controller for requesting the flash controller to activate an HPA function and an L2P-mapping-table acquisition function; issuing a write-multiple-block command to the flash controller for writing a data block to the flash controller, which includes a region number and a sub-region number; issuing a read-multiple-block command to the flash controller for obtaining L2P mapping records corresponding to the region number and the sub-region number from the flash controller; and storing the L2P mapping records in an HPA buffer of a system memory.

Description

Data reading method and device in host performance acceleration mode

The invention relates to a storage device, in particular to a method and device for reading data in a host performance acceleration mode.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address for accessing NOR flash memory on the address pin, and obtain the data stored on the address from the data pin of NOR flash memory in time. material. In contrast, NAND flash memory is not random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the CPU needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest data block for writing operations in flash memory) or a block (the smallest data block for erasing operations in flash memory).

In order to improve the data writing and reading performance of the flash memory module, the device side will execute data writing and reading in parallel through multiple channels. In order to achieve the purpose of parallel processing, a piece of continuous data will be distributed and stored in flash memory units connected to multiple channels, and recorded using the Logical-block-address to Physical-block-address (L2P Mapping Table) The corresponding relationship between the logical address (managed by the host) and the physical address (managed by the flash memory controller) of the user data. However, in the embedded Multi-Media Card (embedded Multi-Media Controller, e‧MMC) storage device, with the rapid increase of device capacity, the length of the logical entity comparison table also doubles, resulting in the traditional management method executed on the device side. unaffordable. Even using hierarchical subsections to Managing the logical entity comparison table can improve the efficiency of logical entity conversion, but the time spent on logical entity conversion is still significantly higher than the time for transferring data from the flash array of the flash memory module to the data register of the flash memory controller (tR ). Therefore, the present invention proposes a data reading method and device in a performance acceleration mode of a host for improving the data reading performance of a storage device of an embedded multimedia card.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem to be solved.

This specification relates to a method for reading data in the host performance acceleration mode, which is executed by the host side, including: sending a switching command to the flash memory controller, which is used to request the flash memory controller to start the host performance acceleration function and the acquisition function of the logical entity comparison table; Write multi-block commands to the flash memory controller, used to write data blocks to the flash memory controller, the data blocks contain area numbers and sub-area numbers; issue read multi-block commands to the flash memory controller, used to obtain corresponding data from the flash memory controller A plurality of logical entity comparison records in the area number and sub-area number; and storing the logical entity comparison records in the host performance acceleration buffer in the system memory.

This specification also relates to a method for reading data in the host performance acceleration mode, which is executed by the flash memory controller, including: receiving a switching command from the host end, which is used to request the flash memory controller to start the host performance acceleration function and the acquisition function of the logical entity comparison table; Enter the default state in response to the switching command; receive a write multi-block command from the host during entering the default state; obtain the area number and sub-area number from the data block received by the host in response to the write multi-block command, and from The flash memory device reads a plurality of logical entity comparison records corresponding to the area number and the sub-area number; receives a read multi-block command from the host during entering the default state; and transmits the logical entity comparison record to the host in response to the read multi-block command end.

This specification also relates to a host performance acceleration mode device, including: a host interface; a flash memory interface; and a processing unit. The processing unit receives a switching command from the host side through the host interface, and is used to request the device to start the host performance acceleration function and the acquisition function of the logical entity comparison table; enter the default state in response to the switching command; pass through during entering the default state The host interface receives the write multi-block command from the host side; in response to the write multi-block command, obtains the area number and sub-area number from the data block received by the host side through the host interface, and reads the corresponding area from the flash memory device through the flash memory interface Multiple logical entity comparison records of numbers and sub-area numbers; during the period of entering the default state, a read multi-block command is received from the host side through the host interface; and in response to the read multi-block command, the logical entity comparison record is sent to the host side through the host interface .

The host and the flash memory controller communicate with each other using the embedded multimedia card communication protocol, and each logical entity compares and records the information stored in the logical address and actually stored in the physical address.

One of the advantages of the above-mentioned embodiment is that by setting the host performance acceleration buffer as described above, the host can send a read command with a logical entity comparison record to the flash memory controller, which is used to reduce the time and computing resources spent by the flash memory controller Perform logical entity comparison conversion.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

10: Electronic device

110: Host side

130: Flash memory controller

131: host interface

132: busbar

134: processing unit

135: ROM

136: random access memory

137: Temporary register

139: Flash interface

150: Flash memory device

151: interface

153#0~153#15: NAND flash memory unit

CH#0~CH#3: channel

CE#0~CE#3: enable signal

310: Advanced Comparison Table

330#0~330#15: L2P comparison table

400: L2P Control Record

410: Logical block address information

430:Information of physical block address

430-0: logical unit number and physical block number

430-1: Entity page number

440: Solid block

450: entity page

450#2: Entity section

500: HPA cache

611~655,711~755,835~839,915,931,955: Operation

S1010~S1060, S1110~S1147: method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a flash memory device according to an embodiment of the invention.

Fig. 3 is a schematic diagram of the association between the high-level comparison table and the logical entity comparison sub-table according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of the association between the logical entity comparison sub-table and the entity page according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of establishment and operation of a Host Performance Acceleration (HPA) cache according to an embodiment of the present invention.

FIG. 6 is an operation sequence diagram of HPA buffer initialization according to an embodiment of the present invention.

7 and 8 are operation sequence diagrams of HPA reading according to an embodiment of the present invention.

FIG. 9 is an operation sequence diagram of HPA buffer update according to an embodiment of the present invention.

FIG. 10 is a flowchart of a method for executing a switch command according to an embodiment of the present invention.

FIG. 11 is a flowchart of a method for executing a write multi-block command according to an embodiment of the present invention.

The following description is a preferred implementation mode of the invention, and its purpose is to describe the basic spirit of the invention, but not to limit the invention. For the actual content of the invention, reference must be made to the scope of the claims that follow.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, components and/or components, but do not exclude the possibility of adding More technical characteristics, numerical values, method steps, operation processes, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a priority order, a pre-relationship, or an element An element preceding another element, or a chronological order in performing method steps, is only used to distinguish elements with the same name.

It must be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements may be interpreted in a similar fashion, eg, "between" versus "directly between," or "adjacent" versus "directly adjacent," and so forth.

Refer to Figure 1. The electronic device 10 includes a host device (also called a host side) 110 , a flash memory controller 130 and a flash memory device 150 , and the flash memory controller 130 and the flash memory device 150 are collectively called a device side. The electronic device 10 can be implemented in electronic products such as personal computers, notebook computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The host device 110 and the host interface (Host Interface) 131 of the flash controller 130 can communicate with each other through the embedded Multi-Media Controller (e.MMC/eMMC) communication protocol. The flash memory interface 139 of the flash memory controller 130 and the flash memory device 150 can communicate with each other with a double data rate (Double Data Rate, DDR) communication protocol, for example, an open NAND flash interface (Open NAND Flash Interface, ONFI), Double Data Rate Switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in various ways, such as using general-purpose hardware (for example, a microcontroller unit, a central processing unit, a multi-processor with parallel processing capabilities, a graphics processing unit, or other processing units with computing capabilities. device) and, when executing software and/or firmware instructions, provide the functionality described hereinafter. The processing unit 134 receives eMMC commands through the host interface 131 and executes these commands. The flash memory controller 130 includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM) ) or a combination of the above two, used to configure the space as a data buffer. The random access memory 136 can also store data required during execution, such as variables, data tables, and the like. The flash memory controller 130 includes a read only memory (Read Only Memory, ROM) 135 for storing program codes that need to be executed when booting. The flash memory interface 139 includes a NAND flash memory controller (NAND Flash Controller, NFC), which provides functions needed when accessing the flash memory device 150, such as a command sequencer (Command Sequencer), a low density parity check (Low Density Parity Check, LDPC), etc. .

The flash memory controller 130 includes a register 137 for storing various parameter values. In the eMMC specification (such as the eMMC electrical standard 5.1 published in July 2014), the register 137 includes a 32-bit operation condition register (Operation Condition Register, OCR), a 128-bit device identification register (Device IDentification, CID Register), 128-bit device-specific data register (Device-Specific Data, CSD Register), 512-byte extended device-specific data register (Extended CSD Register, may be referred to as Ext_CSD register), etc. The Ext_CSD register defines the device properties (Device Properties) and the selected mode (Selected Modes), and the most significant 320 bytes are the properties segment (Properties Segment), which is used to define the capabilities of the device and cannot be modified by the host 110 , additionally the less significant 192-bit The group is the Modes Segment, which defines the settings in which the device is currently operating. The host 110 can change these modes through a switch command (SWITCH command, CMD6). The eMMC specification reserves several areas in the Ext_CSD register that can be freely used by device manufacturers to implement the Host Performance Acceleration (HPA Mode) function.

A bus architecture (Bus Architecture) 132 can be configured in the flash memory controller 130, which is used to couple components to each other to transmit data, addresses, control signals, etc. These components include a host interface 131, a processing unit 134, a ROM 135, RAM 136, register 137, flash memory interface 139, etc. In some embodiments, the host interface 131 , the processing unit 134 , the ROM 135 , the RAM 136 , the register 137 and the flash memory interface 139 may be coupled to each other through a single bus. In other embodiments, the flash memory controller 130 may be configured with a high-speed bus for coupling the processing unit 134, ROM 135, RAM 136, and register 137 to each other, and a low-speed bus for allowing the processing unit 134. The host interface 131 and the flash memory interface 139 are coupled to each other. A bus comprises parallel physical wires connecting two or more components in flash memory controller 130 .

The flash memory device 150 provides a large amount of storage space, usually hundreds of gigabytes (Gigabytes, GB), or even several terabytes (Terabytes, TB), for storing a large amount of user data, such as High-resolution pictures, videos, and more. The flash memory device 150 includes a control circuit and a memory array, and memory cells in the memory array can be configured as single-level cells (Single Level Cells, SLCs) and multi-level cells (Multiple Level Cells, MLCs) after erasing. Layer cells (Triple Level Cells, TLCs), quadruple level cells (Quad-Level Cells, QLCs), or any combination of the above. The processing unit 134 writes the user data to the specified address (destination address) in the flash memory device 150 through the flash memory interface 139, and reads the user data and L2P comparison from the specified address (source address) in the flash memory device 150 specified part of the table. The flash memory interface 139 uses several electronic signals to coordinate data and command transmission between the flash memory controller 130 and the flash memory device 150, including a data line (Data Line), a clock signal (Clock Signal) and control signal (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to FIG. 2, the interface 151 in the flash memory device 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, and each channel is connected to four NAND flash memory units, for example, the channel CH #0 is connected to NAND flash memory units 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent die. The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11 , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in parallel, or write user data to the enabled NAND flash memory unit.

Because the data of a section of continuity (that is, a section of continuous Logical Block Addresses, Logical Block Addresses, LBAs) is dispersedly stored in the NAND flash memory cells connected to multiple channels, the flash memory controller 130 uses a logical entity look-up table (Logical Block Addresses, LBAs) -block-address to Physical-block-address, L2P Mapping Table) records the correspondence between the logical address (managed by the host device 110 ) and the physical address (managed by the flash memory controller 130 ) of user data. The L2P comparison table includes a plurality of records, and stores the information of which physical address the user data of each logical address is actually stored in the order of logical addresses. A piece of continuous LBA data can be divided into several regions (Regions), which are identified by region numbers, and each region can be further divided into several sub-regions (Sub-regions), which are identified by sub-region numbers. For example, 128GB of data addressed by LBA can be divided into 16 8GB areas, and each 8GB area can be further divided into 256 32MB sub-areas. In the eMMC specification, each LBA is associated with (or points to) 512 bytes (Bytes) of data. However, since RAM 136 cannot provide enough space to store the entire L2P lookup table In order for the processing unit 134 to quickly search for future data reading operations, the entire L2P comparison table can be divided into multiple sub-tables according to the division of regions and sub-regions, and stored in different physical addresses of the non-volatile flash memory device 150, Therefore, only the corresponding sub-table is read from the flash memory device 150 to the RAM 136 during the data reading operation in the future. Referring to FIG. 3, the entire L2P comparison table can be divided into sub-tables 330#0~330#15. The processing unit 134 further maintains a high-level mapping table (High-level Mapping Table) 310, which includes a plurality of records, and stores physical address information of sub-tables associated with each LBA segment in the order of logical addresses. For example, the associated subtable 330#0 of the 0th to 4095th LBA is stored in a specific physical block of a specific logical unit number (Logical Unit Number, LUN) (the letter "Z" can represent the number of the LUN and the physical block) The 0th physical page, the associated subtable 330#1 of the 4096th to 8191st LBAs are stored in the 1st physical page in the specific physical block of the specific LUN, and so on. Although only 16 sub-tables are included in FIG. 3 , those skilled in the art can set more sub-tables according to the capacity of the flash memory device 150 , and the present invention is not limited thereto.

In order to cooperate with the physical configuration of the flash memory device 150, the flash memory controller 130 can associate (or point to) a physical block address (Physical Block Address, PBA) with 4KB, 8KB or 16KB of data, which is longer than one LBA of the eMMC specification The length of the associated data (512B). Since the data lengths associated with the LBA and the PBA are inconsistent, each record in each sub-table includes logical address and physical address information, which is used to accurately point out the address in the flash memory device 150 . Referring to FIG. 4, the sub-table 330#0 sequentially stores addressing information from LBA#0 to LBA#4095. Addressing information can be represented by eight bytes: four bytes represent LBA; the other four bytes represent PBA. For example, the record 400 associated with LBA #2 in the sub-table 330 #0 stores the information of the LBA 410 and the PBA 430 . The two bytes 430-0 in the PBA 430 record the logical unit number and the physical block number (Physical Block Number); the other two bytes 430-1 record the physical page number (Physical Page Number). Therefore, the physical address information 400 corresponding to LBA #2 can point to a specific sector (Sector) 450 #2 in the physical page 450 of the physical block 440 .

In order to solve the problem that the flash memory controller 130 spends too much time on logical entity conversion, the embodiment of the present invention adds a new function of HPA on the basis of the host-device communications architecture (Host-Device Communications Architecture) of the current eMMC specification. HPA converts the workload of logical entity comparison transformation that was originally implemented by the flash memory controller 130, which takes a lot of time, to the host side 110, which can improve the random read performance of short-length data. Short-length data can refer to lengths from 512B to 32KB. data of. Referring to FIG. 5 , the host 110 configures space in its system memory (System Memory) as an HPA cache 500 for temporarily storing information of the L2P comparison table maintained and managed by the device. The HPA cache 500 stores a plurality of L2P mapping records (L2P Mapping Records) received from the device, and each L2P mapping record corresponds to the addressing information of one LBA. Next, the host 110 can issue a command carrying the L2P comparison record to the device to obtain user information of the specified LBA. The flash memory controller 130 can directly drive the flash memory interface 139 to read the user data of the specified LBA from the flash memory device 150 according to the information in the L2P comparison record, without spending time and computing resources to read the corresponding LBA from the flash memory device 150 as before. The user data of the specified LBA can be read from the flash memory device 150 only after logical physical address translation is performed on the sub-table. The establishment and use of HPA cache 500 can be divided into three stages:

Stage I (HPA initialization): The host 110 reads the value of the temporary register 137 in the flash controller 130, and checks whether the eMMC storage device (or device side, including at least the flash controller 130 and the flash device 150) supports the HPA function. If yes, the host terminal 110 configures space in the system memory as the HPA L2P comparison table area.

Phase II (HPA comparison table management): If the eMMC storage device supports the HPA function, the host 110 sends a series of commands to request the flash memory controller 130 to read the L2P comparison table. In response to this series of commands, the flash memory controller 130 transmits all or part of the L2P comparison table to the host 110, allowing the host 110 to store the obtained comparison table in the HPA L2P comparison table area (this can be called a mirrored L2P comparison table). Table, Mirrored L2P Mapping Table). When the actual L2P comparison table corresponding to the mirror image L2P comparison table is written due to data, After programs such as data trimming (Data Trimming), garbage collection (Garbage Collection, GC), and wear leveling (Wear Leveling) are changed, the flash memory controller 130 notifies the host end 110 of all or a corresponding part of the system memory of the host end 110 The L2P comparison table needs to be updated.

Phase III (HPA read): The host 110 sends a series of commands with L2P comparison records to the eMMC storage device to request to obtain specific LBA data (especially small block length discontinuous data, such as 512B to 32KB discontinuous data), where the L2P comparison record is searched from the mirrored L2P comparison table. Then, the flash memory controller 130 reads the data of the specified LBA from the PBA of the flash memory device 150 according to the content of the L2P comparison record, and replies the read data to the host end 110, so that the eMMC storage device can save the read time for logical entity comparison conversion. Time to fetch and search the L2P comparison table.

In the eMMC specification, Ext_CSD[160] (also called PARTITIONING_SUPPORT[160]) defines Supported Partition Features, and Bits[7:3] are reserved for free use by manufacturers of eMMC storage devices. The third bit of the 160th byte of the Ext_CSD register (Ext_CSD[160], Bit[3]) can be used to define whether the eMMC storage device supports the HPA function, if it supports it, set it to "1", if it is disabled is set to "0". During the initialization process of the eMMC storage device, the processing unit 134 can set Ext_CSD[160], Bit[3] in the register 137 to “1”. Although the embodiment of the present invention describes the technical solution of using Ext_CSD[160], Bit[3] to define whether the eMMC storage device supports the HPA function, those skilled in the art can change the design to use other reserved bits in the Ext_CSD register, for example Ext_CSD[511:506], Ext_CSD[485:309], Ext_CSD[306], Ext_CSD[233], Ext_CSD[227], Ext_CSD[204], Ext_CSD[195], Ext_CSD[193], Ext_CSD[190], Ext_CSD [188], Ext_CSD[186], Ext_CSD[184], Ext_CSD[182], Ext_CSD[180], Ext_CSD[176], Ext_CSD[172], Ext_CSD[170], Ext_CSD[135], Ext_CSD[129:128] , Ext_CSD[127:64], Ext_CSD[28:27], Ext_CSD[14:0], etc., the present invention does not So limited.

In addition, the flash memory controller 130 can use the pair of Ext_CSD registers to record the information of the specified area and sub-area that needs to be updated in the L2P lookup table cached by the host 110 . For example, the 64th byte (Ext_CSD[64]) and the 66th byte (Ext_CSD[66]) of the Ext_CSD scratchpad are a pair, which are used to indicate the 0th region (Region#0) and The 160th subregion (SubRegion#160). The 65th byte (Ext_CSD[65]) and the 67th byte (Ext_CSD[67]) of the Ext_CSD scratchpad are another pair, which are used to indicate the 0th region (Region#0) and the 0th region respectively 18 subregions (SubRegion#18).

In the eMMC specification, the switching command (CMD6) is issued by the host terminal 110 to switch the operating mode of the selected device or modify the value of the Ext_CSD register, and the 26th to 31st bits of the parameter (Bits[31:26] ) are reserved bits. The host terminal 110 can set the 26th bit (CMD6, Bit[26]) of CMD6 to indicate whether to enable the HPA function, if enabled, set it to "1", and if disabled, set it to "0". Although the embodiment of the present invention describes the technical solution of using CMD6, Bit[26] to define whether to start the HPA function, those skilled in the art can change the design to use other reserved bits in the parameters of CMD6, and the present invention is not limited thereby. The host terminal 110 can set the 27th bit of CMD6 (CMD6, Bit[27]) to indicate whether to activate the L2P comparison table acquisition function, if enabled, set to "1", if disabled, set to "0". Although the embodiment of the present invention describes the technical solution of using CMD6, Bit[27] to define whether to start the acquisition function of the L2P comparison table, those skilled in the art can change the design to use other reserved bits in the parameters of CMD6, and the present invention does not So limited.

In the eMMC specification, the set block number command (CMD23) is issued by the host 110 to indicate the block number of the subsequent packaged write command, or the number of blocks of the header (Header) of the subsequent packaged read command. When CMD23 is associated with the following package write command, the 30th bit (Bit[30]) in the parameter is set to "0b1", and the 0th to 15th bits (Bits[15]) in the parameter of CMD23 :0]) is used to indicate the number of blocks. When CMD23 is associated with the subsequent package write command or package read command, the 30th bit (Bit[30]) in the parameter is set to "0b1". The 0th to 15th bits in the parameters of CMD23 (Bits[15:0]) is used to indicate the number of blocks.

In the eMMC specification, the write multi-block command (CMD25) is issued by the host 110 to continuously write data blocks to the eMMC storage device until a stop transmission command (STOP_TRANSMISSION Command, CMD12) is issued, or the requested number of data blocks has been written. The host 110 can transmit the information of the specified area and sub-area in the L2P comparison table through CMD23 and CMD25, and request the flash memory controller 130 to prepare the L2P comparison record of the designated area and sub-area. In addition, the host 110 can transmit the L2P comparison record through CMD23 and CMD25, requesting the flash memory controller 130 to prepare data for future reading. The 0th to 31st bits (Bits[31:0]) in the parameters of CMD25 indicate the data address.

In the eMMC specification, the read multi-block command (CMD18) is issued by the host terminal 110 to continuously read data blocks from the eMMC storage device until the requested number of data blocks have been read, or the stop command (Stop Command )interrupt. That is to say, the CMD 18 requests the eMMC storage device to send the previously indicated number of data blocks to the host 110 . The 0th to 31st bits (Bits[31:0]) in the parameter of CMD18 represent the data address. The host 110 can request the flash memory controller 130 to transmit the L2P comparison record of the specified area and sub-area (defined in the previous CMD25) through CMD23 and CMD18. Referring to the example shown in FIG. 4 , the length of each L2P collation record is 8B, so that each data block can carry a maximum of 32 L2P collation records. In addition, the host 110 can request the flash memory controller 130 to transmit data corresponding to the L2P comparison record (defined in the previous CMD25) through CMD23 and CMD18.

In the eMMC specification, a normal response command (Normal Response Command, R1) is issued by the flash memory controller 130 to inform the host 110 of a specific message. The length of R1 is 48 bits, of which the 40th to 45th bits (Bits[45:40]) record the index of the command to be replied, and the 8th to 39th bits (Bits[39:8]) record the device Status (Device Status). When the 31st bit (Bit[31]) of R1 is set to "0b1", it means the address exceeds the range (ADDRESS_OUT_OF_RANGE). When the 30th bit of R1 When (Bit[30]) is set to "0b1", it means the address is not matched (ADDRESS_MISALIGN). When the HPA function is started but the acquisition function of the L2P comparison table is not started, if some PBAs in the L2P comparison record carried in the CMD25 are invalid, the flash memory controller 130 can use the 31st bit of the R1 of the CMD18 after the reply (Bit[31]) and the 30th bit (Bit[30]) are both set to "0b1", which is used to indicate that the L2P comparison record cached in the host 110 needs to be updated.

For the establishment of the HPA L2P comparison table area (also called the HPA buffer) in Phase I and Phase II, after the eMMC storage device is initialized, the host terminal 110 reads the L2P comparison table from the device side for the first time and stores it in the HPA buffer district. Table 1 describes the example command sequence details for initializing the HPA buffer:

Referring to the operation sequence diagram of HPA buffer initialization shown in Figure 6, the details are as follows:

Operation 611: the host 110 sends a command to the flash memory controller 130 for requesting the flash memory controller 130 to obtain the value of the Ext_CSD register.

Operation 613 : In response to the register read command received through the host interface 131 , the processing unit 134 obtains the value of the Ext_CSD register in the register 137 , and replies to the host end 110 through the host interface 131 .

Operation 615: the host 110 can check the value of the Ext_CSD register (for example, Ext_CSD[160], Bit[3]) to determine whether the eMMC storage device supports the HPA function. If yes, proceed to operation 617. If not, the HPA function is not started.

Operation 617: the host 110 sends a switching command (CMD6) to the flash memory controller 130 to start the HPA function and the acquisition function of the L2P comparison table. For example, referring to the second row of Table 1, the host 110 can set the parameter of CMD6 to "0x0C000000", which includes Bit[26]="0b1" and Bit[27]="0b1", which are used to indicate flash memory control The controller 130 enables these two functions.

Operation 619: After the flash memory controller 130 receives the switching command shown above, it enters the HPA mapping table read state (HPA_Mapping_READ state), which is used to prepare to send a part of the L2P mapping table to the host 110 .

Operation 631: The host end 110 allocates space in the system memory for the HPA buffer, and decides to store the eMMC memory according to the requirements of the operating system, driver program, and application program. Set the L2P comparison records of the acquired area and sub-area.

Operation 633: the host 110 sends a set block number command (CMD23) to the flash memory controller 130 for notifying the flash memory controller 130 how many data blocks will be transferred. For example, referring to the third horizontal row of Table 1, the host terminal 110 can set the parameter of CMD23 to "0x40000001", which includes Bit[30]="0b1" and Bits[15:0]="0x0001", indicating that the Write a block of data to the flash memory controller 130. Next, the host 110 sends a write multi-block command (CMD25) to the flash memory controller 130 for continuously writing data blocks to the flash memory controller 130 until the requested number of data blocks have been written. For example, referring to the fourth row of Table 1, the host 110 can set the parameter of CMD25 as “0x01E2A3E0”, representing a specific data address. Each data block can be divided into 32 packets (Packets), and the length of each packet is 16B. The 2 bytes in each packet can indicate the number of a specific area, while the remaining 14 bytes can indicate the number of several specific sub-areas. For example, when a packet contains {Region#0,SubRegion#0,SubRegion#1,SubRegion#2,SubRegion#3} information, it means that the specified part of the L2P comparison table is associated with the 0th to 0th region in the 0th region The 3rd sub-district. Next, the host 110 sends a set block number command (CMD23) to the flash memory controller 130 to inform the flash memory controller 130 how many data blocks it will receive. For example, referring to the fifth row in Table 1, the host 110 can set the parameter of CMD23 to "0x40000020", which includes Bit[30]="0b1" and Bits[15:0]="0x0020", indicating that the Read 32 data blocks from the flash memory controller 130, that is, at most 1024 L2P comparison records. Next, the host 110 sends a read multiple block command (CMD18) to the flash memory controller 130 for continuously reading data blocks from the flash memory controller 130 until the requested number of data blocks have been read. For example, referring to the sixth row of Table 1, the host 110 can set the parameter of CMD18 as “0x01E2A3E0”, representing a specific data address.

Operation 635: Since the read state of the HPA comparison table has been entered, when the flash memory controller 130 receives the data block corresponding to the CMD25 from the host terminal 110, it knows that each packet carries the information of the specified part of the L2P comparison table, and The requested L2P collation record can be read from the flash memory device 150 accordingly. In addition, when the flash controller 130 receives from the host 110 When CMD18, it is known that the specified part of the L2P comparison record can be sent to the host end 110. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transmitted by the flash memory controller 130 is the L2P comparison record of the specified part read from the flash memory device 150 according to the content in the data block written by the previous CMD25.

Operation 651: The flash memory controller 130 organizes the requested L2P collation record into multiple packets in a specified number of data blocks.

Operation 653: The flash memory controller 130 continues to transmit the organized data blocks to the host 110 until the specified number of data blocks are completely transmitted. Next, when receiving the packet reading completion message from the host 110, it leaves the read state of the HPA comparison table and enters the transfer state (Transfer State) of the eMMC specification.

Operation 655: The host 110 receives the L2P comparison record carried in each packet, and stores it in the HPA buffer. After storing the L2P comparison record carried in the last packet, the host 110 sends a send status command (SEND_STATUS command, CMD13) to the flash memory controller 130, which includes a message that the packet reading is completed.

For phase III data reading, Table 2 describes the command sequence details of the example for reading data using the HPA function:

Referring to the operation sequence diagram of HPA reading shown in Figure 7, the details are as follows:

Operation 711: The host 110 finds that random reading of short-length data is about to be performed.

Operation 713: the host 110 sends a switching command (CMD6) to the flash memory controller 130 to activate the HPA function. For example, referring to the second row of Table 2, the host 110 can set the parameter of CMD6 to "0x04000000", which includes Bit[26]="0b1" and Bit[27]="0b0", which are used to indicate flash memory control The controller 130 only activates the HPA function.

Operation 715: After the flash memory controller 130 receives the switching command shown above, it enters the HPA read state (HPA_READ state).

Operation 731: The host 110 searches the mirrored L2P lookup table in the HPA buffer to obtain L2P lookup records corresponding to multiple LBAs.

Operation 733: the host 110 sends a set block number command (CMD23) to the flash memory controller 130 to inform the flash memory controller 130 how many data blocks will be transferred. For example, referring to the third horizontal row of Table 2, the host terminal 110 can set the parameter of CMD23 to "0x40000001", which includes Bit[30]="0b1" and Bits[15:0]="0x0001", indicating that the write a Data blocks to flash memory controller 130. Next, the host 110 sends a write multi-block command (CMD25) to the flash memory controller 130 for continuously writing data blocks to the flash memory controller 130 until the requested number of data blocks have been written. For example, referring to the fourth row of Table 2, the host 110 can set the parameter of CMD25 as “0x01521182”, representing a specific data address. Each data block can be divided into 32 packets (Packets), and the length of each packet is 16B. Each packet is associated with a pair of LBA and PBA information, 8 bytes of which can point to a specific LBA, and the remaining 8 bytes can point to a specific PBA. Next, the host 110 sends a set block number command (CMD23) to the flash memory controller 130 to inform the flash memory controller 130 how many data blocks it will receive. For example, referring to the fifth row in Table 2, the host 110 can set the parameter of CMD23 to "0x40000020", which includes Bit[30]="0b1" and Bits[15:0]="0x0020", indicating that the Read 32 data blocks from the flash memory controller 130 , that is, the data of a maximum of 1024 LBAs. Next, the host 110 sends a read multiple block command (CMD18) to the flash memory controller 130 for continuously reading data blocks from the flash memory controller 130 until the requested number of data blocks have been read. For example, referring to the sixth row of Table 2, the host 110 can set the parameter of CMD18 as “0x01521182”, representing a specific data address.

Operation 735: Since the HPA read state has been entered, when the flash memory controller 130 receives the data block corresponding to CMD25 from the host terminal 110, it knows that each packet carries the paired LBA and PBA for a data read. information, and the requested data can be read from the flash memory device 150 accordingly. In addition, when the flash memory controller 130 receives the CMD 18 from the host 110 , it knows that it can start sending the designated data to the host 110 . Since the parameters of CMD18 are set to be the same as those of CMD25, the data transmitted by the flash memory controller 130 is the data of the specified LBA read from the flash memory device 150 according to the contents of the data block written by the previous CMD25.

Operation 751: The flash memory controller 130 organizes the requested data into packets in a specified number of data blocks.

Operation 753: the flash memory controller 130 continuously transmits the organized data blocks to the host 110, Until the specified number of data blocks are transmitted. Then, when receiving the packet reading completion message from the host 110 , it leaves the HPA reading state and enters the eMMC standard transmission state.

Operation 755: The host 110 receives the data carried in each packet, and stores the data in the data buffer of the system memory. After storing the data carried in the last packet, the host 110 sends a transfer status command (CMD13) to the flash memory controller 130, which includes a message that the packet reading is completed.

Regarding the updating of the HPA buffer in Phase II, during the operation of the device, the host 110 can request the flash memory controller 130 to perform operations such as data writing, data trimming (Data Trims), and block erasing (Block Erases). The flash memory controller 130 can actively execute programs such as garbage collection (Garbage Collection, GC) and wear leveling (Wear Leveling, WL), causing some contents of the L2P comparison table to be changed. Therefore, the content in the HPA buffer (that is, the mirrored L2P comparison table) needs to be updated according to the changed content of the L2P comparison table. Referring to the operation sequence diagram of HPA reading as shown in Figure 8, the technical solutions of operations 711 to 733 and operations 751 to 753 are the same as those in Figure 7, and the rest of the operations are described in detail as follows:

Operation 835: Since the HPA read state has been entered, when the flash memory controller 130 receives the data block corresponding to CMD25 from the host terminal 110, it is known that each packet carries the paired LBA and PBA for a data read. Information, and check whether the LBA comparison record to read LBA data has been changed (that is, whether it is invalid). If so, the flash memory controller 130 ignores the information carried in the data block, and instead reads data from the flash memory device 150 according to the changed corresponding LBA comparison record. When the flash memory controller 130 receives the CMD 18 from the host 110 , it knows that it can start sending the designated data to the host 110 . Because the parameter of CMD18 is set to be identical with the parameter of CMD25, the data that makes flash memory controller 130 transmit is to read from flash memory device 150 according to the content in the data block that previous CMD25 writes or according to the content in the corresponding LBA comparison record after changing. Get the specified LBA information. In addition, when the L2P comparison record to read LBA data is invalid, the flashing The memory controller 130 sets the relevant Ext_CSD register to store the information of the area and sub-area in the HPA buffer of the host 110 that needs to be updated.

Operation 837: the flash memory controller 130 sends R1 for replying to CMD18, wherein both the 31st bit (Bit[31]) and the 30th bit (Bit[30]) are set to "0b1", which is used to indicate The mirroring L2P comparison table in the host terminal 110 needs to be updated.

After the host terminal 110 receives the message from the device that the L2P comparison table of the image needs to be updated, the host terminal 110 obtains the information of the area and sub-area that needs to be updated from the device side, and reads the specified part of the L2P comparison table from the device side accordingly. L2P compares the record and updates the corresponding content in the HPA buffer. Table 3 describes example command sequence details for updating the HPA buffer:

Referring to the operation sequence diagram of HPA buffer update as shown in Figure 9, the technical solutions of operations 611, 613, 617, 619, 633, 635, 651 and 653 are the same as those in Figure 6, and the rest of the operations are described in detail as follows:

Operation 915: The host 110 obtains the information of the area and the sub-area to be updated from the value of the Ext_CSD register (eg, Ext_CSD[67:64]).

Operation 931: The host 110 determines the L2P comparison record of the area and the sub-area to be acquired from the eMMC storage device according to the information obtained from the flash memory controller 130 .

Operation 955: the host 110 receives the L2P comparison record carried in each packet, and updates the corresponding part of the HPA buffer. After updating the L2P comparison record carried in the last packet, the host 110 sends a CMD13 to the flash memory controller 130, which includes a message of completion of packet reading.

For details about the execution of CMD6 in command processing operations 619 and 715, reference can be made to the method flow chart shown in FIG.

Step S1010: Receive a switching command (CMD6) from the host 110 through the host interface 131 .

Step S1020: Determine whether the reserved bits of CMD6 include the information of activating the HPA function and the acquisition function of the L2P comparison table. If yes, the process continues to step S1030. Otherwise, the flow continues to step S1040.

Step S1030: store in RAM 136 the information of entering the state of reading the HPA comparison table, use When CMD25 is received later, it can be used as the basis for judging the current device status.

Step S1040: Determine whether the reserved bits of CMD6 contain the information of activating the HPA function. If yes, the process continues to step S1050. Otherwise, the flow continues to step S1060.

Step S1050: Store the information of entering the HPA reading state in the RAM 136, which can be used as a basis for judging the current device state when receiving the CMD25 later.

Step S1060: Execute a traditional switching procedure. For example, switch the operation mode of the device side, modify the value of the Ext_CSD register, and so on.

For details about the execution of CMD25 in command processing operations 635, 735 and 835, reference can be made to the method flow chart shown in FIG. :

Step S1110 : Receive a write multi-block command ( CMD25 ) and the following data blocks from the host 110 through the host interface 131 .

Step S1121: According to the information stored in the RAM 136, it is judged whether to enter the HPA comparison table reading state or the HPA reading state. If yes, the process proceeds to step S1131 for further judgment. Otherwise, the flow proceeds to step S1123.

Step S1123 : Execute a traditional Packed Write Procedure for driving the flash memory interface 139 to write multiple packets of data to the flash memory device 150 .

Step S1131: According to the information stored in the RAM 136, it is judged whether to enter the state of reading the HPA comparison table. If yes, the flow proceeds to step S1133. Otherwise (that is, entering the HPA reading state), the flow continues to the judgment of step S1141.

Step S1133: Drive the flash memory interface 139 to read the L2P comparison record of the specified part in the L2P comparison table from the flash memory device 150 according to the information carried in the data block (that is, the information of the specific area and the specific sub-area).

Step S1135: Store the L2P comparison record in the above-mentioned multi-packet format to the RAM 136, so that the L2P comparison record can be sent to the host 110 in the multi-packet format after receiving the CMD 18 in the future.

Step S1141: Determine whether the LBA comparison record associated with the LBA data to be read has been changed. If yes, the flow continues to step S1145. Otherwise, the flow continues to step S1143.

Step S1143: Drive the flash memory interface 139 to read the data of the specified LBA from the flash memory device 150 according to the information carried in the data block (that is, the information of the L2P comparison record).

Step S1145 : drive the flash memory interface 139 to read the data of the specified LBA from the flash memory device 150 according to the changed corresponding LBA comparison record.

Step S1147: Store the specified LBA data in the RAM 136 in the multi-packet format as described above, so that the specified LBA data can be sent to the host 110 in the multi-packet format after receiving the CMD 18 in the future.

All or part of the steps in the method of the present invention can be realized by computer instructions, such as a firmware translation layer (Firmware Translation Layer, FTL) in a storage device, a specific hardware driver, and the like. In addition, it can also be implemented in other types of programs. Those skilled in the art can write the methods of the embodiments of the present invention into computer instructions, which will not be described again for the sake of brevity. The computer instructions implemented according to the method of the embodiment of the present invention can be stored in a suitable computer-readable medium, such as DVD, CD-ROM, USB disk, hard disk, and can also be placed through a network (for example, the Internet, or other appropriate means of accessing the web server.

Although the elements described above are included in FIGS. 1 to 2 , it is not excluded that more additional elements may be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts in FIG. 10 and FIG. 11 are executed in a specified order, those skilled in the art can modify the order of these steps while achieving the same effect without violating the spirit of the invention. Therefore, The invention is not limited to using only the sequence described above. In addition, those skilled in the art may also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereby.

While the invention has been described using the above examples, it should be noted that these descriptions It is not intended to limit the invention. On the contrary, the invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

611~655: Operation

Claims (18)

A method for reading data in a host performance acceleration mode, executed by a host end, comprising: sending a first switching command to a flash memory controller for requesting the flash memory controller to start a host performance acceleration function and a logical entity comparison table The acquiring function, wherein, the above-mentioned host terminal and the above-mentioned flash memory controller communicate with each other through the embedded multimedia card communication protocol; after sending the above-mentioned first switching command, send a first write multi-block command to the above-mentioned flash memory controller for Write a first data block to a flash memory controller, and the above-mentioned first data block includes a region number and a sub-area number; after sending the above-mentioned first write multi-block command, send a first read multi-block command to The above-mentioned flash memory controller is used to obtain a plurality of first logical entity comparison records corresponding to the above-mentioned area number and the above-mentioned sub-area number from the above-mentioned flash memory controller, wherein each of the above-mentioned first logical entity comparison records stores a logical address corresponding to information to a physical address; storing the first logical entity comparison record to a host performance acceleration buffer in a system memory; and providing at least one of the first logical entity comparison records to the flash memory controller for allowing The flash memory controller obtains the data of the corresponding logical address according to the provided first logical entity comparison record, and replies the data of the corresponding logical address to the host. The data reading method of the host performance acceleration mode as described in claim item 1, wherein each of the above-mentioned first logical entity comparison records includes a logical block address and a physical block address, and the logical block address is associated with For data of a first length, the physical block address is associated with data of a second length, and the second length is greater than the first length. The method for reading data in the host performance acceleration mode according to claim 2, wherein the first length is 512 bytes. The data reading method of the host performance acceleration mode as described in claim item 1, comprising: searching the above-mentioned host performance acceleration buffer to obtain a second logical entity comparison record associated with a logical block address; sending a second switch Command to the above-mentioned flash memory controller to request the above-mentioned flash memory controller to start the above-mentioned host performance acceleration function, but not to start the acquisition function of the above-mentioned logical entity comparison table; after sending the above-mentioned second switch command, send a second write to multiple blocks Command to the above-mentioned flash memory controller for writing a second data block to the above-mentioned flash memory controller, the above-mentioned second data block includes the above-mentioned second logical entity comparison record; and after issuing the above-mentioned second write multiple block command, A second read multi-block command is given to the flash memory controller for acquiring data corresponding to the second logical entity collation record from the flash memory controller. A method for reading data in a host performance acceleration mode, executed by a flash memory controller, comprising: receiving a first switching command from a host end for requesting the flash memory controller to start a host performance acceleration function and a logical entity comparison table The acquiring function, wherein, the above-mentioned host terminal and the above-mentioned flash memory controller communicate with each other through the embedded multimedia card communication protocol; enter a first state in response to the above-mentioned first switching command; receive from the above-mentioned host terminal during entering the above-mentioned first state A first write multi-block command; in response to the above-mentioned first write multi-block command, obtain an area number and a sub-area number from a first data block received from the above-mentioned host end, and read from a flash memory device corresponding to Multiple first logical entity comparison records of the above-mentioned area number and the above-mentioned sub-area number; Receive a first read multi-block command from the host during entering the first state; and transmit the first logical entity comparison record to the host in response to the first read multi-block command, wherein each of the first read multi-block commands A logical entity comparison record stores information corresponding to a logical address to a physical address, and is used to allow the host to provide at least one of the first logical entity comparison records to the flash memory controller, so that the flash memory controller according to the provided The first logical entity obtains the data of the corresponding logical address according to the record, and replies the data of the corresponding logical address to the host. The data reading method of the host performance acceleration mode as described in claim item 5, wherein, a first reserved bit in the above-mentioned first switching command includes the information of activating the above-mentioned host performance acceleration function, and the information in the above-mentioned first switching command A second reserved bit contains information to activate the acquisition function of the logical entity comparison table. The data reading method of the host performance acceleration mode as described in claim item 5, comprising: receiving a second switching command from the host end, for requesting the flash memory controller to activate the host performance acceleration function, but not to activate the logic entity The acquisition function of the comparison table; enter a second state in response to the second switching command; receive a second write multi-block command from the host during entering the second state; respond to the second write multi-block command Obtain a second logical entity comparison record from a second data block received by the host end, and read data corresponding to the second logical entity comparison record from the flash memory device; during entering the second state, from the above-mentioned The host end receives a second read multi-block command; and transmits data corresponding to the above-mentioned second logical entity collation record to the host end in response to the second read multi-block command. The data reading method of the host performance acceleration mode as described in claim item 7, wherein, a first reserved bit in the above-mentioned second switching command includes the information for activating the above-mentioned host performance acceleration function, and the information in the above-mentioned second switching command A second reserved bit contains information that does not activate the acquisition function of the logical entity comparison table. The method for reading data in the host performance acceleration mode according to claim 7, wherein any one of the first write multi-block command and the second write multi-block command is used to allow the host to continuously write data blocks to the above-mentioned flash memory controller until a predetermined number of data blocks have been written. The data reading method in the host performance acceleration mode as described in claim item 7, wherein any one of the above-mentioned first read multi-block command and the above-mentioned second read multi-block command is used to allow the above-mentioned host to continuously read from the above-mentioned The flash memory controller reads data blocks until a predetermined number of data blocks have been read. A device for reading data in a host performance acceleration mode, set in a flash memory controller, including: a host interface, coupled to a host end; a flash interface, coupled to a flash memory device; and a processing unit, coupled to the above-mentioned The host interface and the above-mentioned flash memory interface receive a first switch command from the above-mentioned host end through the above-mentioned host interface, and are used to request the above-mentioned device to start a host performance acceleration function and an acquisition function of a logical entity comparison table; in response to the above-mentioned first switch command. Entering a first state; receiving a first write multi-block command from the host side through the host interface during entering the first state; receiving the first write multi-block command from the host side through the host interface in response to the first write multi-block command Obtain an area number and a sub-area number from a first data block received, and pass the above The flash memory interface reads a plurality of first logical entity comparison records corresponding to the above-mentioned area number and the above-mentioned sub-area number from the above-mentioned flash memory device; during entering the above-mentioned first state, a first read is received from the above-mentioned host terminal through the above-mentioned host interface fetch multiple blocks command; and transmit the above-mentioned first logical entity collation record to the host through the above-mentioned host interface in response to the above-mentioned first read multiple-block command, wherein each of the above-mentioned first logical entity collation records stores a logical address corresponding to a The physical address information is used to allow the host to provide at least one first logical entity comparison record to the above-mentioned device, so that the above-mentioned device obtains the data of the corresponding logical address according to the provided first logical entity comparison record, and replies to the The data of the corresponding logical address is sent to the host, wherein the host and the device communicate with each other through the embedded multimedia card communication protocol. The device for reading data in the host performance acceleration mode as described in claim item 11, wherein the first logical entity comparison record includes a logical block address and a physical block address, and the logical block address is associated with A data of a first length, the physical block address is associated with a data of a second length, and the second length is greater than the first length. The device for reading data in the host performance acceleration mode according to claim 12, wherein the first length is 512 bytes. The device for reading data in the host performance acceleration mode as described in claim item 11, wherein a first reserved bit in the above-mentioned first switching command includes information for activating the above-mentioned host performance acceleration function, and in the above-mentioned first switching command A second reserved bit includes information for activating the acquisition function of the logical entity comparison table. The device for reading data in the host performance acceleration mode as described in claim 11, wherein, The above-mentioned processing unit receives a second switching command from the above-mentioned host side through the above-mentioned host interface, and is used to request the above-mentioned device to start the above-mentioned host performance acceleration function, but does not start the above-mentioned acquisition function of the logical entity comparison table; A second state; during entering the second state, a second write multi-block command is received from the host side through the host interface; in response to the second write multi-block command received from the host side through the host interface Obtain a second logical entity comparison record in a second data block of the above-mentioned flash memory device, and read the data corresponding to the above-mentioned second logical entity comparison record from the above-mentioned flash memory device through the above-mentioned flash memory interface; receiving a second read multi-block command from the host; and sending data corresponding to the second logical entity collation record to the host through the host interface in response to the second read multi-block command. The device for reading data in the host performance acceleration mode as described in claim item 15, wherein a first reserved bit in the above-mentioned second switching command includes information for activating the above-mentioned host performance acceleration function, and in the above-mentioned second switching command A second reserved bit includes information that does not activate the acquisition function of the logical entity comparison table. The device for reading data in the host performance acceleration mode as described in claim 15, wherein any one of the above-mentioned first write multi-block command and the above-mentioned second write multi-block command is used to continuously write data blocks to The above means until the preset number of data blocks have been written. The device for reading data in the host performance acceleration mode according to claim 15, wherein any one of the first read multi-block command and the second read multi-block command is used to make the host end continuously read from The above-mentioned device reads data blocks until a predetermined number of data blocks have been read.

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