TWI795680B - Method and apparatus for data reads in host performance acceleration mode - Google Patents
Method and apparatus for data reads in host performance acceleration mode Download PDFInfo
- Publication number
- TWI795680B TWI795680B TW109135109A TW109135109A TWI795680B TW I795680 B TWI795680 B TW I795680B TW 109135109 A TW109135109 A TW 109135109A TW 109135109 A TW109135109 A TW 109135109A TW I795680 B TWI795680 B TW I795680B
- Authority
- TW
- Taiwan
- Prior art keywords
- mentioned
- host
- flash memory
- data
- command
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Accessory Devices And Overall Control Thereof (AREA)
- Information Transfer Systems (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
本發明涉及儲存裝置,尤指一種主機效能加速模式的資料讀取方法及裝置。 The invention relates to a storage device, in particular to a method and device for reading data in a host performance acceleration mode.
閃存通常分為NOR閃存與NAND閃存。NOR閃存為隨機存取裝置,中央處理器(Host)可於位址腳位上提供任何存取NOR閃存的位址,並及時地從NOR閃存的資料腳位上獲得儲存於該位址上的資料。相反地,NAND閃存並非隨機存取,而是序列存取。NAND閃存無法像NOR閃存一樣,可以存取任何隨機位址,中央處理器反而需要寫入序列的位元組(Bytes)的值到NAND閃存中,用於定義請求命令(Command)的類型(如,讀取、寫入、抹除等),以及用在此命令上的位址。位址可指向一個頁面(閃存中寫入作業的最小資料塊)或一個區塊(閃存中抹除作業的最小資料塊)。 Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address for accessing NOR flash memory on the address pin, and obtain the data stored on the address from the data pin of NOR flash memory in time. material. In contrast, NAND flash memory is not random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the CPU needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest data block for writing operations in flash memory) or a block (the smallest data block for erasing operations in flash memory).
為了提昇閃存模組的資料寫入及讀取效能,裝置端會以多個通道並行地執行資料寫入及讀取。為了達成並行處理的目的,一段連續性的資料會分散地儲存到多個通道所連接的閃存單元,並使用邏輯實體對照表(Logical-block-address to Physical-block-address,L2P Mapping Table)紀錄使用者資料的邏輯位址(由主機端管理)與實體位址(由閃存控制器管理)間的對應關係。然而,在嵌入式多媒體卡(embedded Multi-Media Controller,e‧MMC)的儲存裝置中,隨著裝置容量的快速增加,使得邏輯實體對照表的長度也倍數成長,造成裝置端執行的傳統管理方法難以負擔。就算使用階層式子區來 管理邏輯實體對照表能夠提升邏輯實體對照轉換的效能,但是花費在邏輯實體對照轉換的時間還是大幅高於從閃存模組的快閃陣列傳輸資料到閃存控制器的資料暫存器的時間(tR)。因此,本發明提出一種主機效能加速模式的資料讀取方法及裝置,用於提昇嵌入式多媒體卡的儲存裝置的資料讀取效能。 In order to improve the data writing and reading performance of the flash memory module, the device side will execute data writing and reading in parallel through multiple channels. In order to achieve the purpose of parallel processing, a piece of continuous data will be distributed and stored in flash memory units connected to multiple channels, and recorded using the Logical-block-address to Physical-block-address (L2P Mapping Table) The corresponding relationship between the logical address (managed by the host) and the physical address (managed by the flash memory controller) of the user data. However, in the embedded Multi-Media Card (embedded Multi-Media Controller, e‧MMC) storage device, with the rapid increase of device capacity, the length of the logical entity comparison table also doubles, resulting in the traditional management method executed on the device side. unaffordable. Even using hierarchical subsections to Managing the logical entity comparison table can improve the efficiency of logical entity conversion, but the time spent on logical entity conversion is still significantly higher than the time for transferring data from the flash array of the flash memory module to the data register of the flash memory controller (tR ). Therefore, the present invention proposes a data reading method and device in a performance acceleration mode of a host for improving the data reading performance of a storage device of an embedded multimedia card.
有鑑於此,如何減輕或消除上述相關領域的缺失,實為有待解決的問題。 In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem to be solved.
本說明書涉及一種主機效能加速模式的資料讀取方法,由主機端執行,包含:發出切換命令給閃存控制器,用於請求閃存控制器啟動主機效能加速功能和邏輯實體對照表的獲取功能;發出寫入多塊命令給閃存控制器,用於寫入資料塊到閃存控制器,資料塊中包含區域編號和子區編號;發出讀取多塊命令給閃存控制器,用於從閃存控制器獲取相應於區域編號和子區編號的多個邏輯實體對照紀錄;以及儲存邏輯實體對照紀錄至系統記憶體中的主機效能加速緩衝區。 This specification relates to a method for reading data in the host performance acceleration mode, which is executed by the host side, including: sending a switching command to the flash memory controller, which is used to request the flash memory controller to start the host performance acceleration function and the acquisition function of the logical entity comparison table; Write multi-block commands to the flash memory controller, used to write data blocks to the flash memory controller, the data blocks contain area numbers and sub-area numbers; issue read multi-block commands to the flash memory controller, used to obtain corresponding data from the flash memory controller A plurality of logical entity comparison records in the area number and sub-area number; and storing the logical entity comparison records in the host performance acceleration buffer in the system memory.
本說明書另涉及一種主機效能加速模式的資料讀取方法,由閃存控制器執行,包含:從主機端接收切換命令,用於請求閃存控制器啟動主機效能加速功能和邏輯實體對照表的獲取功能;因應切換命令而進入預設狀態;在進入預設狀態期間從主機端收到寫入多塊命令;因應寫入多塊命令從主機端收到的資料塊中獲取區域編號和子區編號,以及從閃存裝置讀取相應於區域編號和子區編號的多個邏輯實體對照紀錄;在進入預設狀態期間從主機端收到讀取多塊命令;以及因應讀取多塊命令傳送邏輯實體對照紀錄給主機端。 This specification also relates to a method for reading data in the host performance acceleration mode, which is executed by the flash memory controller, including: receiving a switching command from the host end, which is used to request the flash memory controller to start the host performance acceleration function and the acquisition function of the logical entity comparison table; Enter the default state in response to the switching command; receive a write multi-block command from the host during entering the default state; obtain the area number and sub-area number from the data block received by the host in response to the write multi-block command, and from The flash memory device reads a plurality of logical entity comparison records corresponding to the area number and the sub-area number; receives a read multi-block command from the host during entering the default state; and transmits the logical entity comparison record to the host in response to the read multi-block command end.
本說明書另涉及一種主機效能加速模式的裝置,包含:主機介面;閃存介面;和處理單元。處理單元通過主機介面從主機端接收切換命令,用於請求裝置啟動主機效能加速功能和邏輯實體對照表的獲取功能;因應切換命令而進入預設狀態;在進入預設狀態期間通過 主機介面從主機端收到寫入多塊命令;因應寫入多塊命令從主機端通過主機介面收到的資料塊中獲取區域編號和子區編號,以及通過閃存介面從閃存裝置讀取相應於區域編號和子區編號的多個邏輯實體對照紀錄;在進入預設狀態期間通過主機介面從主機端收到讀取多塊命令;以及因應讀取多塊命令通過主機介面傳送邏輯實體對照紀錄給主機端。 This specification also relates to a host performance acceleration mode device, including: a host interface; a flash memory interface; and a processing unit. The processing unit receives a switching command from the host side through the host interface, and is used to request the device to start the host performance acceleration function and the acquisition function of the logical entity comparison table; enter the default state in response to the switching command; pass through during entering the default state The host interface receives the write multi-block command from the host side; in response to the write multi-block command, obtains the area number and sub-area number from the data block received by the host side through the host interface, and reads the corresponding area from the flash memory device through the flash memory interface Multiple logical entity comparison records of numbers and sub-area numbers; during the period of entering the default state, a read multi-block command is received from the host side through the host interface; and in response to the read multi-block command, the logical entity comparison record is sent to the host side through the host interface .
主機端和閃存控制器間使用嵌入式多媒體卡通訊協定彼此溝通,並且每個邏輯實體對照紀錄儲存邏輯位址的資料實際儲存在實體位址的資訊。 The host and the flash memory controller communicate with each other using the embedded multimedia card communication protocol, and each logical entity compares and records the information stored in the logical address and actually stored in the physical address.
上述實施例的優點之一,通過如上所述主機效能加速緩衝區的設置能夠讓主機端發送帶有邏輯實體對照紀錄的讀取命令給閃存控制器,用於減少閃存控制器花費時間和運算資源進行邏輯實體對照轉換。 One of the advantages of the above-mentioned embodiment is that by setting the host performance acceleration buffer as described above, the host can send a read command with a logical entity comparison record to the flash memory controller, which is used to reduce the time and computing resources spent by the flash memory controller Perform logical entity comparison conversion.
本發明的其他優點將搭配以下的說明和圖式進行更詳細的解說。 Other advantages of the present invention will be explained in more detail with the following description and drawings.
10:電子裝置 10: Electronic device
110:主機端 110: Host side
130:閃存控制器 130: Flash memory controller
131:主機介面 131: host interface
132:匯流排 132: busbar
134:處理單元 134: processing unit
135:唯讀記憶體 135: ROM
136:隨機存取記憶體 136: random access memory
137:暫存器 137: Temporary register
139:閃存介面 139: Flash interface
150:閃存裝置 150: Flash memory device
151:介面 151: interface
153#0~153#15:NAND閃存單元 153#0~153#15: NAND flash memory unit
CH#0~CH#3:通道
CE#0~CE#3:致能訊號
310:高階對照表 310: Advanced Comparison Table
330#0~330#15:L2P對照子表 330#0~330#15: L2P comparison table
400:L2P對照紀錄 400: L2P Control Record
410:邏輯區塊位址的資訊 410: Logical block address information
430:實體區塊位址的資訊 430:Information of physical block address
430-0:邏輯單元號和實體塊編號 430-0: logical unit number and physical block number
430-1:實體頁面編號 430-1: Entity page number
440:實體塊 440: Solid block
450:實體頁面 450: entity page
450#2:實體區段 450#2: Entity section
500:HPA快取 500: HPA cache
611~655,711~755,835~839,915,931,955:操作 611~655,711~755,835~839,915,931,955: Operation
S1010~S1060,S1110~S1147:方法步驟 S1010~S1060, S1110~S1147: method steps
圖1為依據本發明實施例的電子裝置的系統架構圖。 FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the invention.
圖2為依據本發明實施例的閃存裝置的示意圖。 FIG. 2 is a schematic diagram of a flash memory device according to an embodiment of the invention.
圖3為依據本發明實施例的高階對照表和邏輯實體對照子表之間的關聯示意圖。 Fig. 3 is a schematic diagram of the association between the high-level comparison table and the logical entity comparison sub-table according to an embodiment of the present invention.
圖4為依據本發明實施例的邏輯實體對照子表和實體頁面之間的關聯示意圖。 Fig. 4 is a schematic diagram of the association between the logical entity comparison sub-table and the entity page according to an embodiment of the present invention.
圖5為依據本發明實施例的主機效能加速(Host Performance Acceleration,HPA)快取的建立與運用示意圖。 FIG. 5 is a schematic diagram of establishment and operation of a Host Performance Acceleration (HPA) cache according to an embodiment of the present invention.
圖6為依據本發明實施例的HPA緩衝區初始化的操作順序圖。 FIG. 6 is an operation sequence diagram of HPA buffer initialization according to an embodiment of the present invention.
圖7和圖8為依據本發明實施例的HPA讀取的操作順序圖。 7 and 8 are operation sequence diagrams of HPA reading according to an embodiment of the present invention.
圖9為依據本發明實施例的HPA緩衝區更新的操作順序圖。 FIG. 9 is an operation sequence diagram of HPA buffer update according to an embodiment of the present invention.
圖10為依據本發明實施例的切換命令的執行方法流程圖。 FIG. 10 is a flowchart of a method for executing a switch command according to an embodiment of the present invention.
圖11為依據本發明實施例的寫入多塊命令的執行方法流程圖。 FIG. 11 is a flowchart of a method for executing a write multi-block command according to an embodiment of the present invention.
以下說明為完成發明的較佳實現方式,其目的在於描述本發明的基本精神,但並不用以限定本發明。實際的發明內容必須參考之後的權利要求範圍。 The following description is a preferred implementation mode of the invention, and its purpose is to describe the basic spirit of the invention, but not to limit the invention. For the actual content of the invention, reference must be made to the scope of the claims that follow.
必須了解的是,使用於本說明書中的“包含”、“包括”等詞,用以表示存在特定的技術特徵、數值、方法步驟、作業處理、元件以及/或組件,但並不排除可加上更多的技術特徵、數值、方法步驟、作業處理、元件、組件,或以上的任意組合。 It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, components and/or components, but do not exclude the possibility of adding More technical characteristics, numerical values, method steps, operation processes, components, components, or any combination of the above.
於權利要求中使用如“第一”、“第二”、“第三”等詞是用來修飾權利要求中的元件,並非用來表示之間具有優先順序,前置關係,或者是一個元件先於另一個元件,或者是執行方法步驟時的時間先後順序,僅用來區別具有相同名字的元件。 Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a priority order, a pre-relationship, or an element An element preceding another element, or a chronological order in performing method steps, is only used to distinguish elements with the same name.
必須了解的是,當元件描述為“連接”或“耦接”至另一元件時,可以是直接連結、或耦接至其他元件,可能出現中間元件。相反地,當元件描述為“直接連接”或“直接耦接”至另一元件時,其中不存在任何中間元件。使用來描述元件之間關係的其他語詞也可類似方式解讀,例如“介於”相對於“直接介於”,或者是“鄰接”相對於“直接鄰接”等等。 It must be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements may be interpreted in a similar fashion, eg, "between" versus "directly between," or "adjacent" versus "directly adjacent," and so forth.
參考圖1。電子裝置10包含主機裝置(又可稱主機端)110、閃存控制器130及閃存裝置150,並且閃存控制器130及閃存裝置150可合稱為裝置端(Device Side)。電子裝置10可實施於個人電腦、筆記型電腦(Laptop PC)、平板電腦、手機、數位相機、數位攝影機等電子產品之中。主機裝置110與閃存控制器130的主機介面(Host Interface)131可以嵌入式多媒體卡(embedded Multi-Media Controller,e‧MMC/eMMC)通訊協定彼此溝通。閃存控制器130的閃存介面139與閃存裝置150可以雙倍資料率(Double Data Rate,DDR)通訊協定彼此溝通,例如,開放NAND快閃介面(Open
NAND Flash Interface,ONFI)、雙倍資料率開關(DDR Toggle)或其他通訊協定。閃存控制器130包含處理單元134,可使用多種方式實施,如使用通用硬體(例如,微控制單元、中央處理器、具平行處理能力的多處理器、圖形處理器或其他具運算能力的處理器),並且在執行軟體以及/或韌體指令時,提供之後描述的功能。處理單元134通過主機介面131接收eMMC命令,並執行這些命令。閃存控制器130包含隨機存取記憶體(Random Access Memory,RAM)136,可實施為動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)、靜態隨機存取記憶體(Static Random Access Memory,SRAM)或上述兩者的結合,用於配置空間作為資料緩衝區。隨機存取記憶體136另可儲存執行過程中需要的資料,例如,變數、資料表等。閃存控制器130包含唯讀記憶體(Read Only Memory,ROM)135,用於儲存開機時需要執行的程式碼。閃存介面139包含NAND閃存控制器(NAND Flash Controller,NFC),提供存取閃存裝置150時需要的功能,例如命令序列器(Command Sequencer)、低密度奇偶校驗(Low Density Parity Check,LDPC)等。
Refer to Figure 1. The
閃存控制器130包含暫存器137,用於儲存各式各樣的參數值。在eMMC規範(例如發表在2014年七月的eMMC電器標準5.1)中,暫存器137包含32位元的操作狀態暫存器(Operation Condition Register,OCR)、128位元的裝置識別暫存器(Device IDentification,CID Register)、128位元的裝置特用資料暫存器(Device-Specific Data,CSD Register)、512位元組的擴充裝置特用資料暫存器(Extended CSD Register,可簡稱Ext_CSD暫存器)等。Ext_CSD暫存器定義裝置屬性(Device Properties)和選定模式(Selected Modes),其中的最高有效320位元組是屬性段(Properties Segment),用於定義裝置的能力,並且不能夠被主機端110修改,另外的較低有效192位元
組是模式段(Modes Segment),定義裝置目前正運行的設置。主機端110可通過切換命令(SWITCH command,CMD6)改變這些模式。eMMC規範在Ext_CSD暫存器中保留了若干區域可以讓裝置端的製造商自由運用,用於完成主機效能加速模式(Host Performance Acceleration,HPA Mode)的功能。
The
閃存控制器130中可配置匯流排架構(Bus Architecture)132,用於讓元件之間彼此耦接以傳遞資料、位址、控制訊號等,這些元件包含主機介面131、處理單元134、ROM 135、RAM 136、暫存器137、閃存介面139等。在一些實施例中,主機介面131、處理單元134、ROM 135、RAM 136、暫存器137與閃存介面139可通過單一匯流排彼此耦接。在另一些實施例中,閃存控制器130中可配置高速匯流排,用於讓處理單元134、ROM 135、RAM 136與暫存器137彼此耦接,並且配置低速匯流排,用於讓處理單元134、主機介面131與閃存介面139彼此耦接。匯流排包含並行的物理線,連接閃存控制器130中兩個以上的組件。
A bus architecture (Bus Architecture) 132 can be configured in the
閃存裝置150提供大量的儲存空間,通常是數百個千兆位元組(Gigabytes,GB),甚至是數個兆兆位元組(Terabytes,TB),用於儲存大量的使用者資料,例如高解析度圖片、影片等。閃存裝置150中包含控制電路以及記憶體陣列,記憶體陣列中的記憶單元可在抹除後組態為單層式單元(Single Level Cells,SLCs)、多層式單元(Multiple Level Cells,MLCs)三層式單元(Triple Level Cells,TLCs)、四層式單元(Quad-Level Cells,QLCs)或上述的任意組合。處理單元134通過閃存介面139寫入使用者資料到閃存裝置150中的指定位址(目的位址),以及從閃存裝置150中的指定位址(來源位址)讀取使用者資料和L2P對照表中的指定部分。閃存介面139使用數個電子訊號來協調閃存控制器130與閃存裝置150間的資料與命令傳遞,包含資料線(Data Line)、時脈訊號(Clock
Signal)與控制訊號(Control Signal)。資料線可用於傳遞命令、位址、讀出及寫入的資料;控制訊號線可用於傳遞晶片致能(Chip Enable,CE)、位址提取致能(Address Latch Enable,ALE)、命令提取致能(Command Latch Enable,CLE)、寫入致能(Write Enable,WE)等控制訊號。
The
參考圖2,閃存裝置150中的介面151可包含四個輸出入通道(I/O channels,以下簡稱通道)CH#0至CH#3,每一個通道連接四個NAND閃存單元,例如,通道CH#0連接NAND閃存單元153#0、153#4、153#8及153#12。每個NAND閃存單元可封裝為獨立的芯片(die)。閃存介面139可通過介面151發出致能訊號CE#0至CE#3中的一個來致能NAND閃存單元153#0至153#3、153#4至153#7、153#8至153#11、或153#12至153#15,接著以並行的方式從致能的NAND閃存單元讀取使用者資料,或者寫入使用者資料至致能的NAND閃存單元。
Referring to FIG. 2, the
由於一段連續性(也就是一段連續的邏輯區塊位址,Logical Block Addresses,LBAs)的資料被分散地儲存到多個通道所連接的NAND閃存單元,閃存控制器130使用邏輯實體對照表(Logical-block-address to Physical-block-address,L2P Mapping Table)紀錄使用者資料的邏輯位址(由主機裝置110管理)與實體位址(由閃存控制器130管理)間的對應關係。L2P對照表包含多筆紀錄,依邏輯位址的順序儲存每個邏輯位址的使用者資料實際儲存在哪個實體位址的資訊。一段連續LBA的資料可切分為數個區域(Regions),以區域編號識別,而每個區域可更切分出數個子區(Sub-regions),以子區編號識別。例如,使用LBA定址的128GB的資料可分為16個8GB的區域,而每個8GB的區域可更分出256個32MB的子區。在eMMC規範中,每個LBA關聯於(或指向)512位元組(Bytes)的資料。然而,由於RAM 136無法提供足夠空間儲存整個L2P對照表
以供處理單元134將來於資料讀取操作時快速查找,整個L2P對照表可依據區域和子區的劃分來切出多個子表,並分別儲存在非揮發性的閃存裝置150的不同實體位址,使得將來於資料讀取操作時只要從閃存裝置150讀取相應的子表至RAM 136即可。參考圖3,整個L2P對照表可切成子表330#0~330#15。處理單元134更維護高階對照表(High-level Mapping Table)310,包含多個紀錄,依邏輯位址的順序儲存每個LBA區段關聯的子表的實體位址資訊。例如,第0個至第4095個LBA的關聯子表330#0儲存在特定邏輯單元號(Logical Unit Number,LUN)的特定實體塊中(字母”Z”可代表LUN和實體塊的編號)的第0個實體頁面,第4096個至第8191個LBA的關聯子表330#1儲存在特定LUN的特定實體塊中的第1個實體頁面,依此類推。雖然圖3中只包含16個子表,但是所屬技術領域的技術人員可因應閃存裝置150的容量,設置更多的子表,本發明並不因此侷限。
Because the data of a section of continuity (that is, a section of continuous Logical Block Addresses, Logical Block Addresses, LBAs) is dispersedly stored in the NAND flash memory cells connected to multiple channels, the
為了配合閃存裝置150的實體配置,閃存控制器130可讓一個實體區塊位址(Physical Block Address,PBA)關聯於(或指向)4KB、8KB或16KB的資料,此長度大於eMMC規範的一個LBA所關聯的資料的長度(512B)。因為LBA與PBA所關聯的資料長度不一致,每個子表中的每個紀錄包含邏輯位址和實體位址的資訊,用於精確指出閃存裝置150中的位址。參考圖4,子表330#0依序儲存從LBA#0至LBA#4095的定址資訊(Addressing Information)。定址資訊可以八個位元組表示:四個位元組代表LBA;其他四個位元組代表PBA。舉例來說,子表330#0中關聯於LBA#2的紀錄400儲存LBA 410和PBA 430的資訊。PBA 430中的二個位元組430-0紀錄邏輯單元號和實體塊編號(Physical Block Number);其他二個位元組430-1紀錄實體頁面編號(Physical Page Number)。所以,相應於LBA#2的實體位址資訊400可指向實體塊440的實體頁面450中的特定區段(Sector)450#2。
In order to cooperate with the physical configuration of the
為了解決閃存控制器130花費過多時間在邏輯實體對照轉換上的問題,本發明實施例在現行eMMC規範的主機裝置通訊架構(Host-Device Communications Architecture)的基礎上加上HPA的新功能。HPA讓原先由閃存控制器130實施的需要耗費大量時間的邏輯實體對照轉換的工作負荷,轉換到主機端110,可提升短長度資料的隨機讀取效能,短長度資料可指長度從512B到32KB的資料。參考圖5,主機端110在其系統記憶體(System Memory)中配置空間作為HPA快取500,用於暫存由裝置端維護與管理的L2P對照表的資訊。HPA快取500儲存多個從裝置端接收的L2P對照紀錄(L2P Mapping Records),每個L2P對照紀錄紀錄相應於一個LBA的定址資訊。接著,主機端110可發出攜帶L2P對照紀錄的命令給裝置端,用於取得指定LBA的使用者資料。閃存控制器130可直接根據L2P對照紀錄中的資訊來驅動閃存介面139從閃存裝置150讀取指定LBA的使用者資料,而不需要像以前一樣得花費時間和運算資源從閃存裝置150讀取相應子表並進行邏輯實體位址轉換後才能從閃存裝置150讀取指定LBA的使用者資料。針對HPA快取500的建立和運用,可分為三個階段:
In order to solve the problem that the
階段I(HPA初始化):主機端110讀取閃存控制器130中暫存器137的值,檢查eMMC儲存裝置(或稱裝置端,至少包含閃存控制器130和閃存裝置150)是否支援HPA功能。如果是,主機端110在系統記憶體中配置空間,作為HPA L2P對照表區。
Stage I (HPA initialization): The
階段II(HPA對照表管理):如果eMMC儲存裝置支援HPA功能,主機端110發出一系列命令,用於向閃存控制器130請求讀取L2P對照表。為反應這一系列命令,閃存控制器130傳送全部或一部份的L2P對照表給主機端110,讓主機端110把獲得的對照表儲存在HPA L2P對照表區(這可稱為鏡像L2P對照表,Mirrored L2P Mapping Table)。當對應於鏡像L2P對照表的實際L2P對照表因資料寫入、
資料修剪(Data Trimming)、垃圾回收(Garbage Collection,GC)、磨耗平均(Wear Leveling)等程序而改變後,閃存控制器130通知主機端110,主機端110的系統記憶體中的全部或者相應部分的L2P對照表需要更新。
Phase II (HPA comparison table management): If the eMMC storage device supports the HPA function, the
階段III(HPA讀取):主機端110發出帶有L2P對照紀錄的一系列命令給eMMC儲存裝置以請求獲取特定LBA的資料(特別是小塊長度的不連續資料,如512B到32KB的不連續資料),其中的L2P對照紀錄是從鏡像L2P對照表中搜索而得。接著,閃存控制器130依據L2P對照紀錄的內容從閃存裝置150的PBA讀取指定LBA的資料,並且回覆讀取的資料給主機端110,使得eMMC儲存裝置能夠節省為進行邏輯實體對照轉換而讀取並搜索L2P對照表的時間。
Phase III (HPA read): The
在eMMC規範中,Ext_CSD[160](也稱為PARTITIONING_SUPPORT[160])定義支援區段特性(Supported Partition Features),其中的Bits[7:3]保留給eMMC儲存裝置的製造商自由使用。Ext_CSD暫存器的第160個位元組的第3個位元(Ext_CSD[160],Bit[3])可用來定義eMMC儲存裝置是否支援HPA功能,若支援則設為“1”,若關閉則設為“0”。在eMMC儲存裝置初始化的過程中,處理單元134可將暫存器137中的Ext_CSD[160],Bit[3]設為“1”。雖然本發明實施例描述了以Ext_CSD[160],Bit[3]定義eMMC儲存裝置是否支援HPA功能的技術方案,所屬技術領域人員可改變設計來使用Ext_CSD暫存器中的其他保留位元,例如Ext_CSD[511:506]、Ext_CSD[485:309]、Ext_CSD[306]、Ext_CSD[233]、Ext_CSD[227]、Ext_CSD[204]、Ext_CSD[195]、Ext_CSD[193]、Ext_CSD[190]、Ext_CSD[188]、Ext_CSD[186]、Ext_CSD[184]、Ext_CSD[182]、Ext_CSD[180]、Ext_CSD[176]、Ext_CSD[172]、Ext_CSD[170]、Ext_CSD[135]、Ext_CSD[129:128]、Ext_CSD[127:64]、Ext_CSD[28:27]、Ext_CSD[14:0]等,本發明並不
因此侷限。
In the eMMC specification, Ext_CSD[160] (also called PARTITIONING_SUPPORT[160]) defines Supported Partition Features, and Bits[7:3] are reserved for free use by manufacturers of eMMC storage devices. The third bit of the 160th byte of the Ext_CSD register (Ext_CSD[160], Bit[3]) can be used to define whether the eMMC storage device supports the HPA function, if it supports it, set it to "1", if it is disabled is set to "0". During the initialization process of the eMMC storage device, the
此外,閃存控制器130可使用成對的Ext_CSD暫存器來記錄主機端110緩存的L2P對照表中需要更新的指定區域和子區的資訊。例如,Ext_CSD暫存器的第64個位元組(Ext_CSD[64])和第66個位元組(Ext_CSD[66])為一對,用於分別指出第0個區域(Region#0)和第160個子區(SubRegion#160)。Ext_CSD暫存器的第65個位元組(Ext_CSD[65])和第67個位元組(Ext_CSD[67])為另一對,用於分別指出第0個區域(Region#0)和第18個子區(SubRegion#18)。
In addition, the
在eMMC規範中,切換命令(CMD6)是由主機端110發出,用於切換選定裝置的操作模式或者修改Ext_CSD暫存器的值,而參數的第26到31位元(Bits[31:26])是保留位元。主機端110可設定CMD6的第26個位元(CMD6,Bit[26])來表示是否啟動HPA功能,若啟動則設為“1”,若關閉則設為“0”。雖然本發明實施例描述了以CMD6,Bit[26]定義是否啟動HPA功能的技術方案,所屬技術領域人員可改變設計來使用CMD6的參數中的其他保留位元,本發明並不因此受限。主機端110可設定CMD6的第27個位元(CMD6,Bit[27])來表示是否啟動L2P對照表的獲取功能,若啟動則設為“1”,若關閉則設為“0”。雖然本發明實施例描述了以CMD6,Bit[27]定義是否啟動L2P對照表的獲取功能的技術方案,所屬技術領域人員可改變設計來使用CMD6的參數中的其他保留位元,本發明並不因此受限。
In the eMMC specification, the switching command (CMD6) is issued by the
在eMMC規範中,設定塊數命令(CMD23)是由主機端110發出,用於表示之後的打包寫入命令的塊數目,或之後的打包讀取命令的標題(Header)的塊數目。當CMD23關聯於之後的打包寫入命令時,參數中的第30個位元(Bit[30])設為“0b1”,並且CMD23的參數中的第0到第15個位元(Bits[15:0])用來表示塊數目。當CMD23關聯於之後的打包寫入命令或打包讀取命令時,參數中的第30個位元(Bit[30])設為“0b1”。CMD23的參數中的第0到第15個位元
(Bits[15:0])用來表示塊數目。
In the eMMC specification, the set block number command (CMD23) is issued by the
在eMMC規範中,寫入多塊命令(CMD25)是由主機端110發出,用於不斷寫入資料塊到eMMC儲存裝置,直到發出停止傳輸命令(STOP_TRANSMISSION Command,CMD12),或者請求數目的資料塊已經寫入完畢。主機端110可通過CMD23及CMD25傳送L2P對照表中的指定區域和子區的資訊,請求閃存控制器130準備指定區域和子區的L2P對照紀錄。此外,主機端110可通過CMD23及CMD25傳送L2P對照紀錄,請求閃存控制器130據以準備資料以供將來的讀取。CMD25的參數中的第0到第31個位元(Bits[31:0])表示資料位址。
In the eMMC specification, the write multi-block command (CMD25) is issued by the
在eMMC規範中,讀取多塊命令(CMD18)是由主機端110發出,用於不斷從eMMC儲存裝置讀取資料塊,直到請求數目的資料塊已經讀取完畢,或者被停止命令(Stop Command)打斷。也就是說,CMD18請求eMMC儲存裝置傳送先前指出數目的資料塊給主機端110。CMD18的參數中的第0到第31個位元(Bits[31:0])表示資料位址。主機端110可通過CMD23及CMD18請求閃存控制器130傳送指定區域和子區(在先前的CMD25中定義)的L2P對照紀錄。參考如圖4所示的範例,每個L2P對照紀錄的長度是8B,使得每個資料塊可攜帶最多32個L2P對照紀錄。此外,主機端110可通過CMD23及CMD18請求閃存控制器130傳送相應於L2P對照紀錄(在先前的CMD25中定義)的資料。
In the eMMC specification, the read multi-block command (CMD18) is issued by the
在eMMC規範中,正常回覆命令(Normal Response Command,R1)是由閃存控制器130發出,用於告訴主機端110特定訊息。R1的長度是48位元,其中的第40到第45位元(Bits[45:40])紀錄要回覆命令的索引,並且第8到第39位元(Bits[39:8])紀錄裝置狀態(Device Status)。當R1的第31個位元(Bit[31])設為“0b1”時,代表位址超過範圍(ADDRESS_OUT_OF_RANGE)。當R1的第30個位元
(Bit[30])設為“0b1”時,代表位址不適配(ADDRESS_MISALIGN)。當HPA功能啟動但L2P對照表的獲取功能未啟動時,如果CMD25中攜帶的L2P對照紀錄中有部分的PBA失效了,閃存控制器130可把用於回覆之後CMD18的R1的第31個位元(Bit[31])和第30個位元(Bit[30])都設為“0b1”,用於指出主機端110中緩存的L2P對照紀錄需要更新。
In the eMMC specification, a normal response command (Normal Response Command, R1) is issued by the
針對階段I和階段II中關於HPA L2P對照表區(又可稱為HPA緩衝區)的建立,在eMMC儲存裝置初始化後,主機端110首次從裝置端讀取L2P對照表,並且儲存到HPA緩衝區。表1描述範例的命令順序細節,用於初始化HPA緩衝區:
參考如圖6所示的HPA緩衝區初始化的操作順序圖,詳細說明如下: Referring to the operation sequence diagram of HPA buffer initialization shown in Figure 6, the details are as follows:
操作611:主機端110發出命令給閃存控制器130,用於向閃存控制器130請求獲取Ext_CSD暫存器的值。
Operation 611: the
操作613:為反應通過主機介面131所接收的暫存器讀取命令,處理單元134獲取暫存器137中Ext_CSD暫存器的值,並通過主機介面131回覆給主機端110。
Operation 613 : In response to the register read command received through the
操作615:主機端110可檢查Ext_CSD暫存器的值(例如,Ext_CSD[160],Bit[3])來判斷此eMMC儲存裝置是否支援HPA功能。如果是,則繼續進行操作617的處理。如果不是,則不啟動HPA功能。
Operation 615: the
操作617:主機端110發出切換命令(CMD6)給閃存控制器130來啟動HPA功能和L2P對照表的獲取功能。例如,參考表1的第二橫行,主機端110可將CMD6的參數設為“0x0C000000”,也就是包含Bit[26]=”0b1”及Bit[27]=”0b1”,用於指示閃存控制器130啟動這兩個功能。
Operation 617: the
操作619:當閃存控制器130收到如上所示的切換命令後,進入HPA對照表讀取狀態(HPA_Mapping_READ state),用於準備傳送一部分的L2P對照表給主機端110。
Operation 619: After the
操作631:主機端110在系統記憶體中配置空間給HPA緩衝區,並依據作業系統、驅動程式、應用程式等的需要決定欲向eMMC儲存裝
置獲取的區域和子區的L2P對照紀錄。
Operation 631: The
操作633:主機端110發出設定塊數命令(CMD23)給閃存控制器130,用於通知閃存控制器130將傳送多少個資料塊。例如,參考表1的第三橫行,主機端110可將CMD23的參數設為“0x40000001”,也就是包含Bit[30]=”0b1”及Bits[15:0]=”0x0001”,表示之後將寫入一個資料塊到閃存控制器130。接著,主機端110發出寫入多塊命令(CMD25)給閃存控制器130,用於不斷寫入資料塊到閃存控制器130,直到請求數目的資料塊已經寫入完畢。例如,參考表1的第四橫行,主機端110可將CMD25的參數設為“0x01E2A3E0”,代表特定資料位址。每個資料塊可分為32包(Packets),而每一包的長度為16B。每包中的2個位元組可指出特定區域的編號,而其餘的14個位元組可指出數個特定子區的編號。例如,當一包中包含{Region#0,SubRegion#0,SubRegion#1,SubRegion#2,SubRegion#3}的資訊時,代表L2P對照表的指定部分關聯到第0個區域中的第0到第3個子區。接著,主機端110發出設定塊數命令(CMD23)給閃存控制器130,用於通知閃存控制器130將接收多少個資料塊。例如,參考表1的第五橫行,主機端110可將CMD23的參數設為“0x40000020”,也就是包含Bit[30]=”0b1”及Bits[15:0]=”0x0020”,表示之後將從閃存控制器130讀取32個資料塊,也就是最多1024個L2P對照紀錄。接著,主機端110發出讀取多塊命令(CMD18)給閃存控制器130,用於不斷從閃存控制器130讀取資料塊,直到請求數目的資料塊已經讀取完畢。例如,參考表1的第六橫行,主機端110可將CMD18的參數設為“0x01E2A3E0”,代表特定資料位址。
Operation 633: the
操作635:由於已經進入HPA對照表讀取狀態,當閃存控制器130從主機端110接收到相應於CMD25的資料塊時,知道其中的每一包攜帶了L2P對照表的指定部分的資訊,並且可據以從閃存裝置150讀取請求的L2P對照紀錄。此外,當閃存控制器130從主機端110接收到
CMD18時,知道可以開始傳送指定部分的L2P對照紀錄給主機端110。由於CMD18的參數被設定為與CMD25的參數相同,使得閃存控制器130傳送的資料是依據先前CMD25寫入的資料塊中的內容從閃存裝置150讀取的指定部分的L2P對照紀錄。
Operation 635: Since the read state of the HPA comparison table has been entered, when the
操作651:閃存控制器130將請求的L2P對照紀錄組織成指定數目的資料塊中的多個包。
Operation 651: The
操作653:閃存控制器130持續傳送組織好的資料塊給主機端110,直到指定數目的資料塊傳送完畢。接著,當從主機端110接收到打包讀取完成的訊息時,離開HPA對照表讀取狀態並進入eMMC規範的傳送狀態(Transfer State)。
Operation 653: The
操作655:主機端110接收每包中攜帶的L2P對照紀錄,並且儲存在HPA緩衝區。當儲存完最後一包中攜帶的L2P對照紀錄後,主機端110發出傳送狀態命令(SEND_STATUS command,CMD13)給閃存控制器130,其中包含打包讀取完成的訊息。
Operation 655: The
針對階段III的資料讀取,表2描述範例的命令順序細節,用於使用HPA功能讀取資料:
參考如圖7所示的HPA讀取的操作順序圖,詳細說明如下: Referring to the operation sequence diagram of HPA reading shown in Figure 7, the details are as follows:
操作711:主機端110發現即將進行短長度資料的隨機讀取。
Operation 711: The
操作713:主機端110發出切換命令(CMD6)給閃存控制器130來啟動HPA功能。例如,參考表2的第二橫行,主機端110可將CMD6的參數設為“0x04000000”,也就是包含Bit[26]=”0b1”及Bit[27]=”0b0”,用於指示閃存控制器130只啟動HPA功能。
Operation 713: the
操作715:當閃存控制器130收到如上所示的切換命令後,進入HPA讀取狀態(HPA_READ state)。
Operation 715: After the
操作731:主機端110搜索HPA緩衝區中的鏡像L2P對照表以獲取相應於多個LBA的L2P對照紀錄。
Operation 731: The
操作733:主機端110發出設定塊數命令(CMD23)給閃存控制器130,用於通知閃存控制器130將傳送多少個資料塊。例如,參考表2的第三橫行,主機端110可將CMD23的參數設為“0x40000001”,也就是包含Bit[30]=”0b1”及Bits[15:0]=”0x0001”,表示之後將寫入一個
資料塊到閃存控制器130。接著,主機端110發出寫入多塊命令(CMD25)給閃存控制器130,用於不斷寫入資料塊到閃存控制器130,直到請求數目的資料塊已經寫入完畢。例如,參考表2的第四橫行,主機端110可將CMD25的參數設為“0x01521182”,代表特定資料位址。每個資料塊可分為32包(Packets),而每一包的長度為16B。每包關聯於一對LBA和PBA資訊,其中的8個位元組可指出特定LBA,而其餘的8個位元組可指出特定PBA。接著,主機端110發出設定塊數命令(CMD23)給閃存控制器130,用於通知閃存控制器130將接收多少個資料塊。例如,參考表2的第五橫行,主機端110可將CMD23的參數設為“0x40000020”,也就是包含Bit[30]=”0b1”及Bits[15:0]=”0x0020”,表示之後將從閃存控制器130讀取32個資料塊,也就是最多1024個LBA的資料。接著,主機端110發出讀取多塊命令(CMD18)給閃存控制器130,用於不斷從閃存控制器130讀取資料塊,直到請求數目的資料塊已經讀取完畢。例如,參考表2的第六橫行,主機端110可將CMD18的參數設為“0x01521182”,代表特定資料位址。
Operation 733: the
操作735:由於已經進入HPA讀取狀態,當閃存控制器130從主機端110接收到相應於CMD25的資料塊時,知道其中的每一包攜帶了為一個資料讀取的成對LBA和PBA的資訊,並且可據以從閃存裝置150讀取請求的資料。此外,當閃存控制器130從主機端110接收到CMD18時,知道可以開始傳送指定的資料給主機端110。由於CMD18的參數被設定為與CMD25的參數相同,使得閃存控制器130傳送的資料是依據先前CMD25寫入的資料塊中的內容從閃存裝置150讀取的指定LBA的資料。
Operation 735: Since the HPA read state has been entered, when the
操作751:閃存控制器130將請求的資料組織成指定數目的資料塊中的多個包。
Operation 751: The
操作753:閃存控制器130持續傳送組織好的資料塊給主機端110,
直到指定數目的資料塊傳送完畢。接著,當從主機端110接收到打包讀取完成的訊息時,離開HPA讀取狀態並進入eMMC規範的傳送狀態。
Operation 753: the
操作755:主機端110接收每包中攜帶的資料,並且儲存在系統記憶體的資料緩衝區。當儲存完最後一包中攜帶的資料後,主機端110發出傳送狀態命令(CMD13)給閃存控制器130,其中包含打包讀取完成的訊息。
Operation 755: The
針對階段II中關於HPA緩衝區的更新,在裝置端運行的過程中,主機端110可請求閃存控制器130執行資料寫入、資料剪除(Data Trims)、塊抹除(Block Erases)等操作,而閃存控制器130可主動執行垃圾回收(Garbage Collection,GC)、磨耗平均(Wear Leveling,WL)等程序,造成L2P對照表的部分內容被改變。所以,HPA緩衝區中的內容(也就是鏡像L2P對照表)需要因應L2P對照表的變更內容而更新。參考如圖8所示的HPA讀取的操作順序圖,其中的操作711到733和操作751到753的技術方案相同於圖7,其餘的操作詳細說明如下:
Regarding the updating of the HPA buffer in Phase II, during the operation of the device, the
操作835:由於已經進入HPA讀取狀態,當閃存控制器130從主機端110接收到相應於CMD25的資料塊時,知道其中的每一包攜帶了為一個資料讀取的成對LBA和PBA的資訊,並且檢查欲讀取LBA資料的LBA對照紀錄是否被改變(也就是是否無效)。如果是,則閃存控制器130忽略資料塊中攜帶的資訊,改為依據變更後的相應LBA對照紀錄從閃存裝置150讀取資料。當閃存控制器130從主機端110接收到CMD18時,知道可以開始傳送指定的資料給主機端110。由於CMD18的參數被設定為與CMD25的參數相同,使得閃存控制器130傳送的資料是依據先前CMD25寫入的資料塊中的內容或者依據變更後的相應LBA對照紀錄中的內容從閃存裝置150讀取的指定LBA的資料。此外,當欲讀取LBA資料的L2P對照紀錄無效時,閃
存控制器130設定相關的Ext_CSD暫存器來儲存主機端110的HPA緩衝區中需要更新的區域和子區的資訊。
Operation 835: Since the HPA read state has been entered, when the
操作837:閃存控制器130發出用於回覆CMD18的R1,其中的第31個位元(Bit[31])和第30個位元(Bit[30])都設為“0b1”,用於指出主機端110中的鏡像L2P對照表需要更新。
Operation 837: the
在主機端110從裝置端接收到鏡像L2P對照表需要更新的訊息後,主機端110從裝置端獲取需要更新的區域和子區的資訊,並據以從裝置端讀取L2P對照表中指定部分的L2P對照紀錄,並且更新HPA緩衝區中的相應內容。表3描述範例的命令順序細節,用於更新HPA緩衝區:
參考如圖9所示的HPA緩衝區更新的操作順序圖,其中的操作611、613、617、619、633、635、651和653的技術方案相同於圖6,其餘的操作詳細說明如下:
Referring to the operation sequence diagram of HPA buffer update as shown in Figure 9, the technical solutions of
操作915:主機端110從Ext_CSD暫存器(例如,Ext_CSD[67:64])的值獲取需要更新的區域和子區的資訊。
Operation 915: The
操作931:主機端110依據從閃存控制器130獲取的資訊決定欲向eMMC儲存裝置獲取的區域和子區的L2P對照紀錄。
Operation 931: The
操作955:主機端110接收每包中攜帶的L2P對照紀錄,並且更新HPA緩衝區中的相應部分內容。當更新完最後一包中攜帶的L2P對照紀錄後,主機端110發出CMD13給閃存控制器130,其中包含打包讀取完成的訊息。
Operation 955: the
命令處理操作619、715中關於CMD6的執行細節可參考如圖10所示的方法流程圖,此方法由處理單元134在載入並執行相關軟體或韌體程式碼時實施,進一步說明如下:
For details about the execution of CMD6 in
步驟S1010:通過主機介面131從主機端110接收到切換命令(CMD6)。
Step S1010: Receive a switching command (CMD6) from the
步驟S1020:判斷CMD6的保留位元中是否包含啟動HPA功能和L2P對照表的獲取功能的資訊。如果是,流程繼續步驟S1030的處理。否則,流程繼續步驟S1040的處理。 Step S1020: Determine whether the reserved bits of CMD6 include the information of activating the HPA function and the acquisition function of the L2P comparison table. If yes, the process continues to step S1030. Otherwise, the flow continues to step S1040.
步驟S1030:在RAM 136儲存進入HPA對照表讀取狀態的資訊,用
於讓之後接收到CMD25時可以作為判斷目前裝置狀態的依據。
Step S1030: store in
步驟S1040:判斷CMD6的保留位元中是否包含啟動HPA功能的資訊。如果是,流程繼續步驟S1050的處理。否則,流程繼續步驟S1060的處理。 Step S1040: Determine whether the reserved bits of CMD6 contain the information of activating the HPA function. If yes, the process continues to step S1050. Otherwise, the flow continues to step S1060.
步驟S1050:在RAM 136儲存進入HPA讀取狀態的資訊,用於讓之後接收到CMD25時可以作為判斷目前裝置狀態的依據。
Step S1050: Store the information of entering the HPA reading state in the
步驟S1060:執行傳統的切換程序。例如,切換裝置端的操作模式、修改Ext_CSD暫存器的值等等。 Step S1060: Execute a traditional switching procedure. For example, switch the operation mode of the device side, modify the value of the Ext_CSD register, and so on.
命令處理操作635、735和835中關於CMD25的執行細節可參考如圖11所示的方法流程圖,此方法由處理單元134在載入並執行相關軟體或韌體程式碼時實施,進一步說明如下:
For details about the execution of CMD25 in
步驟S1110:通過主機介面131從主機端110接收到寫入多塊命令(CMD25)及跟隨的資料塊。
Step S1110 : Receive a write multi-block command ( CMD25 ) and the following data blocks from the
步驟S1121:依據RAM 136中儲存的資訊判斷是否進入HPA對照表讀取狀態或HPA讀取狀態。如果是,流程繼續進行步驟S1131的進一步判斷。否則,流程繼續進行步驟S1123的處理。
Step S1121: According to the information stored in the
步驟S1123:執行傳統的打包寫入程序(Packed Write Procedure),用於驅動閃存介面139寫入多包的資料至閃存裝置150。
Step S1123 : Execute a traditional Packed Write Procedure for driving the
步驟S1131:依據RAM 136中儲存的資訊判斷是否進入HPA對照表讀取狀態。如果是,流程繼續進行步驟S1133的處理。否則(也就是進入HPA讀取狀態),流程繼續進行步驟S1141的判斷。
Step S1131: According to the information stored in the
步驟S1133:驅動閃存介面139依據資料塊中攜帶的資訊(也就是特定區域和特定子區的資訊)從閃存裝置150讀取L2P對照表中指定部分的L2P對照紀錄。
Step S1133: Drive the
步驟S1135:以如上所述多包的格式儲存L2P對照紀錄到RAM 136,使得將來在收到CMD18後能夠以多包的格式傳送L2P對照紀錄給主機端110。
Step S1135: Store the L2P comparison record in the above-mentioned multi-packet format to the
步驟S1141:判斷欲讀取LBA資料所關聯的LBA對照紀錄是否已經被改變。如果是,則流程繼續進行步驟S1145的處理。否則,流程繼續進行步驟S1143的處理。 Step S1141: Determine whether the LBA comparison record associated with the LBA data to be read has been changed. If yes, the flow continues to step S1145. Otherwise, the flow continues to step S1143.
步驟S1143:驅動閃存介面139依據資料塊中攜帶的資訊(也就是L2P對照紀錄的資訊)從閃存裝置150讀取指定LBA的資料。
Step S1143: Drive the
步驟S1145:驅動閃存介面139依據變更後的相應LBA對照紀錄從閃存裝置150讀取指定LBA的資料。
Step S1145 : drive the
步驟S1147:以如上所述多包的格式儲存指定LBA的資料到RAM 136,使得將來在收到CMD18後能夠以多包的格式傳送指定LBA的資料給主機端110。
Step S1147: Store the specified LBA data in the
本發明所述的方法中的全部或部分步驟可以計算機指令實現,例如儲存裝置中的韌體轉換層(Firmware Translation Layer,FTL)、特定硬體的驅動程式等。此外,也可實現於其他類型程式。所屬技術領域具有通常知識者可將本發明實施例的方法撰寫成計算機指令,為求簡潔不再加以描述。依據本發明實施例方法實施的計算機指令可儲存於適當的電腦可讀取媒體,例如DVD、CD-ROM、USB碟、硬碟,亦可置於可通過網路(例如,網際網路,或其他適當載具)存取的網路伺服器。 All or part of the steps in the method of the present invention can be realized by computer instructions, such as a firmware translation layer (Firmware Translation Layer, FTL) in a storage device, a specific hardware driver, and the like. In addition, it can also be implemented in other types of programs. Those skilled in the art can write the methods of the embodiments of the present invention into computer instructions, which will not be described again for the sake of brevity. The computer instructions implemented according to the method of the embodiment of the present invention can be stored in a suitable computer-readable medium, such as DVD, CD-ROM, USB disk, hard disk, and can also be placed through a network (for example, the Internet, or other appropriate means of accessing the web server.
雖然圖1至圖2中包含了以上描述的元件,但不排除在不違反發明的精神下,使用更多其他的附加元件,已達成更佳的技術效果。此外,雖然圖10、圖11的流程圖採用指定的順序來執行,但是在不違反發明精神的情況下,熟習此技藝人士可以在達到相同效果的前提下,修改這些步驟間的順序,所以,本發明並不侷限於僅使用如上所述的順序。此外,熟習此技藝人士亦可以將若干步驟整合為一個步驟,或者是除了這些步驟外,循序或平行地執行更多步驟,本發明亦不因此而侷限。 Although the elements described above are included in FIGS. 1 to 2 , it is not excluded that more additional elements may be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts in FIG. 10 and FIG. 11 are executed in a specified order, those skilled in the art can modify the order of these steps while achieving the same effect without violating the spirit of the invention. Therefore, The invention is not limited to using only the sequence described above. In addition, those skilled in the art may also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereby.
雖然本發明使用以上實施例進行說明,但需要注意的是,這些描述 並非用以限縮本發明。相反地,此發明涵蓋了熟習此技藝人士顯而易見的修改與相似設置。所以,申請權利要求範圍須以最寬廣的方式解釋來包含所有顯而易見的修改與相似設置。 While the invention has been described using the above examples, it should be noted that these descriptions It is not intended to limit the invention. On the contrary, the invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.
611~655:操作 611~655: Operation
Claims (18)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202063052717P | 2020-07-16 | 2020-07-16 | |
US63/052,717 | 2020-07-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202205099A TW202205099A (en) | 2022-02-01 |
TWI795680B true TWI795680B (en) | 2023-03-11 |
Family
ID=79327242
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW109135089A TWI761983B (en) | 2020-07-16 | 2020-10-12 | Method and apparatus for data reads in host performance acceleration mode |
TW111109302A TW202225979A (en) | 2020-07-16 | 2020-10-12 | Method and computer program product and apparatus for executing embedded multi-media controller command |
TW109135109A TWI795680B (en) | 2020-07-16 | 2020-10-12 | Method and apparatus for data reads in host performance acceleration mode |
TW109135126A TWI760884B (en) | 2020-07-16 | 2020-10-12 | Method and apparatus for data reads in host performance acceleration mode |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW109135089A TWI761983B (en) | 2020-07-16 | 2020-10-12 | Method and apparatus for data reads in host performance acceleration mode |
TW111109302A TW202225979A (en) | 2020-07-16 | 2020-10-12 | Method and computer program product and apparatus for executing embedded multi-media controller command |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW109135126A TWI760884B (en) | 2020-07-16 | 2020-10-12 | Method and apparatus for data reads in host performance acceleration mode |
Country Status (2)
Country | Link |
---|---|
CN (3) | CN113946279A (en) |
TW (4) | TWI761983B (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103678145A (en) * | 2012-09-06 | 2014-03-26 | 慧荣科技股份有限公司 | Data storage device and flash memory control method |
US20190235762A1 (en) * | 2018-01-29 | 2019-08-01 | Toshiba Memory Corporation | Memory system controlling nonvolatile memory |
TW202009936A (en) * | 2018-08-30 | 2020-03-01 | 大陸商合肥沛睿微電子股份有限公司 | Flash memory controller and associated accessing method and electronic device |
TWI698874B (en) * | 2018-08-31 | 2020-07-11 | 大陸商合肥沛睿微電子股份有限公司 | Flash memory controller and associated accessing method and electronic device |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7934049B2 (en) * | 2005-09-14 | 2011-04-26 | Sandisk Corporation | Methods used in a secure yet flexible system architecture for secure devices with flash mass storage memory |
US8706968B2 (en) * | 2007-12-06 | 2014-04-22 | Fusion-Io, Inc. | Apparatus, system, and method for redundant write caching |
KR101736337B1 (en) * | 2011-02-28 | 2017-05-30 | 삼성전자주식회사 | Nonvolatile memory device, controller for controlling the same, and operation method thereor |
TWI521343B (en) * | 2011-08-01 | 2016-02-11 | Toshiba Kk | An information processing device, a semiconductor memory device, and a semiconductor memory device |
US9348783B2 (en) * | 2012-04-19 | 2016-05-24 | Lockheed Martin Corporation | Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory |
US9395924B2 (en) * | 2013-01-22 | 2016-07-19 | Seagate Technology Llc | Management of and region selection for writes to non-volatile memory |
US9547447B2 (en) * | 2014-01-03 | 2017-01-17 | Advanced Micro Devices, Inc. | Dedicated interface for coupling flash memory and dynamic random access memory |
JP2017527877A (en) * | 2014-06-25 | 2017-09-21 | 華為技術有限公司Huawei Technologies Co.,Ltd. | Method and apparatus for reading / writing data from / to flash memory and user equipment |
CN105637521B (en) * | 2014-06-30 | 2020-02-14 | 华为技术有限公司 | Data processing method and intelligent terminal |
US10126950B2 (en) * | 2014-12-22 | 2018-11-13 | Intel Corporation | Allocating and configuring persistent memory |
CN104809075B (en) * | 2015-04-20 | 2017-09-12 | 电子科技大学 | A kind of solid state record device and method for accessing real-time parallel processing |
US9940028B2 (en) * | 2015-11-13 | 2018-04-10 | Samsung Electronics Co., Ltd | Multimode storage device |
US10140055B2 (en) * | 2015-12-21 | 2018-11-27 | Memory Technologies Llc | Ensuring that memory device actions are valid using reference values |
TWI629591B (en) * | 2017-08-30 | 2018-07-11 | 慧榮科技股份有限公司 | Method for accessing flash memory module and associated flash memory controller and electronic device |
WO2019209707A1 (en) * | 2018-04-23 | 2019-10-31 | Micron Technology, Inc. | Host logical-to-physical information refresh |
CN110908926B (en) * | 2018-09-14 | 2022-03-22 | 慧荣科技股份有限公司 | Data storage device and writing method of logical-to-physical address mapping table |
-
2020
- 2020-10-12 CN CN202011086743.7A patent/CN113946279A/en active Pending
- 2020-10-12 TW TW109135089A patent/TWI761983B/en active
- 2020-10-12 TW TW111109302A patent/TW202225979A/en unknown
- 2020-10-12 TW TW109135109A patent/TWI795680B/en active
- 2020-10-12 CN CN202011086727.8A patent/CN113946278A/en active Pending
- 2020-10-12 TW TW109135126A patent/TWI760884B/en active
- 2020-10-12 CN CN202011084288.7A patent/CN113946277A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103678145A (en) * | 2012-09-06 | 2014-03-26 | 慧荣科技股份有限公司 | Data storage device and flash memory control method |
US20190235762A1 (en) * | 2018-01-29 | 2019-08-01 | Toshiba Memory Corporation | Memory system controlling nonvolatile memory |
TW202009936A (en) * | 2018-08-30 | 2020-03-01 | 大陸商合肥沛睿微電子股份有限公司 | Flash memory controller and associated accessing method and electronic device |
TWI698874B (en) * | 2018-08-31 | 2020-07-11 | 大陸商合肥沛睿微電子股份有限公司 | Flash memory controller and associated accessing method and electronic device |
Also Published As
Publication number | Publication date |
---|---|
TWI760884B (en) | 2022-04-11 |
CN113946278A (en) | 2022-01-18 |
CN113946279A (en) | 2022-01-18 |
TW202205098A (en) | 2022-02-01 |
TW202225979A (en) | 2022-07-01 |
TW202205099A (en) | 2022-02-01 |
CN113946277A (en) | 2022-01-18 |
TW202205097A (en) | 2022-02-01 |
TWI761983B (en) | 2022-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11636032B2 (en) | Memory system, data storage device, user device and data management method thereof | |
US11429545B2 (en) | Method and apparatus for data reads in host performance acceleration mode | |
US11995003B2 (en) | Method of data caching and device caching data | |
US20160124639A1 (en) | Dynamic storage channel | |
TW202101227A (en) | Apparatus and method and computer program product for handling flash physical-resource sets | |
CN107943710B (en) | Memory management method and memory controller using the same | |
KR102653373B1 (en) | Controller and operation method thereof | |
WO2021035555A1 (en) | Data storage method and apparatus for solid state disk and solid state disk (ssd) | |
KR20120045422A (en) | Memory system and user device, and data management method thereof | |
US11544185B2 (en) | Method and apparatus for data reads in host performance acceleration mode | |
US11544186B2 (en) | Method and apparatus for data reads in host performance acceleration mode | |
CN113641597B (en) | Method and apparatus for managing data storage and computer readable storage medium | |
US12045163B2 (en) | Storage device for classifying data based on stream class number, storage system, and operating method thereof | |
CN115079957B (en) | Request processing method, device, controller, equipment and storage medium | |
TWI795680B (en) | Method and apparatus for data reads in host performance acceleration mode | |
US20230359550A1 (en) | File system integration into data mining model | |
CN110968527A (en) | FTL provided caching | |
TWI835027B (en) | Method and computer program product and apparatus for updating host-to-flash address mapping table | |
KR20220159268A (en) | Host device, storage device and electronic device |