TWI760884B - Method and apparatus for data reads in host performance acceleration mode - Google Patents

Abstract

The invention relates to a method, and an apparatus for data reads in host performance acceleration (HPA) mode. The method is performed by a flash controller to include: searing an HPA buffer of a system memory for a logical-block-address to physical-block-address (L2P) mapping record; issuing a switch command to a flash controller for requesting the flash controller to activate an HPA function but deactivate an L2P-mapping-table acquisition function; issuing a write-multiple-block command to the flash controller for writing a block to the flash controller, which comprises the L2P mapping record; and issuing a read-multiple-block command to the flash controller for obtaining data corresponding to the L2P mapping record from the flash controller.

Description

Data reading method and device in host performance acceleration mode

The present invention relates to a storage device, in particular to a data reading method and device in a host performance acceleration mode.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address for accessing the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in time. material. In contrast, NAND flash memory is not random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data in flash for write operations) or a block (the smallest block of data in flash for erase operations).

In order to improve the data writing and reading performance of the flash memory module, the device side performs data writing and reading in parallel with multiple channels. In order to achieve the purpose of parallel processing, a continuous piece of data will be distributed to the flash memory cells connected to multiple channels, and recorded using the Logical-block-address to Physical-block-address (L2P Mapping Table) The correspondence between the logical address (managed by the host) and the physical address (managed by the flash controller) of the user data. However, in the storage device of the embedded Multi-Media Controller (e˙MMC), with the rapid increase of the device capacity, the length of the logical entity comparison table also grows multiple times, resulting in the traditional management method executed by the device. unaffordable. Even if you use hierarchical subsections to Managing the logical entity mapping table can improve the performance of the logical entity mapping conversion, but the time spent in the logical entity mapping conversion is still significantly higher than the time for transferring data from the flash array of the flash module to the data register of the flash controller (tR ). Therefore, the present invention provides a data reading method and device in a host performance acceleration mode, which are used to improve the data reading performance of a storage device of an embedded multimedia card.

In view of this, how to alleviate or eliminate the above-mentioned deficiencies in related fields is a problem to be solved.

This specification relates to a data reading method in a host performance acceleration mode, which is executed by the host, including: searching the host performance acceleration buffer in the system memory to obtain the logical entity comparison record associated with the logical block address; issuing a switching command To the flash memory controller, it is used to request the flash memory controller to start the host performance acceleration function, but does not start the acquisition function of the logical entity comparison table; issue a write multi-block command to the flash memory controller to write data blocks to the flash memory controller, The data block contains a logical entity comparison record; and a read multiple block command is issued to the flash memory controller for obtaining data corresponding to the logical entity comparison record from the flash memory controller.

This specification relates to a data reading method in a host performance acceleration mode, which is executed by a flash memory controller, including: receiving a switching command from the host side, which is used to request the flash memory controller to activate the host performance acceleration function, but does not activate the acquisition of the logical entity comparison table Function; enter the default state in response to the above switching command; receive a multi-block write command from the host during entering the default state; obtain the logical entity comparison record from the data block received by the host in response to the multi-block write command, and read the data corresponding to the logical entity comparison record from the flash memory device; receive a read multi-block command from the host during entering the default state; and transmit the data corresponding to the logical entity comparison record to the host in response to the read multi-block command end.

The present specification further relates to a device in a host performance acceleration mode, comprising: a host interface; a flash memory interface; and a processing unit. The processing unit receives a switching command from the host through the host interface, which is used to request the device to activate the host performance acceleration function, but does not activate the logical entity pair The acquisition function according to the table; enter the default state in response to the switching command; receive a multi-block write command from the host side through the host interface during entering the default state; in response to the multi-block write command received from the host side through the host interface Obtain the logical entity comparison record from the data block, and read the data corresponding to the logical entity comparison record from the flash memory device through the flash memory interface; during entering the default state, receive a multi-block read command from the host side through the host interface; The fetch multi-block command transmits the data corresponding to the logical entity comparison record to the host through the host interface.

The host side and the flash memory controller communicate with each other using the embedded multimedia card communication protocol, and each logical entity compares the data stored in the logical address with the information actually stored in the physical address.

One of the advantages of the above-mentioned embodiment is that, through the setting of the host performance acceleration buffer as described above, the host side can send a read command with a logical entity comparison record to the flash memory controller, so as to reduce the time and computing resources of the flash memory controller. Perform logical entity comparison transformation.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

10: Electronics

110: Host side

130: Flash Controller

131:Host Interface

132: Busbar

134: Processing unit

135: read-only memory

136: Random Access Memory

137: Scratchpad

139: Flash interface

150: Flash device

151: Interface

153#0~153#15: NAND flash memory unit

CH#0~CH#3: Channel

CE#0~CE#3: Enable signal

310: Advanced comparison table

330#0~330#15: L2P comparison sub-table

400: L2P comparison record

410: Information on the logical block address

430: Information about the physical block address

430-0: Logical unit number and physical block number

430-1: Entity page number

440: Solid Block

450: Entity page

450#2: Physical Section

500:HPA cache

611~655, 711~755, 835~839, 915, 931, 955: Operation

S1010~S1060, S1110~S1147: method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of the association between a high-level comparison table and a logical entity comparison sub-table according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the association between a logical entity comparison sub-table and an entity page according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the establishment and application of a Host Performance Acceleration (HPA) cache according to an embodiment of the present invention.

FIG. 6 is an operation sequence diagram of HPA buffer initialization according to an embodiment of the present invention.

7 and 8 are operational sequence diagrams of HPA reading according to an embodiment of the present invention.

FIG. 9 is an operation sequence diagram of HPA buffer update according to an embodiment of the present invention.

FIG. 10 is a flowchart of a method for executing a handover command according to an embodiment of the present invention.

FIG. 11 is a flowchart of a method for executing a write multi-block command according to an embodiment of the present invention.

The following description is a preferred implementation manner to complete the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. Reference must be made to the scope of the following claims for the actual inventive content.

It must be understood that the words "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, elements and/or components, but do not exclude the possibility of adding More technical features, values, method steps, job processes, elements, components, or any combination of the above.

The use of words such as "first", "second", "third", etc. in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority order, a preceding relationship between them, or an element Prior to another element, or chronological order in which method steps are performed, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements can also be read in a similar fashion, such as "between" versus "directly interposed," or "adjacent" versus "directly adjoining," and the like.

Refer to Figure 1. The electronic device 10 includes a host device (also referred to as a host side) 110 , a flash memory controller 130 and a flash memory device 150 , and the flash memory controller 130 and the flash memory device 150 may be collectively referred to as a device side. The electronic device 10 can be implemented in electronic products such as personal computers, notebook computers (Laptop PCs), tablet computers, mobile phones, digital cameras, and digital video cameras. The host device 110 and the host interface (Host Interface) 131 of the flash controller 130 can communicate with each other through the embedded Multi-Media Controller (e˙MMC/eMMC) protocol. The flash memory interface 139 of the flash memory controller 130 and the flash memory device 150 can be double data rate (Double Data Rate, DDR) protocols communicate with each other, such as Open NAND Flash Interface (ONFI), DDR Toggle, or other protocols. The flash controller 130 includes a processing unit 134, which may be implemented using a variety of ways, such as using general-purpose hardware (eg, a microcontroller, a central processing unit, a multiprocessor with parallel processing capabilities, a graphics processor, or other processing capable of computing). device) and, when executing software and/or firmware instructions, provide the functionality described later. The processing unit 134 receives eMMC commands through the host interface 131 and executes the commands. The flash memory controller 130 includes a random access memory (RAM) 136, which can be implemented as a dynamic random access memory (DRAM), a static random access memory (SRAM) ) or a combination of the above two to configure the space as a data buffer. The random access memory 136 can also store data required in the execution process, such as variables, data tables, and the like. The flash memory controller 130 includes a Read Only Memory (ROM) 135 for storing program codes that need to be executed when booting. The flash memory interface 139 includes a NAND flash controller (NAND Flash Controller, NFC), which provides functions required for accessing the flash memory device 150, such as a command sequencer (Command Sequencer), a low density parity check (Low Density Parity Check, LDPC), etc. .

The flash controller 130 includes a register 137 for storing various parameter values. In the eMMC specification (eg, eMMC Electrical Standard 5.1 published in July 2014), the register 137 includes a 32-bit Operation Condition Register (OCR), a 128-bit device identification register (Device IDentification, CID Register), 128-bit device-specific data register (Device-Specific Data, CSD Register), 512-bit extended device-specific data register (Extended CSD Register, referred to as Ext_CSD) scratchpad), etc. The Ext_CSD register defines the device properties (Device Properties) and the selected mode (Selected Modes). The ability to be set and not modifiable by the host side 110, another less significant 192-bit byte is the Modes Segment, which defines the settings the device is currently running on. The host 110 can change these modes through a switch command (SWITCH command, CMD6). The eMMC specification reserves a number of areas in the Ext CSD register that can be freely used by device manufacturers to complete the function of Host Performance Acceleration (HPA Mode).

A bus architecture 132 can be configured in the flash memory controller 130 to couple elements to each other to transmit data, addresses, control signals, etc. These elements include a host interface 131, a processing unit 134, a ROM 135, RAM 136, scratchpad 137, flash memory interface 139, etc. In some embodiments, the host interface 131, the processing unit 134, the ROM 135, the RAM 136, the register 137, and the flash memory interface 139 may be coupled to each other through a single bus. In other embodiments, a high-speed bus for coupling the processing unit 134 , ROM 135 , RAM 136 and the scratchpad 137 to each other may be configured in the flash controller 130 , and a low-speed bus for allowing the processing unit to be coupled to each other. 134. The host interface 131 and the flash memory interface 139 are coupled to each other. The bus bars contain parallel physical lines that connect more than two components in the flash controller 130 .

The flash memory device 150 provides a large amount of storage space, usually hundreds of gigabytes (Gigabytes, GB), or even several terabytes (Terabytes, TB), for storing a large amount of user data, such as High-resolution pictures, videos, etc. The flash memory device 150 includes a control circuit and a memory array. After erasing, the memory cells in the memory array can be configured as single level cells (Single Level Cells, SLCs), multiple level cells (Multiple Level Cells, MLCs) three Layered cells (Triple Level Cells, TLCs), Quad-Level Cells (Quad-Level Cells, QLCs) or any combination of the above. The processing unit 134 writes the user data to the specified address (destination address) in the flash memory device 150 through the flash memory interface 139, and reads the user data and L2P comparison from the specified address (source address) in the flash memory device 150 specified section in the table. The flash interface 139 uses several electronic signals to coordinate between the flash controller 130 and the flash device 150 data and command transmission, including data line (Data Line), clock signal (Clock Signal) and control signal (Control Signal). Data lines can be used to transmit commands, addresses, read and written data; control signal lines can be used to transmit Chip Enable (CE), Address Latch Enable (ALE), Command Extraction Enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to FIG. 2 , the interface 151 in the flash memory device 150 may include four I/O channels (hereinafter referred to as channels) CH#0 to CH#3, each of which is connected to four NAND flash memory cells, for example, channel CH #0 connects NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent die. The flash memory interface 139 can enable the NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11 by issuing one of the enable signals CE#0 to CE#3 through the interface 151 , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory cells in parallel, or write user data to the enabled NAND flash memory cells.

Since data of a continuous segment (that is, a segment of consecutive logical block addresses, LBAs) is distributed and stored in the NAND flash memory cells connected to multiple channels, the flash memory controller 130 uses a logical entity comparison table (Logical Entity Comparison Table). -block-address to Physical-block-address, L2P Mapping Table) records the correspondence between the logical address (managed by the host device 110 ) and the physical address (managed by the flash controller 130 ) of the user data. The L2P comparison table includes a plurality of records, and stores the information of which physical address the user data of each logical address is actually stored in according to the order of the logical addresses. The data of a continuous LBA can be divided into several regions (Regions), which are identified by region numbers, and each region can be further divided into several sub-regions (Sub-regions), which are identified by sub-region numbers. For example, 128GB of data addressed using LBA can be divided into 16 8GB regions, and each 8GB region can be further divided into 256 32MB sub-regions. In the eMMC specification, each LBA is associated with (or points to) a 512-byte (Bytes) material. However, since the RAM 136 cannot provide enough space to store the entire L2P lookup table for the processing unit 134 to quickly look up the data read operation in the future, the entire L2P lookup table can be divided into multiple sub-tables according to the division of regions and sub-regions, and stored separately The different physical addresses of the non-volatile flash memory device 150 make it possible to read the corresponding sub-table from the flash memory device 150 to the RAM 136 in the future data read operation. Referring to Figure 3, the entire L2P comparison table can be divided into sub-tables 330#0~330#15. The processing unit 134 further maintains a high-level mapping table (High-level Mapping Table) 310, which includes a plurality of records, and stores the physical address information of the sub-tables associated with each LBA segment in the order of logical addresses. For example, the association sub-table 330#0 of the 0th to 4095th LBAs is stored in a specific physical block of a specific Logical Unit Number (LUN) (the letter "Z" can represent the number of the LUN and the physical block). The 0th entity page, the associated subtable 330#1 of the 4096th to 8191st LBAs are stored in the 1st entity page in a specific entity block of a specific LUN, and so on. Although only 16 sub-tables are included in FIG. 3 , those skilled in the art can set more sub-tables according to the capacity of the flash memory device 150 , and the present invention is not limited thereto.

In order to match the physical configuration of the flash memory device 150, the flash memory controller 130 can make a physical block address (Physical Block Address, PBA) associated with (or pointing to) 4KB, 8KB or 16KB of data, which is longer than an LBA in the eMMC specification The length of the associated profile (512B). Because the lengths of data associated with LBA and PBA are inconsistent, each record in each sub-table contains logical address and physical address information for precisely specifying the address in the flash memory device 150 . Referring to FIG. 4 , the sub-table 330#0 stores addressing information from LBA#0 to LBA#4095 in sequence. Addressing information can be represented in eight bytes: four bytes represent LBA; the other four bytes represent PBA. For example, record 400 in sub-table 330#0 associated with LBA#2 stores LBA 410 and PBA 430 information. The two bytes 430-0 in the PBA 430 record the logical unit number and the physical block number; the other two bytes 430-1 record the physical page number. Therefore, the physical address information 400 corresponding to LBA #2 can point to a specific section in the physical page 450 of the physical block 440 (Sector)450#2.

In order to solve the problem that the flash controller 130 spends too much time on the logical entity comparison conversion, the embodiment of the present invention adds a new function of HPA based on the Host-Device Communications Architecture of the current eMMC specification. HPA allows the logical entities that were originally implemented by the flash controller 130 to take a lot of time to compare the workload to be converted to the host side 110, which can improve the random read performance of short-length data, which can refer to lengths from 512B to 32KB data of. Referring to FIG. 5 , the host 110 allocates space in its system memory as the HPA cache 500 for temporarily storing the information of the L2P comparison table maintained and managed by the device. The HPA cache 500 stores a plurality of L2P mapping records (L2P Mapping Records) received from the device, and each L2P mapping record record corresponds to the addressing information of one LBA. Next, the host 110 may issue a command carrying the L2P comparison record to the device for obtaining the user data of the designated LBA. The flash memory controller 130 can directly drive the flash memory interface 139 to read the user data of the specified LBA from the flash memory device 150 according to the information in the L2P comparison record, instead of spending time and computing resources to read the corresponding LBA from the flash memory device 150 as before. The user data of the specified LBA can be read from the flash memory device 150 only after the sub-table is converted and the logical physical address is converted. The establishment and application of HPA cache 500 can be divided into three stages:

Phase I (HPA initialization): The host side 110 reads the value of the register 137 in the flash controller 130, and checks whether the eMMC storage device (or the device side, including at least the flash controller 130 and the flash device 150) supports the HPA function. If so, the host 110 allocates space in the system memory as the HPA L2P comparison table area.

Phase II (HPA table management): If the eMMC storage device supports the HPA function, the host 110 issues a series of commands for requesting the flash controller 130 to read the L2P table. In response to the series of commands, the flash controller 130 transmits all or part of the L2P comparison table to the host 110, so that the host 110 stores the obtained comparison table in the HPA L2P comparison table area (this can be called mirror L2P comparison. Table, Mirrored L2P Mapping Table). When the actual L2P lookup table corresponding to the mirrored L2P lookup table is changed due to procedures such as data writing, data trimming (Data Trimming), garbage collection (GC), wear leveling (Wear Leveling), etc., the flash controller 130 notifies On the host side 110, all or the corresponding part of the L2P comparison table in the system memory of the host side 110 needs to be updated.

Phase III (HPA read): The host 110 issues a series of commands with L2P comparison records to the eMMC storage device to request to obtain the data of a specific LBA (especially the discontinuous data of small block length, such as the discontinuous data of 512B to 32KB data), in which the L2P comparison record is searched from the mirror L2P comparison table. Next, the flash controller 130 reads the data of the specified LBA from the PBA of the flash device 150 according to the content of the L2P comparison record, and replies the read data to the host 110 , so that the eMMC storage device can save reading for the logical entity comparison conversion. Time to fetch and search the L2P lookup table.

In the eMMC specification, Ext_CSD[160] (also referred to as PARTITIONING_SUPPORT[160]) defines Supported Partition Features, and Bits[7:3] are reserved for manufacturers of eMMC storage devices for free use. The third bit (Ext_CSD[160], Bit[3]) of the 160th byte of the Ext_CSD register can be used to define whether the eMMC storage device supports the HPA function. is set to "0". During the initialization process of the eMMC storage device, the processing unit 134 may set Ext_CSD[160], Bit[3] in the register 137 to "1". Although the embodiments of the present invention describe the technical solution of using Ext_CSD[160], Bit[3] to define whether the eMMC storage device supports the HPA function, those skilled in the art can change the design to use other reserved bits in the Ext_CSD register, such as Ext_CSD[511:506], Ext_CSD[485:309], Ext_CSD[306], Ext_CSD[233], Ext_CSD[227], Ext_CSD[204], Ext_CSD[195], Ext_CSD[193], Ext_CSD[190], Ext_CSD [188], Ext_CSD[186], Ext_CSD[184], Ext_CSD[182], Ext_CSD[180], Ext_CSD[176], Ext_CSD[172], Ext_CSD[170], Ext_CSD[135], Ext_CSD[129:128] , Ext_CSD[127:64], Ext_CSD[28:27], Ext_CSD[14:0], etc., the present invention is not limited thereby.

In addition, the flash controller 130 can use the paired Ext_CSD registers to record the information of the designated area and sub-area that need to be updated in the L2P comparison table cached by the host 110 . For example, the 64th byte (Ext_CSD[64]) and the 66th byte (Ext_CSD[66]) of the Ext_CSD register are a pair to indicate the 0th region (Region#0) and The 160th subregion (SubRegion#160). The 65th byte (Ext_CSD[65]) and the 67th byte (Ext_CSD[67]) of the Ext_CSD register are another pair for indicating the 0th region (Region#0) and the 18 subregions (SubRegion #18).

In the eMMC specification, the switch command (CMD6) is issued by the host 110 to switch the operation mode of the selected device or modify the value of the Ext_CSD register, and the 26th to 31st bits of the parameter (Bits[31:26] ) are reserved bits. The host 110 can set the 26th bit of CMD6 (CMD6, Bit[26]) to indicate whether to enable the HPA function. Although the embodiments of the present invention describe the technical solution of defining whether to enable the HPA function by CMD6, Bit[26], those skilled in the art can change the design to use other reserved bits in the parameters of CMD6, and the present invention is not limited thereby. The host 110 can set the 27th bit of CMD6 (CMD6, Bit[27]) to indicate whether to enable the acquisition function of the L2P comparison table. Although the embodiment of the present invention describes the technical solution of defining whether to enable the acquisition function of the L2P lookup table with CMD6, Bit[27], those skilled in the art can change the design to use other reserved bits in the parameters of CMD6, the present invention does not Therefore limited.

In the eMMC specification, the set block number command (CMD23) is issued by the host terminal 110 to indicate the block number of the subsequent packed write command, or the block number of the header (Header) of the subsequent packed read command. When CMD23 is associated with the following packed write command, the 30th bit (Bit[30]) in the parameter is set to "0b1", and the 0th to 15th bits in the parameter of CMD23 (Bits[15] :0]) is used to indicate the number of blocks. When CMD23 is associated with the following packed write command or packed read command, the 30th bit in the parameter (Bit[30]) is set to "0b1". The 0th to 15th bits (Bits[15:0]) in the parameters of CMD23 are used to indicate the number of blocks.

In the eMMC specification, the write multi-block command (CMD25) is issued by the host 110 to continuously write data blocks to the eMMC storage device until a stop transfer command (STOP_TRANSMISSION Command, CMD12) is issued, or the requested number of data blocks has been written. The host 110 can transmit the information of the specified area and sub-area in the L2P comparison table through CMD23 and CMD25, and request the flash controller 130 to prepare the L2P comparison record of the specified area and sub-area. In addition, the host 110 can transmit the L2P comparison record through CMD23 and CMD25, and request the flash controller 130 to prepare data for future reading. The 0th to 31st bits (Bits[31:0]) in the parameter of CMD25 represent the data address.

In the eMMC specification, the read multi-block command (CMD18) is issued by the host 110 to continuously read data blocks from the eMMC storage device until the requested number of data blocks have been read, or a stop command (Stop Command )interrupt. That is, the CMD 18 requests the eMMC storage device to transmit the previously indicated number of data blocks to the host 110 . The 0th to 31st bits (Bits[31:0]) in the parameter of CMD18 represent the data address. The host 110 can request the flash controller 130 to transfer the L2P comparison record of the specified area and sub-area (defined in the previous CMD25) through CMD23 and CMD18. Referring to the example shown in FIG. 4 , the length of each L2P comparison record is 8B, so that each data block can carry at most 32 L2P comparison records. In addition, the host 110 can request the flash controller 130 to transmit data corresponding to the L2P comparison record (defined in the previous CMD25) through CMD23 and CMD18.

In the eMMC specification, a normal response command (R1) is issued by the flash controller 130 to inform the host 110 of a specific message. The length of R1 is 48 bits, in which the 40th to 45th bits (Bits[45:40]) record the index of the command to be replied, and the 8th to 39th bits (Bits[39:8]) record the device Device Status. When the 31st bit (Bit[31]) of R1 is set to "0b1", it means that the address is over over range (ADDRESS_OUT_OF_RANGE). When the 30th bit (Bit[30]) of R1 is set to "0b1", it means that the address is not suitable (ADDRESS_MISALIGN). When the HPA function is activated but the acquisition function of the L2P comparison table is not activated, if some of the PBAs in the L2P comparison record carried in the CMD25 are invalid, the flash controller 130 can use the 31st bit of R1 of the CMD18 for replying (Bit[31]) and the 30th bit (Bit[30]) are both set to "0b1", which are used to indicate that the L2P comparison record cached in the host 110 needs to be updated.

For the establishment of the HPA L2P table area (also called the HPA buffer) in Phase I and Phase II, after the eMMC storage device is initialized, the host 110 reads the L2P table from the device for the first time, and stores it in the HPA buffer Area. Table 1 describes example command sequence details for initializing HPA buffers:

Referring to the operation sequence diagram of HPA buffer initialization shown in FIG. 6 , the detailed description is as follows: Operation 611 : the host 110 sends a command to the flash controller 130 for requesting the flash controller 130 to obtain the value of the Ext_CSD register.

Operation 613 : In response to the register read command received through the host interface 131 , the processing unit 134 obtains the value of the Ext_CSD register in the register 137 and replies to the host 110 through the host interface 131 .

Operation 615: The host 110 may check the value of the Ext_CSD register (eg, Ext_CSD[160], Bit[3]) to determine whether the eMMC storage device supports the HPA function. If so, the process of operation 617 continues. If not, the HPA function is not activated.

Operation 617: The host 110 issues a switch command (CMD6) to the flash controller 130 to start the HPA function and the L2P look-up table acquisition function. For example, referring to the second row of Table 1, the host 110 can set the parameter of CMD6 to "0x0C000000", that is, including Bit[26]="0b1" and Bit[27]="0b1", to indicate the flash control The controller 130 enables these two functions.

Operation 619 : After the flash controller 130 receives the switching command as shown above, it enters the HPA mapping table read state (HPA_Mapping_READ state) for preparing to transmit a part of the L2P mapping table to the host 110 .

Operation 631: The host 110 allocates space in the system memory to the HPA buffer, and Determine the L2P comparison record of the area and sub-area to be obtained from the eMMC storage device according to the needs of the operating system, driver, application, etc.

Operation 633 : The host 110 issues a set block number command ( CMD23 ) to the flash memory controller 130 for informing the flash memory controller 130 of how many data blocks to transfer. For example, referring to the third row of Table 1, the host 110 can set the parameter of CMD23 to "0x40000001", that is, to include Bit[30]="0b1" and Bits[15:0]="0x0001", indicating that the Write a block of data to the flash controller 130 . Next, the host terminal 110 issues a write multi-block command (CMD25) to the flash memory controller 130 for continuously writing data blocks to the flash memory controller 130 until the requested number of data blocks have been written. For example, referring to the fourth row of Table 1, the host 110 may set the parameter of CMD25 to "0x01E2A3E0", which represents a specific data address. Each data block can be divided into 32 packets (Packets), and the length of each packet is 16B. 2 bytes in each packet can indicate the number of a specific area, and the remaining 14 bytes can indicate the number of several specific sub-areas. For example, when a package contains the information of {Region#0,SubRegion#0,SubRegion#1,SubRegion#2,SubRegion#3}, it means that the specified part of the L2P comparison table is associated with the 0th to 0th in the 0th region 3rd sub-area. Next, the host side 110 sends a set block number command (CMD23) to the flash memory controller 130 for informing the flash memory controller 130 of how many data blocks to receive. For example, referring to the fifth row of Table 1, the host 110 can set the parameter of CMD23 to "0x40000020", that is, to include Bit[30]="0b1" and Bits[15:0]="0x0020", indicating that the 32 data blocks are read from the flash controller 130, that is, a maximum of 1024 L2P comparison records. Next, the host terminal 110 issues a multi-block read command (CMD18) to the flash memory controller 130 for continuously reading data blocks from the flash memory controller 130 until the requested number of data blocks have been read. For example, referring to the sixth row of Table 1, the host 110 may set the parameter of CMD18 to "0x01E2A3E0", which represents a specific data address.

Operation 635: Since the HPA lookup table read state has been entered, when the flash controller 130 receives the data block corresponding to CMD25 from the host side 110, it knows that each packet in it carries the information of the specified part of the L2P lookup table, and can be read from the flash memory device 150 accordingly The requested L2P comparison record. In addition, when the flash controller 130 receives the CMD 18 from the host 110 , it knows that it can start to transmit the specified part of the L2P comparison record to the host 110 . Since the parameters of CMD18 are set to be the same as those of CMD25, the data transmitted by the flash controller 130 is an L2P comparison record of a specified portion read from the flash device 150 according to the content of the data block previously written by CMD25.

Operation 651: The flash controller 130 organizes the requested L2P collation record into a plurality of packets in a specified number of data blocks.

Operation 653: The flash controller 130 continues to transmit the organized data blocks to the host 110 until the specified number of data blocks are transmitted. Next, when receiving the packet read complete message from the host 110, it leaves the HPA lookup table read state and enters the transfer state (Transfer State) of the eMMC specification.

Operation 655: The host 110 receives the L2P comparison record carried in each packet and stores it in the HPA buffer. After storing the L2P comparison record carried in the last packet, the host 110 sends a send status command (SEND_STATUS command, CMD13) to the flash controller 130, which includes a packet read complete message.

For Phase III data reading, Table 2 describes example command sequence details for reading data using the HPA function:

Referring to the operation sequence diagram of HPA read as shown in Figure 7, the detailed description is as follows:

Operation 711: The host 110 finds that random reading of short-length data is about to be performed.

Operation 713: The host 110 issues a switch command (CMD6) to the flash controller 130 to enable the HPA function. For example, referring to the second row of Table 2, the host 110 can set the parameter of CMD6 to "0x04000000", that is, including Bit[26]="0b1" and Bit[27]="0b0", to indicate the flash control The controller 130 only enables the HPA function.

Operation 715: After the flash controller 130 receives the switching command as shown above, it enters the HPA read state (HPA_READ state).

Operation 731: The host 110 searches the mirrored L2P comparison table in the HPA buffer to obtain L2P comparison records corresponding to multiple LBAs.

Operation 733 : The host 110 issues a set block number command ( CMD23 ) to the flash controller 130 for informing the flash controller 130 of how many data blocks to transfer. For example, referring to the third row of Table 2, the host 110 can set the parameter of CMD23 to "0x40000001", and also It includes Bit[30]=”0b1” and Bits[15:0]=”0x0001”, which means that a data block will be written to the flash controller 130 later. Next, the host terminal 110 issues a write multi-block command (CMD25) to the flash memory controller 130 for continuously writing data blocks to the flash memory controller 130 until the requested number of data blocks have been written. For example, referring to the fourth row of Table 2, the host 110 may set the parameter of CMD25 to "0x01521182", which represents a specific data address. Each data block can be divided into 32 packets (Packets), and the length of each packet is 16B. Each packet is associated with a pair of LBA and PBA information, of which 8 bytes can specify a specific LBA, and the remaining 8 bytes can specify a specific PBA. Next, the host side 110 sends a set block number command (CMD23) to the flash memory controller 130 for informing the flash memory controller 130 of how many data blocks to receive. For example, referring to the fifth row of Table 2, the host 110 can set the parameter of CMD23 to "0x40000020", that is, to include Bit[30]="0b1" and Bits[15:0]="0x0020", indicating that the 32 data blocks are read from the flash controller 130, that is, data of a maximum of 1024 LBAs. Next, the host terminal 110 issues a multi-block read command (CMD18) to the flash memory controller 130 for continuously reading data blocks from the flash memory controller 130 until the requested number of data blocks have been read. For example, referring to the sixth row of Table 2, the host 110 may set the parameter of CMD18 to "0x01521182", which represents a specific data address.

Operation 735: Since the HPA read state has been entered, when the flash controller 130 receives the data block corresponding to CMD25 from the host side 110, it knows that each packet in it carries the paired LBA and PBA read for one data block. information, and the requested data can be read from the flash memory device 150 accordingly. In addition, when the flash controller 130 receives the CMD 18 from the host 110 , it knows that it can start to transmit the specified data to the host 110 . Since the parameters of CMD18 are set to be the same as those of CMD25, the data transmitted by the flash controller 130 is the data of the specified LBA read from the flash device 150 according to the content of the data block previously written by the CMD25.

Operation 751: The flash controller 130 organizes the requested data into multiple packets in a specified number of data blocks.

Operation 753: The flash controller 130 continues to transmit the organized data blocks to the host 110 until the specified number of data blocks are transmitted. Next, when the packet read complete message is received from the host 110, it leaves the HPA read state and enters the eMMC specification transmission state.

Operation 755: The host 110 receives the data carried in each packet and stores the data in the data buffer of the system memory. After storing the data carried in the last packet, the host 110 sends a transfer status command ( CMD13 ) to the flash controller 130 , which includes a packet read complete message.

Regarding the update of the HPA buffer in Phase II, the host 110 may request the flash controller 130 to perform operations such as data writing, data trims, and block erases during the operation of the device. On the other hand, the flash controller 130 may actively execute procedures such as garbage collection (GC), wear leveling (WL), etc., resulting in part of the content of the L2P comparison table being changed. Therefore, the content in the HPA buffer (that is, the mirrored L2P comparison table) needs to be updated according to the changed content of the L2P comparison table. Referring to the operation sequence diagram of HPA reading as shown in FIG. 8 , the technical solutions of operations 711 to 733 and operations 751 to 753 are the same as those of FIG. 7 , and the remaining operations are described in detail as follows:

Operation 835: Since the HPA read state has been entered, when the flash controller 130 receives the data block corresponding to CMD25 from the host side 110, it knows that each packet in it carries the paired LBA and PBA read for one data block. information, and check whether the LBA comparison record of the LBA data to be read has been changed (that is, whether it is invalid). If so, the flash controller 130 ignores the information carried in the data block, and instead reads the data from the flash device 150 according to the corresponding LBA comparison record after the change. When the flash controller 130 receives the CMD 18 from the host 110 , it knows that it can start to transmit the specified data to the host 110 . Since the parameters of CMD18 are set to be the same as those of CMD25, the data transmitted by the flash memory controller 130 is read from the flash memory device 150 according to the content in the data block written in the previous CMD25 or according to the content in the corresponding LBA comparison record after the change take designation Information on LBA. In addition, when the L2P comparison record of the LBA data to be read is invalid, the flash controller 130 sets the relevant Ext_CSD register to store the information of the area and sub-area to be updated in the HPA buffer of the host 110 .

Operation 837: The flash controller 130 issues an R1 for replying to the CMD18, in which the 31st bit (Bit[31]) and the 30th bit (Bit[30]) are both set to "0b1" to indicate that The mirrored L2P comparison table in the host 110 needs to be updated.

After the host side 110 receives the message that the mirror L2P comparison table needs to be updated from the device side, the host side 110 obtains the information of the area and sub-area to be updated from the device side, and reads the specified part of the L2P comparison table from the device side accordingly. The L2P compares the record and updates the corresponding content in the HPA buffer. Table 3 describes example command sequence details for updating HPA buffers:

Referring to the operation sequence diagram of HPA buffer update shown in FIG. 9 , the technical solutions of operations 611 , 613 , 617 , 619 , 633 , 635 , 651 and 653 are the same as those of FIG. 6 , and the remaining operations are described in detail as follows:

Operation 915: The host 110 obtains the information of the region and sub-region to be updated from the value of the Ext_CSD register (eg, Ext_CSD[67:64]).

Operation 931 : The host 110 determines, according to the information obtained from the flash controller 130 , the L2P comparison record of the region and sub-region to be obtained from the eMMC storage device.

Operation 955: The host 110 receives the L2P comparison record carried in each packet, and updates the corresponding partial content in the HPA buffer. After updating the L2P comparison record carried in the last packet, the host 110 sends a CMD13 to the flash controller 130, which contains a packet read complete message.

For details about the execution of CMD6 in the command processing operations 619 and 715, please refer to the method flowchart shown in FIG. 10. This method is implemented by the processing unit 134 when the relevant software or firmware code is loaded and executed, which is further described as follows:

Step S1010 : Receive a switching command ( CMD6 ) from the host terminal 110 through the host interface 131 .

Step S1020: Determine whether the reserved bits of the CMD6 include information for enabling the HPA function and the acquisition function of the L2P comparison table. If so, the flow continues with the process of step S1030. Otherwise, the flow continues with the processing of step S1040.

Step S1030 : the information of entering the HPA comparison table read state is stored in the RAM 136 , which can be used as a basis for judging the current device state when the CMD 25 is subsequently received.

Step S1040: Determine whether the reserved bits of the CMD6 include information for enabling the HPA function. If so, the flow continues with the processing of step S1050. Otherwise, the flow continues with the processing of step S1060.

Step S1050 : storing the information of entering the HPA read state in the RAM 136 , which can be used as a basis for judging the current device state when the CMD 25 is subsequently received.

Step S1060: Execute a conventional handover procedure. For example, switch the operation mode of the device side, modify the value of the Ext_CSD register, and so on.

For the execution details of CMD25 in the command processing operations 635, 735 and 835, please refer to the method flow chart shown in FIG. 11. This method is implemented by the processing unit 134 when the relevant software or firmware code is loaded and executed, which is further explained as follows :

Step S1110 : Receive a write multi-block command (CMD25 ) and the following data blocks from the host terminal 110 through the host interface 131 .

Step S1121: According to the information stored in the RAM 136, determine whether to enter the HPA lookup table read state or the HPA read state. If yes, the flow proceeds to further judgment in step S1131. Otherwise, the flow proceeds to the processing of step S1123.

Step S1123 : Execute a conventional Packed Write Procedure for driving the flash memory interface 139 to write multiple packets of data to the flash memory device 150 .

Step S1131: According to the information stored in the RAM 136, determine whether to enter the HPA look-up table reading state. If so, the flow continues with the processing of step S1133. Otherwise (that is, entering the HPA reading state), the flow continues to the judgment of step S1141.

Step S1133 : The drive flash interface 139 reads the L2P comparison record of the specified part in the L2P comparison table from the flash memory device 150 according to the information carried in the data block (that is, the information of the specific area and the specific sub-area).

Step S1135: Store the L2P comparison record in the multi-packet format as described above in the RAM 136, so that the L2P comparison record can be transmitted to the host in the multi-packet format in the future after receiving the CMD18. Machine end 110.

Step S1141: Determine whether the LBA comparison record associated with the LBA data to be read has been changed. If so, the flow continues with the processing of step S1145. Otherwise, the flow proceeds to the processing of step S1143.

Step S1143: The drive flash interface 139 reads the data of the specified LBA from the flash memory device 150 according to the information carried in the data block (that is, the information of the L2P comparison record).

Step S1145 : The drive flash interface 139 reads the data of the specified LBA from the flash device 150 according to the corresponding LBA comparison record after the change.

Step S1147 : Store the data of the designated LBA in the RAM 136 in the multi-packet format as described above, so that the data of the designated LBA can be transmitted to the host 110 in the multi-packet format in the future after receiving the CMD 18 .

All or part of the steps in the method of the present invention can be implemented by computer instructions, such as a firmware translation layer (Firmware Translation Layer, FTL) in a storage device, a driver of a specific hardware, and the like. In addition, it can also be implemented in other types of programs. Those skilled in the art can compose the methods of the embodiments of the present invention into computer instructions, which will not be described for brevity. Computer instructions for implementing methods according to embodiments of the present invention may be stored in a suitable computer-readable medium, such as DVD, CD-ROM, USB disk, hard disk, or may be other suitable vehicles) to access the web server.

Although the above-described elements are included in FIGS. 1 to 2 , it is not excluded that more other additional elements may be used to achieve better technical effects without departing from the spirit of the invention. In addition, although the flowcharts of Figure 10 and Figure 11 are executed in the specified order, those skilled in the art can modify the order of these steps under the premise of achieving the same effect without violating the spirit of the invention. Therefore, The present invention is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the scope of the appended claims is to be construed in the broadest manner so as to encompass all obvious modifications and similar arrangements.

711~755: Operation

Claims (16)

A data reading method in a host performance acceleration mode, executed by a host, comprising: searching a host performance acceleration buffer in a system memory to obtain a first logical entity comparison record associated with a logical block address issue a first switching command to a flash memory controller, for requesting the above-mentioned flash memory controller to start a host performance acceleration function, but not to start a function of obtaining a logical entity comparison table, wherein, the above-mentioned host side and the above-mentioned flash memory controller pass through The communication protocols of the embedded multimedia cards communicate with each other; a first write multi-block command is sent to the above-mentioned flash memory controller for writing a first data block to a flash memory controller, and the above-mentioned first data block includes the above-mentioned first logical entity a comparison record, wherein the first logical entity comparison record stores data of a logical address and actually stores information of a physical address in a flash memory device; and sends a first read multi-block command to the flash memory controller, It is used for acquiring data corresponding to the comparison record of the first logical entity from the flash memory controller. The method for reading data in a host performance acceleration mode according to claim 1, wherein the first logical entity comparison record includes a logical block address and a physical block address, and the logical block address is associated with a For the data of the first length, the physical block address is associated with the data of a second length, and the second length is greater than the first length. The data reading method in the host performance acceleration mode according to claim 2, wherein the first length is 512 bytes. The method for reading data in a host performance acceleration mode according to claim 1, comprising: receiving a normal reply command corresponding to the first read multi-block command from the flash memory controller, indicating that the data in the host performance acceleration buffer Content needs to be updated; After receiving the above-mentioned normal reply command, obtain the information of the part to be updated in the above-mentioned host performance acceleration buffer from the above-mentioned flash memory controller; issue a second switching command to the above-mentioned flash memory controller, for requesting the above-mentioned flash memory controller to start the above-mentioned host The performance acceleration function and the acquisition function of the above-mentioned logical entity comparison table; a second write multi-block command is issued to the above-mentioned flash memory controller for writing a second data block to the above-mentioned flash memory controller, and the above-mentioned second data block contains the required An area number and a sub-area number of the update part; a second read multi-block command is issued to the above-mentioned flash memory controller, for obtaining from the above-mentioned flash memory controller a plurality of second numbers corresponding to the above-mentioned area number and the above-mentioned sub-area number a logical entity comparison record; and updating the corresponding part of the content in the host performance acceleration buffer to the second logical entity comparison record. A data reading method in a host performance acceleration mode, executed by a flash memory controller, comprising: receiving a switching command from a host side for requesting the flash memory controller to activate a host performance acceleration function, but not to activate a logical entity comparison The acquisition function of the table, wherein, the host side and the flash memory controller communicate with each other through the embedded multimedia card communication protocol; enter a state in response to the above-mentioned switching command; during entering the above state, a write-in multi-block is received from the host side command; obtain a logical entity comparison record from a data block received by the host in response to the above-mentioned write multi-block command, and read data corresponding to the above-mentioned logical entity comparison record from a flash memory device, wherein the above-mentioned logical entity comparison recording data stored at a logical address and actually storing information of a physical address in the flash memory device; receiving a read multi-block command from the host during entering the state; and transmitting in response to the read multi-block command The data corresponding to the above-mentioned logical entity comparison record is given to The above host side. The method for reading data in a host performance acceleration mode according to claim 5, wherein a first reserved bit in the switching command includes information for enabling the host performance acceleration function, and a second reserved bit in the switching command The bit contains information to disable the acquisition function of the above-mentioned logical entity lookup table. The method for reading data in a host performance acceleration mode according to claim 5, comprising: when it is detected that the logical entity comparison record is invalid, sending a normal reply command corresponding to the command to read multiple blocks, indicating a system memory The contents of a host performance acceleration buffer in need to be updated. The data reading method in the host performance acceleration mode according to claim 5, wherein the write multi-block command is used to allow the host to continuously write data blocks to the flash memory controller until a preset number of data blocks have been Writing is complete. The method for reading data in a host performance acceleration mode according to claim 5, wherein the read multi-block command is used to allow the host to continuously read data blocks from the flash memory controller until a preset number of data blocks have been Finished reading. A device for reading data in a host performance acceleration mode, comprising: a host interface, coupled to a host; a flash memory interface, coupled to a flash memory device; and a processing unit, coupled to the host interface and the flash memory interface, through The above-mentioned host interface receives a switching command from a host terminal, which is used to request the above-mentioned device to start a host performance acceleration function, but does not start a function of obtaining a logical entity comparison table, wherein the above-mentioned host terminal and the above-mentioned device communicate through an embedded multimedia card agreement to communicate with each other; Entering a state in response to the above switching command; during entering the above state, a write multi-block command is received from the host side through the host interface; a multi-block write command is received from the host side through the host interface in response to the write multi-block command. A logical entity comparison record is obtained from the data block, and data corresponding to the logical entity comparison record is read from the flash memory device through the flash memory interface, wherein the logical entity comparison record stores the data of a logical address actually stored in the flash memory information of a physical address in the device; receiving a read multi-block command from the host side through the host interface during entering the state; and transmitting the logical entity corresponding to the logical entity through the host interface in response to the read multi-block command Compare the recorded data to the above host. The device for reading data in a host performance acceleration mode as claimed in claim 10, wherein a first reserved bit in the switching command includes information for enabling the host performance acceleration function, and a second reserved bit in the switching command The reserved bits contain information to disable the acquisition function of the above-mentioned logical entity mapping table. The device for reading data in a host performance acceleration mode according to claim 10, wherein the logical entity comparison record includes a logical block address and a physical block address, and the logical block address is associated with a first A length of data, the physical block address is associated with a second length of data, and the second length is greater than the first length. The device for reading data in a host performance acceleration mode according to claim 12, wherein the first length is 512 bytes. The device for reading data in a host performance acceleration mode according to claim 10, wherein when the processing unit detects that the logical entity comparison record is invalid, the processing unit sends a normal data corresponding to the multi-block read command through the host interface. Reply to the command, indicating a series of The contents of a host performance acceleration buffer in the system memory needs to be updated. The device for reading data in a host performance acceleration mode according to claim 10, wherein the write multi-block command is used to allow the host to continuously write data blocks to the device until a preset number of data blocks have been written Finished entering. The device for reading data in a host performance acceleration mode according to claim 10, wherein the read multi-block command is used to allow the host to continuously read data blocks from the device until a preset number of data blocks have been read Take it.

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