TWI756854B - Method and apparatus and computer program product for managing data storage - Google Patents

Abstract

The invention relates to a method, an apparatus and a computer program product for managing data storage. The method is performed by a flash controller to include: obtaining information indicating a sub-region to be activated, which is associated with a logical block address (LBA) range; triggering a garbage collection (GC) process in background for migrating user data of the whole or a portion of the LBA range to continuous physical addresses of a flash device; and updating the content of a plurality of entries of the sub-region according to the migration results, where each entry includes information indicating a physical address of the flash device user data of an LBA is physically stored. By the triggering of the GC process, it allows an execution of a subsequent read command to read data from the flash device according to the content of the updated entries directly, without the need to spend extra time and computing resources to read a T1 table from the flash device and perform a logical-to-physical address translation.

Description

Method and apparatus for managing data storage and computer program product

The present invention relates to a storage device, in particular to a method and device for managing data storage and a computer program product.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address for accessing the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in time. material. In contrast, NAND flash memory is not random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data in flash for write operations) or a block (the smallest block of data in flash for erase operations).

In order to improve the data writing and reading performance of the flash memory device, the device side performs data writing and reading through multiple channels in parallel. In order to achieve the purpose of parallel processing, a continuous piece of data will be distributed to the flash memory cells connected to multiple channels, and a logical-to-physical (L2P Mapping Table) will be used to record the logical bits of user data. The correspondence between addresses (managed by the host side) and physical addresses (managed by the flash controller). Furthermore, in the new specification, the flash memory controller can organize the corresponding relationship between the logical address and the physical address into the format of the Host Performance Booster (HPB Entries) and provide it to the host side. After that, the host can take out the required physical address from the HPB project, and carry the physical address In the HPB read command sent to the device, the flash controller can directly read the user data from the physical address of the flash device and reply to the host, without the need to spend time and computing resources from the flash device as before. Read the logical entity comparison table and perform logical entity address conversion.

In addition, in the new specification, the host side can send an HPB read command to the flash controller to read the user data of two or more consecutive logical addresses, but only one HPB item is allowed, and its associated Starting logical address. However, when the user data of these consecutive logical addresses are not actually stored in consecutive physical addresses, the flash controller still needs to read the L2P comparison table from the flash device to know that the user data of the subsequent logical addresses is actually stored The physical address of the HPB will cause the execution of the HPB read command to fail to obtain the expected efficiency. Therefore, the present invention provides a method and device for managing data storage and a computer program product for solving the above-mentioned problems.

In view of this, how to alleviate or eliminate the above-mentioned deficiencies in related fields is a problem to be solved.

This specification relates to a method for managing data storage, executed by a flash memory controller, including: acquiring information about a sub-area to be activated, the sub-area being associated with a logical block address range; triggering a background operation of a garbage collection program for Migrating all or part of the user data in the logical block address range associated with the sub-area to consecutive physical addresses in the flash memory device; and updating the contents of the items corresponding to the sub-area according to the migration result.

The present specification further relates to a computer program product comprising program code, wherein the method of managing data storage as described above is implemented when the program code is loaded and executed by a processing unit of a flash memory controller.

The present specification also relates to a device for managing data storage, comprising: a flash memory interface and a processing unit. The processing unit is used to obtain the information of the sub-area to be activated, wherein the sub-area is associated with a logical block address range; the background operation of triggering the garbage collection program is used to drive the flash memory interface to associate all or a part of the sub-area The above logical block bit The user data in the address interval is migrated to consecutive physical addresses in the flash memory device; and the contents of the plurality of items corresponding to the sub-areas are updated according to the migration result.

Each of the above-mentioned entries contains information about the physical address at which the user data of the logical block address is actually stored in the flash memory device.

One of the advantages of the above embodiment is that, through the triggering of the garbage collection program as described above, the execution of subsequent read commands can directly read data according to the content of the updated item, without spending more time and computing resources from the flash memory device. Read T1 table and perform logical entity address translation.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

10: Electronics

110: Host device

130: Flash Controller

131:Host Interface

132: Busbar

134: Processing unit

135: read-only memory

136: Random Access Memory

139: Flash interface

150: Flash device

151: Interface

153#0~153#15: NAND flash memory unit

CH#0~CH#3: Channel

CE#0~CE#3: Enable signal

310:T2 table

330#0~330#15: T1 table

400#1: Solid Block

410: Entity page

430: Physical address information

430-0: Entity block number

430-1: Entity page number

500:HPB cache

610~650, 711~775, 1011~1037: Operation

S810~S830, S910~S970: method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of the association between the T1 table and the T2 table according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of an association between a T1 table and an entity page according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the establishment and application of a Host Performance Booster (HPB) cache according to an embodiment of the present invention.

FIG. 6 is an operation sequence diagram of reading HPB data according to an embodiment of the present invention.

FIG. 7 is an operation sequence diagram of an application in a host control mode according to an embodiment of the present invention.

FIG. 8 is a flowchart of a method for generating and updating HPB items according to an embodiment of the present invention.

FIG. 9 is a flowchart of a method for reading user data according to an embodiment of the present invention.

FIG. 10 is an operation sequence diagram of an application in a device control mode according to an embodiment of the present invention.

The following description is a preferred implementation manner to complete the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. Reference must be made to the scope of the following claims for the actual inventive content.

It must be understood that the words "comprising", "comprising" and the like used in this specification are used to indicate the existence of specific technical features, values, method steps, work processes, elements and/or components, but does not exclude the addition of further technical features, values, method steps, job processes, elements, components, or any combination of the above.

The use of words such as "first", "second", "third", etc. in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority order, a prepositional relationship between them, or an element Prior to another element, or the chronological order in which method steps are performed, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements can also be read in a similar fashion, such as "between" versus "directly interposed," or "adjacent" versus "directly adjoining," and the like.

Refer to Figure 1. The electronic device 10 includes a host device (also referred to as a host side) 110 , a flash memory controller 130 and a flash memory device 150 , and the flash memory controller 130 and the flash memory device 150 may be collectively referred to as a device side. The electronic device 10 can be implemented in electronic products such as personal computers, notebook computers (Laptop PCs), tablet computers, mobile phones, digital cameras, and digital video cameras. The host device 110 and the host interface (Host Interface) 131 of the flash controller 130 can communicate with each other through a communication protocol such as Universal Flash Storage (UFS). Although the following embodiments describe the function of the Host Performance Booster (HPB) of the UFS specification, those skilled in the art can apply the present invention to similar functions of other specifications, and the present invention is not limited thereby. The flash memory interface 139 of the flash memory controller 130 and the flash memory device 150 can communicate with each other through a Double Data Rate (DDR) protocol, such as Open NAND Flash Interface (ONFI), double data rate switch (DDR Toggle) or other protocols. The flash controller 130 includes a processing unit 134, which may be implemented in a variety of ways, such as using general-purpose hardware (eg, a microcontroller unit, a central processing unit, a multiprocessor with parallel processing capabilities, a graphics processor, or other computing-capable processors) and, when executing software and/or firmware instructions, provide the functions described later. The processing unit 134 receives HPB commands, such as HPB READ Command, HPB READ BUFFER Command, HPB Write Buffer Command (HPB WRITE BUFFER Command), etc. through the host interface 131, and Execute these commands. The flash memory controller 130 includes a random access memory (RAM) 136, which can be implemented as a dynamic random access memory (DRAM), a static random access memory (SRAM) ) or a combination of the above two to configure the space as a data buffer. The random access memory 136 can also store data required in the execution process, such as variables, data tables, and the like. The flash memory controller 130 includes a Read Only Memory (ROM) 135 for storing program codes that need to be executed when booting. The flash memory interface 139 includes a NAND flash controller (NAND Flash Controller, NFC), which provides functions required for accessing the flash memory device 150, such as a command sequencer (Command Sequencer), a low density parity check (Low Density Parity Check, LDPC), etc. .

A bus architecture 132 can be configured in the flash memory controller 130 to couple elements to each other to transmit data, addresses, control signals, etc. These elements include a host interface 131, a processing unit 134, a ROM 135, RAM 136, flash memory interface 139, etc. In some embodiments, the host interface 131, the processing unit 134, the ROM 135, the RAM 136, and the flash memory interface 139 may be coupled to each other through a single bus. In other embodiments, the flash controller 130 may be configured with a high-speed bus for coupling the processing unit 134 , the ROM 135 and the RAM 136 to each other, and a low-speed bus for connecting the processing unit 134 and the host interface 131 to each other. and the flash memory interface 139 are coupled to each other. The bus bars contain parallel physical lines that connect more than two components in the flash controller 130 .

The flash memory device 150 provides a large amount of storage space, usually hundreds of gigabytes (Gigabytes, GB), or even several terabytes (Terabytes, TB), for storing a large amount of user data, such as High-resolution pictures, videos, etc. flash The device 150 includes a control circuit and a memory array, and the memory cells in the memory array can be configured as single-level cells (Single Level Cells, SLCs), multi-level cells (Multiple Level Cells, MLCs), triple-level cells (Triple Level Cells, MLCs) Level Cells, TLCs), Quad-Level Cells (Quad-Level Cells, QLCs), or any combination of the above. The processing unit 134 writes the user data to the specified address (destination address) in the flash memory device 150 through the flash memory interface 139, and reads the user data and L2P comparison from the specified address (source address) in the flash memory device 150 specified section in the table. The flash memory interface 139 uses several electronic signals to coordinate data and command transfer between the flash memory controller 130 and the flash memory device 150 , including a data line, a clock signal, and a control signal. Data lines can be used to transmit commands, addresses, read and written data; control signal lines can be used to transmit Chip Enable (CE), Address Latch Enable (ALE), Command Extraction Enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to FIG. 2 , the interface 151 in the flash memory device 150 may include four I/O channels (hereinafter referred to as channels) CH#0 to CH#3, each of which is connected to four NAND flash memory cells, for example, channel CH #0 connects NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent die. The flash memory interface 139 can enable the NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11 by issuing one of the enable signals CE#0 to CE#3 through the interface 151 , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory cells in parallel, or write user data to the enabled NAND flash memory cells.

Since a continuous piece of data (that is, a piece of data with a continuous logical address) is dispersedly stored in the flash memory cells connected to multiple channels, the flash memory controller 130 uses a logical-to-physical (L2P Mapping Table) table. ) to record the logical address (managed by the host device 110) and physical address (managed by the flash controller) of user data 130 management) correspondence. The L2P mapping table may also be referred to as a host-to-flash mapping table (Host-to-flash, H2F Mapping Table). The L2P comparison table includes a plurality of records, and stores the information of which physical address the user data of each logical address is actually stored in according to the order of the logical addresses. However, since the RAM 136 cannot provide enough space to store the entire L2P lookup table for the processing unit 134 to quickly look up the data read operation in the future, the L2P lookup table can be divided into a plurality of first tables (Table 1, also known as T1 table) ) and stored in the non-volatile flash memory device 150 , so that the corresponding T1 table only needs to be read from the flash memory device 150 to the RAM 136 in the future data read operation. Referring to Figure 3, the entire L2P comparison table can be cut into T1 tables 330#0~330#15. The processing unit 134 further maintains a second table (Table 2, also referred to as a T2 table) 310, which includes a plurality of records and stores the physical address information of the T1 table associated with each logical address segment in the order of logical addresses. For example, the associated T1 table 330#0 of the 0th to 4095th Logical Block Addresses (LBAs) is stored in a specific physical block (the letter "Z") of a specific Logical Unit Number (LUN) ” can represent the number of the LUN and the physical block) of the 0th physical page, the associated T1 table 330#1 of the 4096th to 8191st LBAs is stored in the 1st physical page of a specific physical block of a specific LUN, and so on analogy. Although only 16 T1 tables are included in FIG. 3 , those skilled in the art can set more T1 tables according to the capacity of the flash memory device 150 , and the present invention is not limited thereto.

The space required for each T1 table can be 4KB, 8KB, 16KB, etc. Each T1 table stores the physical address information corresponding to each LBA according to the LBA order, and each LBA corresponds to a fixed-size physical storage space, such as 4KB. Referring to FIG. 4, for example, T1 table 330#0 stores physical address information from LBA#0 to LBA#4095 in sequence. The physical address information 430 can be represented by four bytes: the first two bytes 430-0 record the physical block number (Physical Block Number); the last two bytes 430-1 record the physical page number (Physical Page Number) . For example, physical address information 430 corresponding to LBA #2 may point to physical page 410 in physical block 400 #1. The byte group 430-0 records the number of the physical block 400#1, and the byte group 430-1 records the number of the physical page 410.

Referring to FIG. 5 , in the HPB specification, the host 110 configures a space in its system memory as the HPB cache 500 for temporarily storing the information of the L2P comparison table maintained by the device. The HPB cache 500 stores a plurality of HPB entries (HPB Entries) received from the device, and each HPB entry records information corresponding to a physical address of an LBA. Next, the host side 110 may issue an HPB read command carrying the HPB item to the device side for obtaining the user data of the designated LBA. The device side can directly drive the flash memory interface 139 to read the user data of the specified LBA from the flash memory device 150 according to the information in the HPB item, without the need to spend time and computing resources to read the T1 table from the flash memory device 150 and perform the same as before. The user data of the designated LBA can be read from the flash memory device 150 only after the logical physical address is translated. The establishment and application of HPB cache 500 can be divided into three stages:

Phase I (HPB initialization): The host side 110 requests the device side (specifically, the flash controller 130 ) to obtain its device capability and configure the HPB function, including the HPB mode (Mode).

Phase II (L2P cache management): The host 110 allocates space in the system memory as the HPB cache 500 for storing HPB items. The host 110 may send an HPB READ BUFFER Command to the flash controller 130 at a required time point in the configured mode, for requesting to load a specified HPB item from the device. Next, the host 110 stores the HPB items in one or more sub-regions (Sub-Regions) in the HPB cache 500 . In the HPB specification, the LBAs of each logical unit (eg, Partition) are divided into multiple HPB regions, and each HPB region can be further subdivided into multiple sub-regions.

Phase III (HPB read command): The host 110 searches the HPB entries in the HPB cache 500 for HPB entries containing physical block addresses (PBAs) of the data to be read from the LBA. The PBA can be represented using physical address information 430 as shown in FIG. 4 . Next, the host 110 sends an HPB READ Command to the flash controller 130, in which, except for LBA, transfer length In addition to information such as (TRANSFER LENGTH), it also includes HPB items, which are used to obtain specified user data from the device.

Although the HPB read command contains the information of the HPB item, when the transmission length of the HPB read command is greater than 1 (that is, the host 110 wants to read user data exceeding 4KB), the PBA in the HPB item only It belongs to the starting LBA, so that the flash controller 130 still needs to read the associated T1 table to know the PBA of the LBA after the starting LBA. Referring to the operation sequence diagram of HPB data reading as shown in Figure 6, the detailed description is as follows:

Operation 610 : the host 110 obtains the HPB entry corresponding to the starting LBA to be read from the HPB cache 500 .

Operation 620: The host 110 sends an HPB read command to the flash controller 130, and requests the flash controller 130 for the user data of the designated LBA, which includes the LBA, the transfer length and the HPB item. It should be noted that, the HPB read command may represent a command UFS Protocol Information Unit HPB Read (COMMAND UFS Protocol Information Unit, UPIU HPB Read). The transfer length can be any integer between 1 and 8. For example, when the transmission length is 1, the HPB read command is to read the user data of one LBA; when the transmission length is 2, the HPB read command is to read the user data of two consecutive LBAs; So on and so forth.

Operation 630: The flash controller 130 reads the requested user data from the flash device 150 according to the PBA of the HPB entry. If the transfer length in the HPB read command is greater than 1, the flash controller 130 also needs to read the corresponding T1 table from the flash memory device 150, and obtain the PBA of the subsequent LBA from the T1 table. Next, the flash controller 130 reads the requested user data from the flash memory device 150 according to the PBA of the HPB entry (when the transfer length is equal to 1) or according to the PBA in the read T1 table (when the transfer length is greater than 1).

Operation 640: The flash controller 130 transmits one or more data input UPIUs to the host 110, including the requested user data. Each data input UPIU can transmit 4KB of user data. After all requested user data are sent to the host 110, the flash controller 130 sends a reply UPIU to the host 110, indicating that the HPB read command has been completed message.

Operation 650: The host 110 processes the user data according to the needs of the operating system, drivers, applications and the like.

As can be seen from the above description, when the transfer length in the HPB read command is greater than 1, the flash controller 130 cannot save the time for reading the T1 table from the flash device 150 and performing logical physical address translation, thus losing the advantages of the original HPB function.

Those skilled in the art understand that the length (eg, 8 bytes) of each HPB entry of the HPB specification may be greater than the length (eg, 4 bytes) of the physical address information associated with each LBA recorded in the T1 table. In order to solve the above problem, in addition to the physical address information of each LBA (that is, the PBA information of the LBA recorded in the T1 table), the processing unit 134 can add the continuity information of the corresponding PBA to the remaining space of the HPB entry , used to speed up future HPB read operations. The continuity information of each HPB entry describes the consecutive physical addresses in the flash memory device 150 where the user data of the specific LBA interval following this LBA is stored.

In some embodiments of Phase II, the processing unit 134 may fill the HPB entry of each octet with 4-byte corresponding PBA information and the 4-byte Continuous Length. The contiguous length indicates how many LBAs are consecutively stored in the physical address of the flash memory device 150 after the LBA. Therefore, one HPB entry can express information for multiple consecutive PBAs in the T1 table. Examples of HPB projects are shown in Table 1:

For example, the 11th HPB item in Table 1 is associated with LBA#11, the user data of LBA#11 is stored in PBA "212344" and the user data continuity of LBA#11~17 (7 LBAs in total) physical addresses stored in the flash memory device 150 . The 12th HPB item in Table 1 is associated with LBA#12, the user data of LBA#12 is stored in PBA "212345" and the user data of LBA#12~17 (6 LBAs in total) are continuously stored in flash memory Physical address in device 150. In the future, the processing unit 134 can read the user data of LBA #11-17 according to the information carried in the eleventh HPB item. That is, if the HPB read command indicates that the starting LBA to be read is LBA#11 and the transfer When the length is less than or equal to "7", the processing unit 134 does not need to read the corresponding T1 table from the flash memory device 150, but directly reads the user data from the speculative PBA of the flash memory device 150 and replies to the host 110.

In other embodiments of Phase II, the processing unit 134 may fill in the corresponding 4-byte PBA information and the 4-byte Continuous Bit Table in each 8-byte HPB entry. The contiguous bit table is used to represent the PBA contiguity of multiple subsequent LBAs (eg, 32 subsequent LBAs) of this LBA. For example, 32 bits respectively correspond to 32 subsequent LBAs. Examples of HPB projects are shown in Table 2:

For example, the 11th HPB entry in Table 2 is associated with LBA#11, the user data of LBA#11 is stored in PBA "212344" and the contiguous bit table is stored in "0x0000003F" (ie "0b00000000000000000000000000111111"), indicating that User data of LBAs #11 to 17 (7 LBAs in total) are continuously stored at physical addresses in the flash memory device 150 .

If the data stored in the flash memory device 150 has a considerable degree of discontinuity (also referred to as random storage in the flash memory device 150 ), although the continuity information is provided to the flash memory controller 130 in advance, when the HPB read command requests the transfer length When the contiguous length is larger than that carried in the HPB entry, the flash controller 130 also needs to read the corresponding T1 table from the flash device 150 and perform logical physical address translation. For example, with the example of Table 1 or Table 2, when the host 110 requests to read the user data of LBAs #3-10, the flash controller 130 still needs to read the T1 table 330#0 from the flash memory device 150. That is, when the data is randomly stored in the flash memory device 150, the execution performance of the HPB read command is almost the same as that of the previous UFS read command.

In some embodiments, when flash controller 130 (more specifically, processing unit 134 in flash controller 130 during execution of certain firmware or software instructions) is aware of storage in a subsection of HPB cache 500 in Phase II When there are T1 tables corresponding to HPB entries corresponding to multiple consecutive LBA intervals, the flash controller 130 can analyze the content of the corresponding T1 table to determine which LBA intervals in the specific sub-area of the HPB cache 500 have random user data The physical address stored in the flash memory device 150 . Then, the flash controller 130 may perform the background operation of the garbage collection procedure in phase II or phase III for migrating (writing) the user data of the specified LBA interval to the consecutive physical addresses in the flash memory device 150, and Update the corresponding T1 table and the HPB entry for this subregion. The updated result may be temporarily stored in RAM 136 first. For example, the example HPB project in Table 1 can be updated as shown in Table 3:

After the execution of the garbage collection procedure is completed, the flash controller 130 notifies the host 110 to update the HPB entry of the subarea. After receiving the update message, the host 110 issues an HPB read buffer command to obtain the updated HPB entry, and accordingly updates the content of the subarea in the HPB cache 500 . Therefore, most of the user data of a continuous LBA interval requested to be read in the HPB read command sent by the host 110 is stored in a continuous physical address in the flash memory device 150, so that the execution performance of the HPB read command can be further improved.

The HPB specification defines two modes for obtaining HPB items: Host Control Mode and Device Control Mode. The host control mode is triggered by the host 110 to determine which HPB subareas need to be stored in the HPB cache 500 ; and the device control mode is triggered by the flash controller 130 to determine which HPB subareas need to be stored in the HPB cache 500 . Those skilled in the art understand that the embodiments of the present invention cover these two or other similar control modes.

Referring to the operation sequence diagram applied in the host control mode as shown in Figure 7, the detailed description is as follows:

Operation 711: The host 110 determines which sub-regions are about to be activated (Activated).

Operation 713: The host 110 sends an HPB read buffer command to the flash controller 130, and requests the flash controller 130 to determine the HPB entry of the subarea. The HPB read buffer command can contain 10 bytes, of which the 0th byte records the operation code (Operation Code) "F9h", the 2nd and 3rd bytes record the information about the HPB area to be activated, and the first byte The 4th and 5th bytes record the information about the subarea to be activated.

Operation 715: The flash controller 130 generates an HPB entry corresponding to the boot sub area. For the technical details of the generating operation 715, please refer to the flowchart of the method for generating and updating the HPB item shown in FIG. 8. This method is implemented by the processing unit 134 when the relevant software or firmware code is loaded and executed, which is further explained as follows :

Step S810 : Drive the flash memory interface 139 to read the specific T1 table from the flash memory device 150 .

Step S820: Arrange HPB items according to the content of the read T1 table. In order to improve the efficiency of reading, in addition to the PBA, the processing unit 134 also adds the above-mentioned PBA continuity information to the HPB item.

Step S830: Trigger the background operation corresponding to the garbage collection program of the initiator sub-area. After the flash memory controller 130 receives the HPB read buffer command, the flash memory controller 130 not only arranges the read comparison information for the HPB entry to reply to the host 110, but also triggers the background operation of the garbage collection program to The user data of all or a specified part of the LBA interval associated with the initiator area is migrated (written) to the contiguous physical address in the flash memory device 150 . The processing unit 134 may also maintain a variable in the RAM 136 for recording the execution status of the garbage collector of the initiator area. Initially, the variable records information that this promoter region is not associated with any garbage collector. When the garbage collector is triggered, the variable records the information that the garbage collector in this initiator area is executing. Flash controller 130 updates the corresponding T1 table temporarily stored in RAM 136 and the HPB entry for this sub-area when each batch of migration (write) operations is completed, wherein a batch of migration (write) operations corresponds to User data for a portion of the LBA region in the promoter region. After the execution of the garbage collection procedure is completed, the flash controller 130 updates the variable for recording the information that the execution of the garbage collection procedure in the startup subarea has been completed.

Please refer back to Figure 7. Operation 717 : The flash controller 130 transmits a DATA IN UFS Protocol Information Unit (UPIU) to the host 110 .

If the corresponding garbage collection procedure has not been completed, the flash controller 130 first replies to the data input UPIU containing the original HPB entry (such as the example shown in Table 1). Afterwards, when receiving the HPB read command corresponding to the boot sub area from the host 110 , the flash controller 130 may not reply to the user data requested to be read, but first reply a message to the host 110 , requesting the host 110 Update the HPB project for this promoter region.

If the garbage collector has been executed, the data input UPIU contains the updated HPB entry (example shown in Table 3). In the flash controller 130, the After the updated HPB entry is sent to the host 110, the variable in the RAM 136 is updated to the information that the startup subarea is not associated with any garbage collector.

Operation 719 : the host 110 stores the received HPB entry into the promoter region in the HPB cache 500 .

Operation 731: The host 110 determines which regions are about to be deactivated. It should be noted here that in the HPB specification, startup is based on sub-areas, and shutdown is in units of regions. The host 110 can determine the sub-region to be activated and the region to be closed according to the requirements of its algorithm.

Operation 733: The host side 110 sends an HPB write buffer command (HPB WRITE BUFFER command) to the flash controller 130, and notifies the flash controller 130 of the area determined to be closed. The HPB read buffer command may contain 10 bytes, wherein the 0th byte records the opcode "FAh" and the 2nd and 3rd bytes record the information of the area to be closed.

Operation 735: The flash controller 130 closes the region. For example, after the flash memory controller 130 transmits the HPB item to the host side 110, the flash memory controller 130 can perform an optimization operation on the read process of the subsequent read command from the host side 110 for the activated sub-area, and then After the host 110 is notified of the closed area, the flash controller 130 can terminate the relevant optimization operation corresponding to the closed area.

Operation 751 : If necessary, the flash controller 130 drives the flash interface 139 to update the content of the corresponding T1 table in the flash device 150 after executing the garbage collection procedure of the specific startup sub-region. In addition, the flash controller 130 updates a specific variable in the RAM 136 to indicate that the garbage collection process of the startup sub-region has been executed. It should be noted here that, if the garbage collection program of the specific promoter area has been executed in operation 715, the flash controller 130 does not need to perform the update operation 751, so the subsequent operations 753 to 775 do not need to be performed again. implement.

Operation 753 : The flash controller 130 transmits a reply UFS protocol information unit (RESPONSE UPIU) to the host 110 , which includes recommending the host 110 to update the HPB of the sub-region. project information.

Operations 755 and 757 : The host side 110 sends an HPB read buffer command to the flash controller 130 to request the flash controller 130 for the HPB entry associated with the proposed subregion.

Operation 771 : The flash controller 130 reads the updated HPB entry of the above sub-area from the RAM 136 .

Operation 773: The flash controller 130 transmits the data input UPIU to the host 110, which includes the updated HPB entry of the above-mentioned sub-area.

Operation 775: The host 110 overwrites the content in the promoter region of the HPB cache 500 with the received updated HPB entry.

In the host control mode, the technical content of the read operation 630 in FIG. 6 needs to be modified in order to cope with the background operation as described above. Referring to the flowchart of the method for reading user data as shown in FIG. 9 , the method is implemented by the processing unit 134 when the relevant software or firmware code is loaded and executed, which is further described as follows:

Step S910: The processing unit 134 receives the HPB read command from the host terminal 110 through the host interface 131, which includes the LBA, the transmission length and the HPB item.

Step S920: The processing unit 134 determines the subarea to which the HPB item in the HPB read command belongs according to the LBA and the transmission length in the HPB read command.

Step S930: The processing unit 134 determines whether the HPB item of the sub-region to which it belongs needs to be updated. If so, the flow continues with the processing of step S970. Otherwise, the flow continues to the process of step S950. The processing unit 134 can judge according to the variables stored in the RAM 136 and corresponding to the sub-areas. If the sub-area to which this variable record belongs is not associated with any garbage collector information, the HPB entry representing the sub-area does not need to be updated. If this variable records the information that the garbage collector of the sub-area is executing or has been executed, it means that the HPB item of the sub-area to which it belongs needs to be updated.

Step S950 : The processing unit 134 drives the flash memory interface 130 to read the user data of the requested LBA section from the flash memory device 150 according to the content of the HPB item carried by the HPB read command. It should be noted that, due to the background operation of the garbage collector, the corresponding Most of the user data of the consecutive LBAs of the subarea are stored in consecutive physical addresses in the flash memory device 150, so in most cases, the processing unit 134 can directly read the content of the HPB item carried by the HPB read command from the flash memory device 150. Get the user data of the requested LBA interval.

Step S960: The processing unit 134 drives the host interface 131 to transmit one or more data input UPIUs to the host, including the read user data.

Step S970 : The processing unit 134 drives the host interface 131 to transmit a reply UPIU to the host 110 , which includes the information suggesting that the host 110 update the HPB item of the sub-area. After the host 110 receives the reply UPIU, the host 110 can perform the sending operation 755 as described in FIG. 7 to start the update of the HPB item of the above-mentioned sub-area.

Referring to the operation sequence diagram applied in the device control mode as shown in Figure 10, the detailed description is as follows:

Operation 1011: The flash controller 130 actively decides which sub-regions are about to be powered on and/or which regions are about to be powered off.

Operation 1012: The flash controller 130 generates an HPB entry corresponding to the boot sub area. For the technical details of the generating operation 1012, reference may be made to the content of step S830 in FIG. 8 as described above, which will not be repeated for brevity.

Operation 1013: The flash controller 130 transmits a reply UPIU to the host side 110, wherein the host side 110 is advised to activate the above-mentioned sub-area and/or close the above-mentioned area. In this mode, the device side decides when to activate the subarea, so the flash controller 130 can send a reply UPIU to the host side 110 after the background operation of the garbage collector corresponding to the subarea is completed.

Operation 1015: If necessary, the host side 110 discards the HPB entries of those HPB regions that are no longer valid from the system memory.

Operation 1031 : If necessary, the host side 110 sends an HPB read buffer command to the flash controller 130 to request the flash controller 130 for the HPB item of the proposed subarea.

Operation 1033: The flash controller 130 reads the HPB entries of the requested subregion from the RAM 136, wherein each HPB entry contains the PBA continuity information as described above.

Operation 1035: The flash controller 130 transmits the data input UPIU to the host 110, which includes the HPB entry corresponding to the above-mentioned sub-area. After transferring the HPB entry corresponding to the above-mentioned sub-area, the processing unit 134 may update the variable corresponding to the above-mentioned sub-area in the RAM 136 to record the information that the sub-area is not associated with any garbage collection program.

Operation 1037 : the host 110 stores the received HPB entry into the promoter region in the HPB cache 500 .

All or part of the steps in the method of the present invention can be implemented by computer instructions, such as a firmware translation layer (Firmware Translation Layer, FTL) in a storage device, a driver of a specific hardware, and the like. In addition, it can also be implemented in other types of programs. Those skilled in the art can compose the methods of the embodiments of the present invention into computer instructions, which will not be described for brevity. Computer instructions for implementing methods according to embodiments of the present invention may be stored in a suitable computer-readable medium, such as DVD, CD-ROM, USB disk, hard disk, or may be other suitable vehicles) to access the web server.

Although the above-described elements are included in FIGS. 1 to 2 , it is not excluded that more other additional elements may be used to achieve better technical effects without departing from the spirit of the invention. In addition, although the flowcharts of Fig. 8 and Fig. 9 are executed in the specified order, those skilled in the art can modify the order of these steps under the premise of achieving the same effect without violating the spirit of the invention. Therefore, The present invention is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the scope of the appended claims is to be construed in the broadest manner so as to encompass all obvious modifications and similar arrangements.

S810~S830: method steps

Claims (14)

A method for managing data storage, executed by a flash memory controller, comprising: obtaining information of a sub-area to be activated from a first read command sent by a host, wherein the sub-area is associated with a segment of logical block bits address interval, and the first read command requests the flash memory controller to provide a plurality of items associated with the sub-area for storing the plurality of items associated with the sub-area to a system memory in the host side After receiving the above-mentioned first read command, trigger a background operation of a garbage collection program for migrating all or part of the user data in the above-mentioned sub-area associated with the above-mentioned logical block address interval to a flash memory device. Consecutive physical addresses; and updating the contents of a plurality of items corresponding to the sub-areas according to the migration result, wherein each of the items includes user data of a logical block address that is actually stored in a physical bit in the flash memory device address information. The method for managing data storage according to claim 1, wherein each of the above items includes continuity information, and the user data describing a specific logical block address interval following a corresponding logical block address is stored in the flash memory device Consecutive physical addresses in . The method for managing data storage according to claim 1, comprising: after the execution of the garbage collection program is completed, sending a reply to the host side, including suggesting that the host side update a plurality of items in the sub-area; from the host side Receive a second read command, the second read command requests the flash controller to provide a plurality of items associated with the sub-area; read the updated items of the sub-area; and transmit the update of the sub-area After the project to the above host side. The method for managing data storage according to claim 1, comprising: when a background operation of the garbage collection program is triggered, updating a first variable for recording information that the garbage collection program is executing; and when the garbage collection program is executed After the completion, the first variable is updated to record the information that the garbage collection program has been executed. The method for managing data storage according to claim 4, comprising: receiving a third read command from the host, wherein the third read command includes a logical block address, a transmission length and an item; according to The above-mentioned logical block address and the above-mentioned transmission length determine the sub-area to which the above-mentioned item belongs; and when a second variable corresponding to the above-mentioned sub-area records information that the garbage collection program corresponding to the above-mentioned sub-area is being executed or has been executed , sending a reply to the host, including suggesting that the host update a plurality of items in the sub-area to which it belongs. The method for managing data storage according to claim 1, comprising: actively determining the above-mentioned sub-areas to be activated. A computer program product, comprising a program code, wherein, when the program code is loaded and executed by a processing unit of a flash memory controller, the method for managing data storage as described in any one of claims 1 to 6 is implemented . A device for managing data storage, comprising: a flash memory interface coupled to a flash memory device; a processing unit coupled to the flash memory interface for a first read sent from a host Obtaining information about a sub-area to be activated in the fetch command, wherein the sub-area is associated with a logical block address range, and the first read command requests the flash memory controller to provide a plurality of items associated with the sub-area, for storing the above-mentioned multiple items associated with the above-mentioned sub-areas in a system memory in the above-mentioned host side; after receiving the above-mentioned first read command, triggering a background operation of a garbage collection program for driving the above-mentioned flash memory The interface migrates all or a part of the user data in the logical block address range associated with the sub-area to consecutive physical addresses in a flash memory device; and updates the contents of a plurality of items corresponding to the sub-area according to the migration result, Wherein, each of the above-mentioned items includes information of a physical address where the user data of a logical block address is actually stored in the above-mentioned flash memory device. The device for managing data storage as claimed in claim 8, wherein each of the above items includes continuity information, and user data describing a specific logical block address interval following a corresponding logical block address is stored in the flash memory device Consecutive physical addresses in . The device for managing data storage according to claim 8, comprising: a host interface coupled to the host and the processing unit, wherein the processing unit receives the first read command from the host through the host interface. The device for managing data storage according to claim 10, wherein the processing unit sends a reply to the host through the host interface after the garbage collection program is executed, including a number of suggestions for the host to update the sub-area. receive a second read command from the host side through the host interface, the second read command requests the flash memory controller to provide a plurality of items associated with the sub-area; read the updated sub-area item; and transmitting the updated item of the sub-area to the host through the host interface. The device for managing data storage according to claim 10, comprising: a random access memory, coupled to the processing unit, to store a first variable, wherein when the processing unit triggers the background operation of the garbage collection program, update The first variable is used to record the information that the garbage collection program is being executed; and the processing unit updates the first variable after the garbage collection program is executed, and is used to record the information that the garbage collection program has been executed. The device for managing data storage according to claim 12, wherein the processing unit receives a third read command from the host through the host interface, wherein the third read command includes a logical block address, a transfer length and an item; determine the sub-area to which the item belongs according to the logical block address and the transfer length; and when a second variable record corresponding to the sub-area corresponds to the garbage collection process of the sub-area When the information is executed or has been executed, a reply is sent to the host through the host interface, including suggesting that the host update a plurality of items in the sub-area to which it belongs. The device for managing data storage according to claim 8, wherein the processing unit actively determines the sub-area to be activated.

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