TW202006553A - Methods for internal data movement of a flash memory and apparatuses using the same - Google Patents

Abstract

A method for internal data movement, performed by a processing unit of a solid state disk (SSD), includes: receiving an internal data movement command, which instructs the SSD to move data of a source location of an input/output (I/O) channel to a new location of the I/O channel; performing a copyback procedure to move data of the source location of the I/O channel to a destination location of the I/O channel; and replying to the host with a completion element (CE) according to an execution result of the copyback procedure.

Description

Method for internally transferring data of flash memory and device using the method

The invention relates to a flash memory, in particular to a method for internally transferring data of a flash memory and a device using the method.

Flash memory devices are generally divided into NOR flash devices and NAND flash devices. The NOR flash device is a random access device. The host device (Host) can provide any address for accessing the NOR flash device on the address pin, and the data pin of the NOR flash device is instantly obtained and stored in the User data at this address. In contrast, NAND flash devices are not random access, but sequential access. The NAND flash device cannot access any random address like the NOR flash device. Instead, the master device needs to write the sequence of bytes (Bytes) to the NAND flash device to define the command Type (eg, read, write, erase, etc.), and the address on this command. The address can point to a page (the smallest data block of a write operation in the flash memory) or a block (the smallest data block of an erase operation in the flash memory). In fact, NAND flash devices usually read or write complete pages of data from memory cells. After a whole page of data is read from the array to the buffer in the device, by using the Strobe Signal to sequentially knock out the content, the main unit can be byte by byte or word Tuples (Words) access data.

The Open-Channel Solid State Disk (Open-Channel Solid State Disk) system includes an open-channel solid state disk (device side) and a main device. Instead of implementing a Flash Translation Layer (FTL) on the device side, it is located on the main The device implements a flash memory translation layer. Unlike traditional solid state drives, open channel solid state drives let the host device know the internal operating parameters of the solid state drive, and allow the host device to operate the open channel solid state drives based on the operating parameters, that is, to manage data. However, current open channel SSDs only contain three basic access commands: erase; read; and write. When the host device executes a series of access procedures that can be completed by reading and writing, such as garbage collection (GC, Garbage Collection), wear leveling (Wear Leveling), etc., it is necessary to transfer data through the access interface of the open channel solid state drive , Which consumes a lot of bandwidth of the access interface.

Therefore, a method for internally transferring data in a flash memory and a device using the method are needed to solve the above-mentioned problems.

In view of this, how to mitigate or eliminate the above-mentioned deficiencies in related fields is really a problem to be solved.

The invention proposes a method for internally moving data in a flash memory, which is executed by a processing unit of a solid-state hard disk, and includes: receiving an internal moving command and instructing to move the data of the source position of the input/output channel to a new position of the input/output channel; execution The copy-back writing program of the I/O channel is used to move the data of the source position of the input-output channel to the destination position of the I/O channel; and reply the completed component to the main device according to the execution result of the copy-back writing program.

The invention also provides a data internal transfer device of a flash memory, including: a flash controller; and a processing unit. The flash controller is coupled to the storage unit, and the storage unit includes input and output channels. The processing unit is coupled to the flash controller, and is used to receive an internal move command from the main device, instruct to move the data of the source position of the I/O channel to the new position of the I/O channel; instruct the flash controller to execute the copy back of the I/O channel Write program, used to move the data of the source position of the I/O channel to the destination position of the I/O channel; and reply the completed component to the host device according to the execution result of the copy-back write program.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the scope of the following claims.

It must be understood that the terms "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, work processes, components and/or components, but do not exclude Add more technical features, values, method steps, job processing, components, components, or any combination of the above.

The terms such as "first", "second", and "third" are used in the claims to modify the elements in the claims, not to indicate that there is a priority order, prior relationship, or is an element Prior to another component, or the time sequence when performing method steps, is only used to distinguish components with the same name.

FIG. 1 is a schematic diagram of the architecture of an open channel SSD system 100 according to an embodiment of the present invention. The architecture of the open channel solid state drive system 100 includes a main device 110, a data buffer (Data Buffer) 120, and an open channel solid state drive (SSD, Solid State Disk) 130. The main device 110 can create a queue, a storage mapping table (also known as an L2P Logical-to-Physical table) and a usage record according to its needs during operation. This system architecture can be implemented in personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, digital cameras and other electronic products. The data buffer 120, the queue, the physical storage comparison table, and the usage record may be implemented in a specific area in a random access memory (RAM). The main device 110 communicates with the open channel solid state hard disk 130 through an open channel solid state hard disk fast non-volatile memory (NVMe, Non-Volatile Memory express) interface. The host device 110 can be implemented in various ways, for example, using general-purpose hardware (eg, a single processor, a multiprocessor with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and executing instructions (Instructions) , Macrocode (Macrocode) or Microcode (Microcode), provide the functions described later. The main device 110 may include an arithmetic logic unit (ALU, Arithmetic and Logic Unit) and a shifter (Bit Shifter). The arithmetic logic unit is responsible for performing Boolean operations (such as AND, OR, NOT, NAND, NOR, XOR, XNOR, etc.) or mathematical operations (such as addition, subtraction, multiplication, division, etc.), and the shifter is responsible for displacement operations and bit rotation . Open channel SSD NVMe specifications, such as version 1.2, released in April 2016, support several I/O Channels, each I/O channel is connected to a logical unit number (LUNs, Logical Unit Numbers), used In order to correspond to a plurality of storage subunits in the storage unit 139, respectively. In the open channel SSD NVMe specification, the host device 110 integrates the Flash Translation Layer (FTL) originally implemented in the device to optimize the load. The conventional flash memory translation layer maps the logical block addresses (LBAs) recognized by the host device or the file system to the physical addresses of the storage unit 139 (also called logical-to-physical mapping). In the open channel SSD NVMe specification, the main device 110 can instruct the open channel solid-state drive 130 to store user data to a physical address in the storage unit 139. Therefore, the maintenance of the physical storage comparison table is the responsibility of the main device 110 and It records the physical address in the storage unit 139 where the user data of each logical block address is actually stored.

The open channel SSD 130 includes a processing unit 133. The processing unit 133 can communicate with the host device 110 using the open channel SSD NVMe protocol to receive data access commands including physical addresses, and instruct the flash controller 135 to perform erasing, reading, or writing according to the data access commands Into. It should be noted here that the processing unit 133 may be implemented using a light-weight general-purpose processor (Lightweight General-Purpose Processor).

The open channel SSD 130 further includes a flash controller 135, an access interface 137, and a storage unit 139, and the flash controller 135 communicates with the storage unit 139 through the access interface 137. In detail, a double data rate can be used (Double Data Rate, DDR) communication protocol, such as Open NAND Flash Interface (ONFI), Double Data Rate Switch (DDR Toggle), or other interfaces. The flash controller 135 of the open channel SSD 130 writes user data to the specified address (destination address) in the storage unit 139 through the access interface 137, and the specified address (source bit) from the storage unit 139 Address) to read user data. The access interface 137 uses several electronic signals to coordinate the transfer of data and commands between the flash controller 135 and the storage unit 139, including the data line (Data Line), clock signal (Clock Signal) and control signal (Control Signal). The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transfer Chip Enable (CE), Address Latch Enable (ALE), and command extraction Control signals such as Command Latch Enable (CLE) and Write Enable (WE). The processing unit 133 and the flash controller 135 may exist separately or be integrated in the same chip.

During system boot, the main device 110 obtains from the open channel SSD 130 the operating parameters required to control the operation of the open channel SSD 130, such as the number of blocks, the number of bad blocks, and the lag Time (latency), total number of input and output channels, etc.

The storage unit 139 may include a plurality of storage subunits, and each storage subunit uses its associated access subinterface to communicate with the flash controller 135. One or more storage subunits can be packaged in a die. FIG. 2 is a block diagram of an access interface and a storage unit according to an embodiment of the invention. The open channel SSD 130 may include j+1 accessor interfaces 137_0 to 137_j, and each accessor interface is connected to i+1 storage subunits. The access sub-interface and subsequent storage sub-units can be collectively referred to as I/O channels, and can be identified by the logical unit number. In other words, i+1 storage subunits share an accessor interface. For example, when the open channel SSD 130 includes 4 I/Os (j=3) and each input/output is connected to 4 storage units (i=3), the open channel SSD 130 has a total of 16 storage subunits 139_0_0 To 139_j_i. The flash controller 135 can drive one of the access sub-interfaces 137_0 to 137_j to read data from the designated storage sub-unit. Each storage subunit has an independent chip enable (CE) control signal. In other words, when reading data from the specified storage subunit, the associated access subinterface needs to be driven to enable the chip enable control signal of the storage subunit. FIG. 3 is a schematic diagram of connection between an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention. The flash controller 135 can select one of the connected storage subunits 139_0_0 to 139_0_i using the independent chip enable control signals 320_0_0 to 320_0_i through the access sub-interface 137_0, and then select from the selected through the shared data line 310_0 To read data at the specified address of the storage subunit.

FIG. 4 is a schematic diagram of the storage unit 139. The storage unit 139 includes multiple data planes (Data Planes) 410_0 to 410_m, 430_0 to 430_m, 450_0 to 450_m, and 470_0 to 470_m. Each data plane or multiple data planes are placed in a logical unit number. The data planes 410_0 to 410_m and the shared access sub-interface are called I/O channels 410, the data planes 430_0 to 430_m and the shared access sub-interfaces are called I/O channels 430, the data planes 450_0 to 450_m and the shared access sub-interfaces Called I/O channel 450, and the data planes 470_0 to 470_m and the shared access sub-interface are called I/O channels 470, where m can be an integer to the power of 2 (eg 2, 4, 8, 16, 32, etc. ), I/O channels 410, 430, 450 and 470 can be identified using logical unit numbers. Each of the data planes 410_0 to 470_m includes multiple physical blocks, each physical block includes multiple pages (Pages) P#0 to P#(n), and each page includes multiple areas Sectors (for example, 4, 8, etc.), where n may be 767, 1535, or the like. Each page contains multiple NAND memory cells (Memory Cells), and NAND memory cells can be single-level cells (Single-Level Cells, SLCs), multi-level cells (Multi-Level Cells, MLCs), three-tier type Cells (Triple-Level Cells, TLCs) or quad-level cells (Quad-Level Cells, QLCs). In some embodiments, when each NAND memory cell is a single-layer cell and can record two states, the page P#0 in the data plane 410_0 to 470_0 can virtually form a Super Page (Super Page) 490_0, the data plane Pages P#1 in 410_0 to 470_0 can be virtually formed as a super page 490_1, and so on. In other embodiments, when each NAND memory cell is a multi-layer cell and can record 4 states, a physical word line may include page P#0 (which may be called the lowest bit page, MSB, Most Significant Bit page), page P#1 (may be called the highest bit page, LSB, Least Significant Bit page), and so on. In still other embodiments, when each NAND memory cell is a three-layer cell and can record 8 states, a physical word line may include page P#0 (which may be called the lowest bit page, MSB page ), page P#1 (may be called Center Significant Bit page, CSB, Center Significant Bit page) and page P#2 (may be called the highest bit page, LSB page). When each NAND memory cell is a four-layer cell and can record 16 states, in addition to the MSB, CSB, and LSB pages, it also includes a TSB (top significant bit) page.

When the storage unit 139 is in operation, the page can be the smallest unit for data management or programming. The size is, for example, 16KB. At this time, the physical address can be expressed as a page number; The segment can be the smallest unit of data management. In this case, the physical address can be expressed as the sector number of the page (Sector numbers) or the offset of the sector on the page (Offset). The block is the smallest unit for erasing data.

Physical blocks can be divided into active blocks, data blocks, and idle blocks according to their usage status. The active block represents a physical block that is currently writing data, that is, a physical block that has not yet written End of Block information. The data block is a physical block that has written end-of-block information, that is, no user data is written. The idle block can be selected to become an active block, and the idle block does not store any valid user data. Generally, after an idle block is selected, an erase operation is required to become an active block.

In some embodiments, the physical address sent by the main device 110 to the open channel SSD 130 may include logical unit number, data plane number, physical block number, physical page number, and section number, etc., to indicate the desired The read or written user data is located in a specific section in a specific physical page in a specific physical block in a specific data plane in a specific data channel in a specific input and output channel. In some embodiments, sometimes the column number is replaced by the column number. In other embodiments, the physical address sent by the main device 110 to the open channel SSD 130 may include information such as the logical unit number, data plane number, and physical block number to indicate that a specific input/output channel is to be erased Specific data blocks in the specific data plane of.

Figure 5 is a schematic diagram of the command queue. The queue may include a submission queue (Submission Queue) 510 and a completion queue (Completion Queue) 530, which are used to temporarily store a master device command and a completion element (Completion Element), respectively. Each of the submission queue 510 and the completion queue 530 includes a collection of multiple entries. Each entry in the submission queue 510 stores a host device command, such as an input/output command (hereinafter referred to as a data access command) or a management command, and each entry in the completion queue 530 is stored and associated with a data access The completion component of a command or management command. This completion component functions like a confirmation message. The items in the collection are stored sequentially. The basic principle of the operation of the collection is to add an entry from the end position (may be referred to as enqueue), and remove an entry from the start position (may be referred to as dequeue). In other words, the first command or message added to the submission queue 510 or the completion queue 530 will also be the first to be removed. The host device 110 may write a data access command (eg, erase, read, write command, etc.) to the submission queue 510, and the processing unit 133 reads from the submission queue 510 (or called extraction) Fetch) The earliest arriving data access command and execute it. After the execution of the data access command is completed, the processing unit 133 writes the completion element to the completion queue 530, and the host device 110 can read or extract the completion element to determine the execution result of the data access command.

Figure 6 is a flow chart of the execution steps of the data access command. The host device 110 generates and writes a data access command (eg, erase, read, write command, etc.) to the submission queue 510 (step S1110), where the data access command includes information of the physical address, and, The physical address points to a specific block, page or section address. Next, the main device 110 issues a submission doorbell (Submission Doorbell) to the processing unit 133 (step S1120), to notify the processing unit 133 that the data in the submission queue 510 has written a data access command, and update the submission queue 510 The value of Tail at the end of the queue. After receiving the delivery doorbell (step S1310), the processing unit 133 reads the (earliest arriving) data access command from the delivery queue 510 (step S1320), and instructs the flash controller 135 according to the data access command to complete The designated operation (for example, erasing, data reading, writing, etc.) (step S1330). After the designated operation is completed, the processing unit 133 generates and writes the completion element to the completion queue 530 (step S1340) to notify the host device 110 of the execution status information of the operation corresponding to the specific data access command, and issues an interrupt to the host device ( Step S1350). After receiving the interrupt (step S1130), the main device 110 reads the (earliest arriving) completion element from the completion queue 530 (step S1130), and then sends a completion doorbell to the processing unit 133 (step S1140). After receiving the doorbell (S1360), the processing unit 133 updates the value of the head of the completed queue 530.

In steps S1120 and S1140, the host device 110 may set up corresponding registers to issue the doorbell delivery and end doorbell to the processing unit 133.

A data access command can process multiple user data, for example: 64, then the completion component can include a 64-bit execution response table, each bit represents the execution result of each user data, such as: "0" means success, "1" means failure. The data access command includes an operation code field to store the type of the data access command (for example, erase, read, write, etc.). The completion component includes a status field for storing the execution status (for example, success, failure, etc.) of the corresponding data access command. In addition, the processing unit 133 can execute the data access commands out of order or in order of priority. Therefore, both the data access command and the completion element include a command identifier (Command Identifier), so that the main device 110 can use each Complete component access to specific data access commands.

For example, an idle block needs to be erased to become an active block before writing, and the master device 110 can write an erase command to submit the queue 510 (step S1110) to instruct the open channel SSD 130 ( In detail, the processing unit 133) performs an erasing operation on a specific idle block in a specific input/output channel. In response to the erase command, the processing unit 133 instructs the flash controller 135 to drive the access interface 137 to complete the erase operation specified in the storage unit 139 (step S1330). When the erasing operation is completed, the processing unit 133 writes the completion element to the completion queue 530 (step S1340) to notify the main device 110 that the corresponding erasing operation has been completed.

For example, the host device 110 may write a read command to the submission queue 510 (step S1110) to instruct the open channel SSD 130 to output a specific data in a specific physical block in a specific data plane in a specific channel of the channel The physical page (specific section) reads user data. The processing unit 133 instructs the flash controller 135 to read the user data from the physical address specified in the storage unit 139 through the drive access interface 137 in response to the read command, and stores the user data to the data specified by the read command The buffer 120 (step S1330). When the reading operation is completed, the processing unit 133 writes the completion element to the completion queue 530 (step S1340) to notify the host device 110 that the corresponding reading operation has been completed.

For example, the host device 110 may store the user data to be written in the data buffer 120, and store the write command to the submission queue 510 (step S1110) to instruct the open channel solid state hard disk 130 to write the user data To a specific physical page (a specific section) in a specific active block in a specific data plane in a specific I/O channel, where the write command includes the address in the data buffer 120 where the user data to be written is stored News. The processing unit 133 reads the user data to be written from the specified address in the data buffer 120 in response to the write command, and instructs the flash controller 135 to program the user data to the storage unit 139 through the drive access interface 137 The physical address specified by the write command in step (step S1330). When the writing operation is completed, the processing unit 133 writes the completion element to the completion queue 530 (step S1340) to notify the host device 110 that the corresponding writing operation has been completed.

After multiple accesses, a physical page may contain valid and invalid segments (also known as expired segments), where valid segments store valid user data and invalid segments store invalid (old) usage者资料。 Information. In some embodiments, when the main device 110 detects that the available space of the storage unit 139 is insufficient, it can use the read command as described above to instruct the processing unit 133 to read and collect the user data in the valid section, and then, The host device 110 instructs the processing unit 133 to rewrite the collected valid user data to the empty physical page of the idle block or the active block using the write command as described above, so that these data areas containing invalid user data The block can be changed to an idle block, and after erasing, data storage space can be provided. The program described above is called Garbage Collection (GC).

Figure 7 is a schematic diagram of garbage collection according to some embodiments. Assume that a physical page of the data block includes four sections, and each section can store a piece of user data: after multiple accesses, the 0th section 711 of the physical page P1 in the data block 710 is stored and valid The user data of, the rest stores invalid user data. The first section 733 of the physical page P2 in the data block 730 stores valid user data, and the rest stores invalid user data. The second and third sections 755 and 757 of the physical page P3 in the data block 750 store valid user data, and the rest store invalid user data. In order to collect and store valid user data in the physical pages P1 to P3 and store them in the new physical page P4 in the physical block 770, a garbage collection process may be performed, including a series of read and write commands.

In addition, due to a certain number of erasures (for example, 500 times, 1000 times, 5000 times, etc.), the physical block in the storage unit 139 is classified as a bad block due to poor data retention (Data Retention) capability No longer use. In order to extend the service life of physical blocks, the main device 110 continuously monitors the number of erasures of each physical block. When the number of erasures of a data block exceeds the erasure threshold, the main device 110 may use the read command as described above to instruct the processing unit 133 to read the user data in this data block (source block). Then, the main device 110 selects an idle block with the least number of erasures as the destination block, and uses the write command as described above to instruct the processing unit 133 to write the read user data before writing to the selected destination block Available entity pages in. The procedure described above is called Wear Leveling. Figure 8 is a schematic diagram of the average loss according to some embodiments. Suppose that the number of erasures of data block 810 has exceeded the erasure threshold, and the number of erasures of idle block 830 is the least of all physical blocks in the output channel: the master device 110 starts to wear out the average and divides the data block The user data of the physical pages P5 to P6 in 810 is moved to the physical pages P7 to P8 in the idle block 830, where the average wearout procedure includes a series of read and write commands.

In addition, the host device 110 can record the number of readings of each data block and use the number of readings as a condition for starting the wear-out average program. For example, in a month, the data block 810 has the lowest number of reads and the number of erasures does not exceed the erasure threshold, the main device 110 may select all idle blocks or the highest value among all idle blocks of the same input/output channel The idle block of the erase count, for example, the idle block 830 is used as the destination block, and the data block 810 is used as the source block, and the wear-average process is started to use the user data (or cold data) of the data block 810 ) Moved to the idle block 830, wherein the wear-out average process includes a series of read and write commands.

However, using the read and write commands as described above to complete the garbage collection or wear-out averaging process will cause the queue to consume a lot of space to store a series of read and write commands and completion elements, and the data buffer 120 also needs to be consumed A large amount of bandwidth transmits the data read from the storage unit 139 and the data to be written to the storage unit 139, and consumes a large amount of space to store the data read from the storage unit 139. In addition, the main device 110 and the processing unit 133 also need to consume a large amount of computing resources to process the series of read and write commands, and this will make the open channel SSD 130 unable to maintain proper computing resources to respond to the data of the main device 110 in time The access command causes the system performance of the open channel SSD 130 to be low.

In order to solve the defects of the above-mentioned embodiments, an embodiment of the present invention provides a method for internally moving data in a flash memory. This method for internally moving data is suitable for a system where the physical storage comparison table is maintained by the main device 110, for example: open channel Solid State Drive System 100. FIG. 9 is a flowchart of a method for internally moving data in a flash memory according to an embodiment of the present invention. The main device 110 may periodically monitor the usage status of each input/output channel, for example, the number of available idle blocks, the number of erases or reads of each physical block, and so on. When the main device 110 detects that the usage status of an input/output channel in the open channel SSD 130 satisfies the conditions for data transfer, an internal movement command is generated and written to the submission queue 510 (step S9110), It is used to instruct the open channel SSD 130 to move the user data of the source block in a specific input and output channel to the target block in the same input and output channel, where the condition for data transfer may be that the number of idle blocks is lower than The idle threshold or the number of erasing or reading of the data block (source block) is higher than the erasing threshold or reading threshold, respectively. In addition, it is better to move only valid user data to the destination block, but for higher execution efficiency or when most of the user data are valid, all user data can be moved to the destination block.

After writing the internal transfer command to the delivery queue 510, the host device 110 issues a delivery doorbell to the processing unit 133 (step S1120) to notify the processing unit 133 that information about a data access command has been written in the delivery queue 510. After the processing unit 133 receives the doorbell for delivery (step S1310), it reads the internal transfer command from the delivery queue 510 (step S9310), and instructs the flash controller 135 to drive the access interface 137 in the specific input and output channel in response to the internal transfer command A copy back procedure is initiated between the source block and the destination block of (Step S9320). Although in the most ideal case, the earliest arriving data access command read by the processing unit 133 in step S9310 is an internal transfer command, but when there are other earlier arriving data access commands in the submission queue 510, the process The unit 133 will take a while to read and execute the data access commands that arrive earlier, and then read and execute the internal move command in step S9310. Although the embodiment of the present invention does not show the reading and execution of these earlier data access commands in FIG. 6, the present invention is not so limited. After the processing unit 133 completes the internal transfer operation, the processing unit 133 writes the completion element to the completion queue 530 (step S9330) to notify the host device 110 that the corresponding internal transfer command has been completed. In step S1130, the host device 110 can execute an interrupt service process (ISR, Interrupt Service Routine) to read the completed elements in the completion queue 530, and update the physical storage comparison table in response to the executed internal transfer operation. For example, the previously associated physical address (that is, the source block) of a logical block address in the physical storage comparison table is updated to a new physical address (that is, the destination block). Although in the most ideal case, the earliest arrival confirmation message read by the processing unit 133 in step S1130 corresponds to the internal move command, but when there are other earlier arrival confirmation messages in the completion queue 530, the processing unit 133 will It takes a while to read these earlier arrival confirmation messages and perform corresponding processing, and then reads the confirmation message corresponding to the internal move command in step S1130, and accordingly updates the physical storage comparison table. Although the embodiment of the present invention does not show the reading and corresponding processing of these earlier arrival confirmation messages in FIG. 6, the present invention is not so limited. In another embodiment, the main device 110 updates the physical storage comparison table before step S9110 or step S9110, instead of updating the physical storage comparison table after step S1130 or step S1130. In another embodiment, the main device 110 further determines whether the destination block is filled with user data and writes end-of-block information in step S1130. If it is, the physical storage comparison table is updated. If it is not, it is not. Update the physical storage comparison table.

The internal move command can be defined using a structured format. FIG. 10 is a data format diagram of an internal move command according to an embodiment of the present invention. The internal move command can be a 64-byte command. The 0th byte of the 0th double word of the internal move command 1000 records an opcode 1010 to notify the open channel solid state drive 130 that this is an internal move command. The 2nd to 3rd bytes of the 0th double word of the internal move command 1000 record the command identification code 1030. This command identification code 1030 is preferably generated sequentially, as the basis for the internal move command 1000 to identify, and also used to complete A corresponding completed element in the queue 530 is associated with the internal move command 1000. The internal transfer command 1000 uses the segment as the basic unit to instruct the open channel solid state hard disk 130 to perform the data transfer operation of a specific input and output channel, but it is not limited to this.

The 0th to 5th bits of the 12th double word of the internal move command 1000 record the number of moved segments 1080, the maximum value is 64. Therefore, an internal move command 1000 can instruct the open channel SSD 130 to move in the data move operation User data for up to 64 sectors in specific input and output channels.

The 10th to 11th double words of the internal transfer command 1000 record physical sector information 1070. If the physical address of the physical block is represented by 32 bits, and the value of the number of moving blocks 1080 is 1, then the 10th double word of the internal moving command 1000 records the user data stored in the block address of the source block ( Source address), the 11th double-word record user data is stored in the segment address of the destination block (destination address). By copying the write-back procedure, the processing unit 133 can program the user data of the source address to the destination address.

If the value of the number of moving segments 1080 is greater than 1, or the physical address of the physical block is represented by 64 bits, the physical segment information 1070 records the memory address of the data buffer 120. At this time, the source address and the destination bit The addresses are stored in the data buffer 120 in pairs. In step S9310, the processing unit 133 reads the internal transfer command 1000 from the submission queue 510 and obtains the paired source address and the source address from the data buffer 120 according to the record of the physical segment information 1070 and the value of the transfer segment number 1080 For the destination address, by copying and writing back the program, the processing unit 133 can program multiple user data of multiple source addresses to multiple specified destination addresses.

In another embodiment, the 6th to 7th double words of the internal move command 1000 record the main memory address 1050 with a physical region page entry (PRP) or a Scatter Gather List (SGL). And the 8th to 9th double words of the internal move command 1000 record the extended memory address 1060 in the physical area page record or the debris collection list. When the value of the moving segment number 1080 is greater than 1, the physical segment information 1070 can record the first source address, and the main memory address 1050 can record the first destination address. In another embodiment, the main memory address 1050 can record the first source address, and the extended memory address 1060 can record the first destination address. In another embodiment, the main memory address 1050 can record the first paired source address and destination address. When the memory space covered by the main memory address 1050 cannot record all paired source addresses and For the destination address, the extended memory address 1060 can record the remaining paired source and destination addresses.

The 24-25th bit of the internal move command 1000 records the write mode (M1) 1020, and the 26-27th bit records the read mode (M2) 1040 of the 12th double word. The write mode and the read mode can each include two states, for example: preset mode and SLC mode. When it indicates the SLC mode, the processing unit 133 instructs the flash controller 135 to read or write data of one page in the SLC mode through the drive access interface 137. When it is indicated as the preset mode, the processing unit 133 instructs the flash controller 135 to read or write data of one page in the preset mode through the drive access interface 137. The preset mode takes TLC as an example. This page can be an MSB page, a CSB page, or an LSB page. In other embodiments, the write mode may include four states, for example: SLC mode; MLC mode; TLC mode; and QLC mode. In addition, the number of write modes is preferably related to the programming method of the storage unit 139. For example, the storage unit 139 is a QLC and adopts a 3-pass programming method. The first-stage programming only writes to the MSB page, and the second Segment programming and then writing to CSB page and LSB page, the third segment programming and then writing to TSB page, the writing mode can include three modes, including: SLC mode, TLC mode and QLC mode (default mode). When it indicates the QLC mode, the processing unit 133 instructs the flash controller 135 to request a specific I/O channel to write the user data of the MSB page, CSB page, LSB page or TSB page to each memory unit through the driver access interface 137 . The above settings can also be applied to the reading mode. It should be noted that the setting values of the reading mode and the writing mode may be different. For example, the reading mode is the SLC mode but the writing mode is the default mode. Assuming that the storage unit 139 is QLC, the host device 110 can output multiple internal transfer commands 1000 to read 4 user data from the source address of the source block in SLC mode, and sequentially program the QLC mode to the destination area The destination address of the block.

Figure 11 is the data format diagram of the completed component. The completion element 1100 may be a 16-byte message. The 0 to 1 byte of the third double word of the completed component 1100 records the command identification code 1130, and its content should be the same as the command identification code 1030 of the internal move command 1000 to allow the completed device 1100 to be associated with a specific internal move Command 1000. The 0 to 1 double-word storage execution reply table 1110 of the completion element 1100 is used to record the access result of each user data. The 17th to 31st bit record status field 1120 of the third double word of the completion element 1100 is used to record the execution result of the internal transfer command 1000.

Before step S9110, the system of the main device 110 may store multiple usage records, and each record stores information on the usage status of a physical block of the input and output channels. After each open channel SSD 130 performs data access operations (eg, erase, read, write, internal transfer, etc.), the main device 110 can update the usage status information in the corresponding usage record and determine whether Meet the data movement conditions of the corresponding input and output channels. For example, the number of idle blocks of the corresponding I/O channel is decreased by 1, the number of erases of a physical block of the corresponding I/O channel is increased by 1, or the number of reads of a data block of the corresponding I/O channel is increased by 1. Wait. In some embodiments, when the usage record indicates that the number of idle blocks of the corresponding input/output channel is lower than the idle threshold, it means that the number of idle blocks is too small, and a garbage collection process needs to be started to increase the number of idle blocks. In some embodiments, when the usage record indicates that the number of erasures of a physical block of the corresponding input/output channel is higher than the erasure threshold, the main device starts the wear-out averaging process to prevent user data from encountering data storage problems.

During the process of reading or writing data, you may encounter a failure to read or write. When the above situation is encountered, the status field 1120 of the completed component 1100 will be set to "1", and the bit corresponding to the user data that fails to read or write to the execution reply table will also be set to "1" ". At this time, the main device 110 must first determine whether the failure is a read failure or a write failure. If it is a read failure, an error management process such as RAID is started to repair the user data at the source address; if it is a write If it fails, a new destination address is determined for the user data.

As can be seen from the above description, if a failure occurs during the internal transfer process, the main device 110 needs to spend a lot of time and computing resources to determine the cause and correct the error. In order to solve the above-mentioned defects, in other embodiments, the main device 110 does not determine a destination address for each source address user data, but allows the open channel SSD 130 to determine, after which, the open channel SSD The hard disk 130 uploads the determined destination address to the memory address of the data buffer 120 designated by the host device 110 according to the instruction of the internal move command 1000, for example, the main memory address 1050, the extended memory address 1060, or the physical area The memory address specified by segment information 1070. Finally, the completion device 1100 notifies the host device 110 that the destination address has been uploaded. After that, the host device 110 can update the physical storage comparison table according to the destination address.

When user data of multiple sectors needs to be moved, in detail, before step S9110, the host device 110 can store the source addresses of multiple pieces of user data to the data buffer 120, and place the source addresses in the data The memory address of the buffer 120 is stored in one of the main memory address 1050, the extended memory address 1060, or the physical segment information 1070 in the internal move command 1000, the main memory address 1050, the extended memory address 1060, or the physical segment The other of the information 1070 is the destination address for the open channel SSD 130 to upload user data. In step S9110, the internal transfer command 1000 is written to the delivery queue 510. The source address can be represented by logical unit number, data plane number, physical block number, physical page number, and section number. In step S9310, the processing unit 133 reads and determines the operation code 1010 of the internal transfer command 1000, and then reads the number of transfer sections 1080 of the internal transfer command 1000, the main memory address 1050, the extended memory address 1060, or the physical area The value of the segment information 1070, and then the memory address of the data buffer 120 to obtain the source address of multiple pieces of user data. Next, in step S9320, the processing unit 133 determines a destination address for each user data, for example, selects an idle block with the number of erasures as the destination block, and instructs the flash controller 135 to access the interface 137 through the driver The copy-write-back procedure is executed on the source block and the destination block of a specific input/output channel. When writing to any destination address fails, the processing unit 133 programs the user data to the next page (the first section); or directly writes all the remaining pages of this physical character line to dummy data (Dummy Data), and then program the user data to the MSB page of the next physical character line (the first section), or re-instruct the flash controller 135 to request a specific input/output channel through the driver access interface 137 The source block and the destination block of the program perform a copy-back process to move the user data to the MSB page of the next physical character line, or program the user data to another destination block. In step S9330, after the copy-back procedure is successfully executed, the processing unit 133 can store the destination addresses of all user data in the data buffer 120, and write the completion element 1100 to the completion queue 530. In step S1130, after receiving the completed component 1100, the host device 110 reads all the destinations from the data buffer 120 according to the values of the number of moved segments 1080, the main memory address 1050, the extended memory address 1060, or the physical segment information 1070 Address and update the physical storage comparison table accordingly.

When the user data of only one sector needs to be moved, in detail, in step S9110, the host device 110 may store a source address to the physical sector information 1070 in the internal migration command 1000, and set the main memory address 1050 The value is used for the open channel SSD 130 to upload the user data destination address, and write the internal transfer command 1000 to the delivery queue 510. In step S9310, when the processing unit 133 reads the source address of the physical sector information 1070 in the internal move command 1000, it determines a destination address for the source address and instructs the flash controller 135 to access the interface 137 through the driver Require specific I/O channels to execute copy-back writing procedures. In step S9330, when the copy-and-write-back procedure is successfully executed, the processing unit 133 uploads the destination address of the user data to the memory address writing completion element 1100 to the completion queue 530 corresponding to the main memory address 1050. In step S1130, the host device 110 reads the completed element 1100 and reads the destination address from the data buffer 120 according to the value of the main memory address 1050, and accordingly updates the physical storage comparison table.

FIG. 12 is a schematic diagram of the internal moving operation of the waste collection process according to an embodiment of the present invention. The host device 110 can write an internal move command to the delivery queue 510. The internal move command includes multiple sets of physical locations of the source and destination sectors. The first group includes the physical location of the source segment 711 and the destination segment 771, the second group includes the physical location of the source segment 733 and the destination segment 773, and the third group includes the physical location of the source segment 755 and the destination segment 775 , And the fourth group includes the physical locations of the source section 757 and the destination section 777. Next, the flash controller 135 drives the access sub-interface 1210 to execute the copy-back procedure. The access sub-interface 1210 instructs the direct data access circuit (DMA-Direct Memory Access Circuit) 1230 to read the data of the source sections 711, 733, 755 and 757, collect and store them in the register 1250, and then instruct the direct data access circuit 1230 Write the data of an entire physical page in the register 1250 to the physical page P4 (including the sections 771, 773, 775, and 777) in the physical block 770.

FIG. 13 is a schematic diagram of the internal moving operation of the wear-out average procedure according to an embodiment of the present invention. The host device 110 can write an internal move command to the delivery queue 510. The internal move command includes multiple sets of physical locations of the source and destination sectors. For example, the first group includes the first source section in the physical page P5 of the physical block 810 and the physical location of the first destination section in the physical page P7 of the physical block 830, and the second group includes the physical page P5 of the physical block 810 The physical location of the second source segment in the second source segment and the physical location of the second destination segment in the physical page P7 of the physical block 830, and so on. Next, the flash controller 135 drives the access sub-interface 1310 to execute the copy-back procedure. The access sub-interface 1310 instructs the direct data access circuit 1330 to read the data of the eight source sections in the physical pages P5 and P6, and stores it in the register 1350, and then instructs the direct data access circuit 1330 to transfer the two entities in the register 1350 The data of the page is written into the physical pages P7 and P8 in the physical block 830.

In addition, during the execution of the copy-back program, user data does not need to be uploaded to the data buffer 120. The flash controller 135 outputs a copy-back read command to the source block of the storage unit 139, so that the user data read from the source address is temporarily stored in the register (cache register or page register) of the storage unit 139 in. Next, the flash controller 135 outputs a copy-write programming command to the destination block of the storage unit 139, so that the user data temporarily stored in the register 1250 is programmed to the destination address. Since user data does not need to be uploaded to the data buffer 120, the time for user data to be transferred from the source block to the data buffer 120 and from the data buffer 120 to the destination block can be saved, so the openness can be increased The system performance of the channel SSD 130 achieves the purpose of the present invention.

Although the elements described above are included in Figures 1 to 3, it is not excluded that more other additional elements are used without violating the spirit of the invention, and a better technical effect has been achieved. In addition, although the flowcharts in Figures 6 and 9 are executed in the specified order, without violating the spirit of the invention, those skilled in the art can modify the order between these steps on the premise of achieving the same effect. Therefore, the present invention is not limited to using only the order described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers obvious modifications and similar settings for those skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest way to include all obvious modifications and similar settings.

100‧‧‧Main device

120‧‧‧Data buffer

130‧‧‧ Solid State Drive

133‧‧‧ processing unit

135‧‧‧Flash controller

137‧‧‧Access interface

137_0~137_j, 1210, 1310 ‧‧‧ accessor interface

139‧‧‧storage unit

139_0_0~139_j_i‧‧‧storage subunit

310_0‧‧‧Data cable

320_0_0~320_0_i‧‧‧Chip enable control signal

410, 430, 450, 470

410_0~410_m, 430_0~430_m, 450_0~450_m, 470_0~470_m‧‧‧‧plane

490_0~490_n‧‧‧Super Page

P#0~p#(n)‧‧‧Entity page

510, 530‧‧‧ queue

S1110~S1360, S9110~S9120, S9310~S9330

P1~P4, P5~P8 ‧‧‧ physical page

Sections 711, 733, 755, 757‧‧‧

810, 830‧‧‧ physical block

1010‧‧‧Operation code

1020‧‧‧Write mode

1030, 1130‧‧‧ command identification code

1040‧‧‧Namespace ID

1050, 1060‧‧‧ memory address

1070‧‧‧Physical section information

1080‧‧‧ Number of moving sections

1100‧‧‧Complete components

1110‧‧‧Physical Area Page Record

1120‧‧‧ State flag

1230, 1330‧‧‧ direct data access circuit

1250, 1350‧‧‧‧ register

FIG. 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

FIG. 2 is a block diagram of an access interface and a storage unit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of connection between an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention.

Figure 4 is a schematic diagram of a storage unit.

Figure 5 is a schematic diagram of the command queue.

Figure 6 is a flow chart of the execution steps of the data access command.

Figure 7 is a schematic diagram of garbage collection according to some embodiments.

Figure 8 is a schematic diagram of the average loss according to some embodiments.

FIG. 9 is a flowchart of a method for internally moving data in a flash memory according to an embodiment of the present invention.

FIG. 10 is a data format diagram of an internal move command according to an embodiment of the present invention.

Figure 11 is the data format diagram of the completed component.

FIG. 12 is a schematic diagram of the internal moving operation of the waste collection process according to an embodiment of the present invention.

FIG. 13 is a schematic diagram of the internal moving operation of the wear-out average procedure according to an embodiment of the present invention.

111‧‧‧Main device

133‧‧‧ processing unit

S1120~S1140, S1310, S1350~S1360, S9110~S9120, S9310~S9330‧‧‧

Claims (12)

A method for internally transferring data from flash memory, executed by a processing unit in a solid state drive, including: Receive an internal move command, instructing to move the data of a source location of an I/O channel to a new location of the aforementioned I/O channel; Executing a copy-write-back program of the I/O channel for moving the data of the source location of the I/O channel to a destination location of the I/O channel; and According to the execution result of the copy-and-write program, a completed component is returned to the host device. The method for internally transferring data of a flash memory according to claim 1, wherein the destination location is determined by the host, and the internal migration command includes information of the source location and the destination location. The method for internally transferring data of the flash memory as described in claim 1 includes: Before the above copy-and-write program is executed, determine the above-mentioned destination location; and After the copy-and-write-back procedure is successfully executed, the completion element is used to notify the host device of the destination location information. The method for internally transferring data in a flash memory according to any one of claims 1 to 3, wherein the master device continuously monitors a use state of the input/output channel for deciding to send the internal transfer command to the solid state The time of the hard drive. The method for internally transferring data of the flash memory according to claim 4, wherein the usage state includes a number of available idle blocks, the number of erasing or reading times of each physical block. The method for internally transferring data of a flash memory according to any one of claims 1 to 3, wherein the internal transfer command includes information of a read mode and a write mode, and the read mode indicates a first The preset mode or a first single-layer unit mode, and the above-mentioned write mode indicate a second preset mode or a second single-layer unit mode. The method for internally transferring data of the flash memory as described in claim 6 includes: Reading the data of the source position of the I/O channel in the first preset mode or the first single-layer unit mode according to the internal movement command; and According to the internal transfer command, write data to the destination position of the I/O channel in the second preset mode or the second single-layer unit mode. A data internal moving device of flash memory, including: A flash controller coupled to a storage unit, wherein the storage unit includes an input and output channel; and A processing unit, coupled to the flash controller, for receiving an internal transfer command from a host device, instructing to move the data of a source position of the I/O channel to a new position of the I/O channel; indicating the fast The flash controller executes a copy-and-write-back procedure of the I/O channel to move the data of the source-position of the input-output channel to a destination-position of the input-output channel; and according to the execution result of the copy-and-write-back procedure Reply a completed component to the above master device. The internal data migration device for flash memory according to claim 8, wherein the destination location is determined by the host, and the internal migration command includes information of the source location and the destination location. The internal data transfer device of the flash memory according to claim 8, wherein the processing unit determines the destination location before the copy-write-back program is executed; and after the copy-write-back program is successfully executed, uses the above The completion component notifies the above-mentioned host device of the information about the above-mentioned destination location. The internal data transfer device for flash memory according to any one of claims 8 to 10, wherein the internal transfer command includes information of a read mode and a write mode, and the read mode indicates a first The preset mode or a first single-layer unit mode, and the above-mentioned write mode indicate a second preset mode or a second single-layer unit mode. The internal data transfer device for flash memory according to claim 11, wherein the processing unit instructs the flash controller to use the first preset mode or the first single-layer unit mode according to the internal transfer command Reading the data of the source location of the I/O channel; and instructing the flash controller to write data to the I/O channel in the second preset mode or the second single-layer unit mode according to the internal move command The above destination location.

Images