TWI679535B - Methods for internal data movement of a flash memory and apparatuses using the same - Google Patents

Abstract

An embodiment of the present invention provides a method for internal data transfer of flash memory, which is executed by a host device and includes the following steps: when a use state of an input / output channel in a solid-state hard drive is detected to satisfy a condition, an internal transfer command is generated; and Provide an internal transfer command to instruct the solid-state hard disk to perform internal data transfer operations in the input and output channels.

Description

Method for internally transferring data of flash memory and device using same

The invention relates to a flash memory, in particular to a method for internally transferring data in the flash memory and a device using the method.

Flash memory devices are generally divided into NOR flash devices and NAND flash devices. The NOR flash device is a random access device. The host device can provide an arbitrary address for accessing the NOR flash device on the address pin, and it can be obtained from the data pin of the NOR flash device and stored in real time. User data at that address. In contrast, NAND flash devices are not random access, but serial access. A NAND flash device cannot access any random address like a NOR flash device. Instead, the master device needs to write serial bytes to the NAND flash device to define the request command. The type (for example, read, write, erase, etc.), and the address on this command. The address can point to a page (the smallest data block of a write operation in flash memory) or a block (the smallest data block of an erase operation in flash memory). In fact, NAND flash devices usually read or write complete pages of data from memory cells. When a whole page of data is read from the array to the buffer in the device, the content of Clock Out is sequentially knocked out by using the Strobe Signal, so that the main unit can be byte-by-byte or word-by-byte. Words to access data.

The Open-Channel Solid State Disk (Open-Channel Solid State Disk) system includes an open-channel solid state disk (device side) and the main device. A Flash Translation Layer (FTL) is not implemented on the device side. The device implements a flash memory translation layer. Unlike traditional solid state drives, open channel SSDs let the host device know the operating parameters inside the solid state drive and allow the host device to operate the open channel SSDs based on the operating parameters, that is, to manage data. However, current open channel solid state drives only contain three basic access commands: erase; read; and write. When the host device executes a series of read and write access procedures, such as garbage collection (GC, Garbage Collection), wear leveling (Wear Leveling), etc., data needs to be transmitted through the open channel solid-state hard disk access interface , Which consumes a lot of bandwidth of the access interface.

Therefore, a method for internally transferring data in a flash memory and a device using the method are needed to solve the problems described above.

An embodiment of the present invention provides a method for internal data transfer of flash memory, which is executed by a host device and includes the following steps: when a use state of an input / output channel in a solid-state hard drive is detected to satisfy a condition, an internal transfer command is generated; and Provide an internal transfer command to instruct the solid-state hard disk to perform internal data transfer operations in the input and output channels.

An embodiment of the present invention provides a data internal moving device of a flash memory, including a main device. When the host device detects that the use status of the input / output channel in the solid-state hard disk meets the conditions, it generates an internal move command; and provides an internal move command to instruct the solid-state hard disk to perform an internal data move operation in the input / output channel.

An embodiment of the present invention further provides a flash memory data internal moving method, which is executed by a processing unit in a solid state hard disk and includes the following steps: obtaining an internal moving command generated by the main device, wherein the internal moving command indicates the solid state hard disk; Perform internal data transfer operations in the input and output channels, including the memory address that points to the first data transfer record in the data buffer; obtain multiple data transfer records from the memory address in the data buffer, where data transfer Each record contains the source location; determines the destination location in the input / output channel for each source location; instructs the flash controller to request the input / output channel to perform a copy-write procedure to copy each source location in the input / output channel. The user data is moved to the determined destination location; and the determined destination location is returned to the host device for each source location.

An embodiment of the present invention further provides a flash internal memory data moving device, which includes a flash controller and a processing unit. The processing unit is coupled to the flash controller and obtains an internal transfer command generated by the main device. The internal transfer command instructs the solid-state hard disk to perform an internal data transfer operation in the input / output channel, including the first data pointed to the data buffer. Memory address of the transfer record; multiple data transfer records are obtained starting from the memory address in the data buffer, where each of the data transfer records includes the source location; for each source location, the purpose of the input and output channels is determined Local location; instruct the flash controller to request the input and output channels to perform a copy-write procedure to move the user data of each source location in the input and output channels to the determined destination location; and reply to the destination location of each source location to The main unit.

110‧‧‧Master

120‧‧‧Data Buffer

130‧‧‧Solid State Drive

133‧‧‧Processing unit

135‧‧‧Flash Controller

137‧‧‧Access interface

137_0 ~ 137_ j ‧‧‧ accessor interface

139‧‧‧Storage unit

139_0_0 ~ 139_ j _ i ‧‧‧Storage subunit

310_0‧‧‧Data Line

320_0_0 ~ 320_0_ i ‧‧‧ Chip enable control signal

410, 430, 450, 470‧‧‧ I / O channels

410_0 ~ 410_ m , 430_0 ~ 430_ m , 450_0 ~ 450_ m , 470_0 ~ 470_ m ‧‧‧ data plane

490_0 ~ 490_ n ‧‧‧ Hyper Page

P # 0 ~ p # ( n ) ‧‧‧physical page

510‧‧‧Submission queue

530‧‧‧Complete queue

S1110 ~ S1360‧‧‧Method steps

710, 730, 750, 770‧‧‧ physical blocks

P1 ~ P4‧‧‧physical page

Sections 711, 733, 755, 757‧‧‧

810, 830‧‧‧ physical block

P5 ~ P8‧‧‧physical page

S9110 ~ S9120, S9310 ~ S9330‧‧‧Method steps

1000‧‧‧ Internal Move Order

1010‧‧‧opcode

1020‧‧‧write mode

1030‧‧‧Command ID

1040‧‧‧namespace identifier

1050‧‧‧Main memory address

1060‧‧‧ extended memory address

1070‧‧‧ Entity Section Information

1080‧‧‧ Number of moving sections

1100‧‧‧Complete components

1110‧‧‧ physical area page record

1120‧‧‧Status Flag

1130‧‧‧Command ID

1210‧‧‧Accessor Interface

1230‧‧‧Direct Data Access Circuit

1250‧‧‧Register

1310‧‧‧Accessor Interface

1330‧‧‧Direct Data Access Circuit

1350‧‧‧Register

FIG. 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

FIG. 2 is a block diagram of an access interface and a storage unit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of connection between an accessor interface and a plurality of storage subunits according to an embodiment of the present invention.

Figure 4 is a schematic diagram of a storage unit.

Figure 5 is a schematic diagram of the command queue.

FIG. 6 is a flowchart of the execution steps of the data access command.

FIG. 7 is a schematic diagram of garbage recycling according to some embodiments.

FIG. 8 is a schematic diagram of wear loss averaging according to some embodiments.

FIG. 9 is a flowchart of a method for internally transferring data in a flash memory according to an embodiment of the present invention.

FIG. 10 is a data format diagram of an internal move command according to an embodiment of the present invention.

Figure 11 is a data format diagram of the completed component.

FIG. 12 is a schematic diagram of an internal moving operation of a waste collection program according to an embodiment of the present invention.

FIG. 13 is a schematic diagram of an internal moving operation according to a wear averaging program according to an embodiment of the present invention.

The following description is a preferred implementation of the invention. The purpose is to describe the basic spirit of the invention, but not to limit the invention. The actual summary must refer to the scope of the claims that follow.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, job processing, elements and / or components, but do not exclude Add more technical features, values, method steps, job processing, components, components, or any combination of the above.

The use of words such as "first", "second", and "third" in claims is used to modify elements in the claims, and is not intended to indicate that there is a priority order, a prior relationship, or an element between claims Preceding another element, or chronological order when performing a method step, is only used to distinguish elements with the same name.

FIG. 1 is a schematic structural diagram of an open channel solid state hard disk system 100 according to an embodiment of the present invention. The architecture of the open channel solid state disk system 100 includes a main device 110, a data buffer (Data Buffer) 120, and an open channel solid state disk (SSD) 130. When the main device 111 operates, it can establish a queue (Queue), a physical storage mapping table (also known as an L2P Logical-to-Physical table), and a usage record according to its needs. This system architecture can be implemented in electronic products such as personal computers, laptop PCs, tablets, mobile phones, digital cameras, and digital cameras. The data buffer 120, the queue, the physical storage comparison table, and the usage record can be implemented in a specific area in a random access memory (RAM, Random Access Memory). The host device 110 communicates with the open channel solid state hard disk 130 through an open channel solid state hard disk fast non-volatile memory (NVMe, Non-Volatile Memory express) interface. The host device 110 may be implemented in a variety of ways, such as using general-purpose hardware (e.g., a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other computing capabilities Device), and when the instructions (Instructions), macro code (Macrocode) or microcode (Microcode) is executed, it provides the functions described later. The host device 110 may include an arithmetic logic unit (ALU) and a shifter (Bit Shifter). The operation logic unit is responsible for performing Bolling operations (such as AND, OR, NOT, NAND, NOR, XOR, XNOR, etc.) or mathematical operations (such as addition, subtraction, multiplication, division, etc.), while the shifter is responsible for displacement operations and bit rotation . Open channel SSD NVMe specifications, such as version 1.2, which was released in April 2016. It supports several I / O channels. Each I / O channel is connected to a logical unit number LUNs, Logical Unit Numbers. Corresponding to a plurality of storage sub-units in the storage unit 139 respectively. In the open channel SSD NVMe specification, the main device 110 integrates a flash memory translation layer (FTL, Flash Translation Layer) originally implemented in the device to optimize the load. The traditional flash memory translation layer maps logical block addresses (LBAs, Logical Block Addresses) recognized by the host device or the file system to the physical addresses (also called logical-to-physical mapping) of the storage unit 139. In the open channel SSD NVMe specification, the main device 110 may instruct the open channel solid state hard disk 130 to store user data to a physical address in the storage unit 139. Therefore, the maintenance of the physical storage comparison table is the responsibility of the main device 110 and Record which physical address of the user data of each logical block address is actually stored in the storage unit 139.

The open channel solid state hard disk 130 includes a processing unit 133. The processing unit 133 may communicate with the host device 110 by using an open channel SSD NVMe communication protocol to receive a data access command including a physical address, and instruct the flash controller 135 to perform erasing, reading or writing according to the data access command. Into. It should be noted here that the processing unit 133 may use a lightweight general purpose processor (Lightweight General-Purpose Processor).

The open channel solid state hard disk 130 further includes a flash controller 135, an access interface 137, and a storage unit 139, and the flash controller 135 communicates with the storage unit 139 through the access interface 137. In detail, a double data rate can be used (Double Data Rate, DDR) communication protocol, for example, Open NAND Flash Interface (ONFI), Double Data Rate Switch (DDR Toggle) or other interfaces. The flash controller 135 of the open channel solid state hard disk 130 writes user data to the specified address (destination address) in the storage unit 139 through the access interface 137, and from the specified address (source bit) in the storage unit 139 Address) to read user data. The access interface 137 uses several electronic signals to coordinate data and command transfer between the flash controller 135 and the storage unit 139, including data lines, clock signals, and control signals. The data line can be used to transmit command, address, read and write data; the control signal line can be used to pass Chip Enable (CE), Address Latch Enable (ALE), command extraction Control signals such as Command Latch Enable (CLE) and Write Enable (WE). The processing unit 133 and the flash controller 135 may exist separately or integrated in the same chip.

When the system is booted (System Boot), the main device 110 obtains the operating parameters required for controlling the operation of the open channel solid state hard disk 130 from the open channel solid state hard disk 130, such as the number of blocks, the number of bad blocks, and the hysteresis. Time (latency), total number of input and output channels, etc.

The storage unit 139 may include multiple storage sub-units, and each storage sub-unit communicates with the flash controller 135 using an associated access sub-interface. One or more storage sub-units may be packaged in a die. FIG. 2 is a block diagram of an access interface and a storage unit according to an embodiment of the present invention. Solid State Drive open channel 130 may include j +1 th sub-access interface 137_0 to 137_ j, each of the sub-access interface connector i +1 th storage subunit. The access sub-interface and the storage sub-units connected thereafter can be collectively referred to as input-output channels, and can be identified by the logical unit number. In other words, i + 1 storage subunits share an accessor interface. For example, when the open channel solid state hard disk 130 includes four inputs and outputs ( j = 3 ) and each input and output is connected to four storage units ( i = 3), the open channel solid state hard disk 130 has a total of 16 storage subunits 139_0_0 To 139_ j _ i . The flash controller 135 can drive one of the sub-interfaces 137_0 to 137_ j to read data from a designated storage sub-unit. Each storage sub-unit has an independent chip enable (CE) control signal. In other words, when data is read from a specified storage sub-unit, the associated access sub-interface needs to be driven to enable the chip enable control signal of the storage sub-unit. FIG. 3 is a schematic diagram illustrating a connection between an accessor interface and a plurality of storage subunits according to an embodiment of the present invention. Flash controller 135 may access through the use of separate sub-interface 137_0 wafer to enable control signal 320_0_0 wherein 320_0_ i selected from one of the storage sub-unit connected to 139_0_ i 139_0_0, followed, through the shared data line 310_0 Read data at the specified address of the selected storage subunit.

FIG. 4 is a schematic diagram of the storage unit 139. The storage unit 139 includes a plurality of data plane (Data Planes) 410_0 through 410_ m, 430_0 to 430_ m, 450_0 and 470_0 through 450_ m to 470_ m, each of the plurality of information data plane or a plane disposed in the logical unit number. The data planes 410_0 to 410_ m and the shared accessor interface are called input / output channels 410, and the data planes 430_0 to 430_ m and the shared accessor interface are called input / output channels 430, and the data planes 450_0 to 450_ m and shared access taking into sub-channels are called output interface 450, and data plane 470_0 to 470_ m and shared access sub-channels into output interface 470 referred to, wherein, m may be an integer power of 2 (e.g. 4, 8, 16, 32, etc.), I / O channels 410, 430, 450, and 470 can be identified by logical unit numbers. Each of the data planes 410_0 to 470_ m contains multiple physical blocks, each of which contains multiple pages (Pages) P # 0 to P # ( n ), each page contains multiple Sectors (for example, 4, 8, etc.), where n can be 767 or 1535, etc. Each page contains multiple NAND memory cells (Memory Cells), and NAND memory cells can be single-level cells (SLCs), multi-level cells (MLCs), three-level cells Cells (Triple-Level Cells, TLCs) or Quad-Level Cells (QLCs). In some embodiments, when each NAND memory cell is a single-layer cell and can record 2 states, the page P # 0 in the data plane 410_0 to 470_0 can virtually form a Super Page 490_0, a data plane Pages P # 1 from 410_0 to 470_0 can virtually form a superpage 490_1, and so on. In other embodiments, when each NAND memory cell is a multi-layer cell and can record 4 states, a physical character line may include page P # 0 (may be referred to as the least significant page, MSB, Most Significant Bit page), page P # 1 (may be called Least Significant Bit page, LSB), and so on. In still other embodiments, when each NAND memory cell is a three-layer cell and can record 8 states, a physical character line may include a page P # 0 (which may be referred to as the least significant page, MSB page ), Page P # 1 (could be called the Center Significant Bit page, CSB) and page P # 2 (could be called the most significant page, LSB page). When each NAND memory cell is a four-layer cell and can record 16 states, in addition to the MSB, CSB, and LSB pages, it also includes a TSB (can be referred to as a TSB, Top Significant Bit) page.

When the storage unit 139 operates, the page can be the smallest unit for data management or programming, for example, the size is 16KB. At this time, the physical address can be expressed as a page number. Or, the page can contain multiple sections, such as 4KB, and the area Segments can be the smallest unit of data management. At this time, the physical address can be expressed as the sector number of the page or the offset of the sector on the page. A block is the smallest unit of data erasure.

The physical blocks can be divided into active blocks, data blocks, and idle blocks according to their use status. The active block indicates a physical block that is writing data, that is, a physical block that has not been written with End of Block information. A data block is a physical block that has been written with end-of-block information, that is, no more user data is written. The idle block can be selected to become the active block. The idle block does not store any valid user data. Usually, after an idle block is selected, an erasing action is required to become an active block.

In some embodiments, the physical address transmitted by the host device 110 to the open channel solid state hard disk 130 may include information such as a logical unit number, a data plane number, a physical block number, a physical page number, and a section number, and is used to indicate that The user data read or written is located in a specific section of a specific entity page in a specific entity block in a specific data plane in a specific input / output channel. In some embodiments, column numbers are sometimes replaced with column numbers. In other embodiments, the physical address transmitted by the host device 110 to the open channel solid state hard disk 130 may include information such as a logical unit number, a data plane number, and a physical block number, and is used to indicate that a specific input / output channel is to be erased. A specific data block in a specific data plane of.

Figure 5 is a schematic diagram of the command queue. The queue 115 may include a Submission Queue 510 and a Completion Queue 530, which are respectively used to temporarily store a main device instruction and a Completion Element. Each of the submission queue 510 and the completion queue 530 contains a set of multiple entries. Each entry in the submitted queue 510 stores a master device command, such as an input / output command (hereinafter referred to as a data access command) or a management command, and each entry in the completed queue 530 is associated with a data access The completion element of the command or management command. This completion element functions like a confirmation message. The entries in the collection are stored in order. The basic principle of the operation of the set is to add an entry from the end position (which can be referred to as dequeuing), and to remove the entry from the start position (which can be referred to as dequeuing). That is, the first command or message added to the submission queue 510 or the completion queue 530 will also be the first to be removed. The host device 110 may write a data access command (eg, an erase, read, write command, etc.) to the submission queue 510, and the processing unit 133 reads (or is referred to as extraction) from the submission queue 510 Fetch) The earliest data access command arrives and executes. After the execution of the data access command is completed, the processing unit 133 writes the completion element to the completion queue 530, and the host device 110 can read or extract the completion element to determine the execution result of the data access command.

FIG. 6 is a flowchart of the execution steps of the data access command. The host device 110 generates and writes a data access command (for example, an erase, read, write command, etc.) to the submission queue 510 (step S1110), where the data access command includes information of a physical address, and, The physical address points to a specific block, page, or section address. Next, the main device 110 sends a Submission Doorbell to the processing unit 133 (step S1120) to notify the processing unit 133 of the submission queue The information of a data access command has been written in 510, and the value of the tail of the queue 510 is updated. After receiving the doorbell (step S1310), the processing unit 133 reads the (earliest) data access command from the submission queue 510 (step S1320), and instructs the flash controller 135 according to the data access command to complete The designated job (for example, erasing, data reading, writing, etc.) (step S1330). After the designated operation is completed, the processing unit 133 generates and writes a completion element to the completion queue 530 (step S1340) to notify the host device 110 of the execution status information of the operation corresponding to the specific data access command, and issues an interrupt to the host device ( Step S1350). After receiving the interruption (step S1130), the main device 110 reads the (earliest) completion element from the completion queue 530 (step S1130), and then issues a completion doorbell to the processing unit 133 (step S1140). After receiving the completion doorbell (S1360), the processing unit 133 updates the value of the queue head of the completed queue 530.

In steps S1120 and S1140, the main device 110 may set corresponding registers to send the doorbell to the processing unit 133 and end the doorbell.

One data access command can process multiple user data, for example: 64, the completion component can include 64-bit execution response table, each bit represents the execution result of each user data, for example: "0" indicates success, and "1" indicates failure. The data access command contains an opcode field to store the type of data access command (eg, erase, read, write, etc.). The completion component includes a status field to store the execution status (eg, success, failure, etc.) of the corresponding data access command. In addition, the processing unit 133 can execute the data access commands out of order or in the order of priority. Therefore, the data access command and the completion component both include a command identifier (Command Identifier), so that the main device 110 can Complete the component associated with a specific data access command.

For example, an idle block needs to be erased to become an active block before writing. The master device 110 can write an erase command to the submission queue 510 (step S1110) to instruct the open channel solid state hard disk 130 ( In detail, the processing unit 133) performs an erase operation for a specific idle block in a specific input / output channel. In response to the erase command, the processing unit 133 instructs the flash controller 135 to complete the erase operation specified in the storage unit 139 by driving the access interface 137 (step S1330). When the erasing operation is completed, the processing unit 133 writes a completion element to the completion queue 530 (step S1340) to notify the host device 110 that the corresponding erasing operation has been completed.

For example, the host device 110 may write a read command to the submission queue 510 (step S1110) to instruct the open channel solid state hard disk 130 to select a specific physical block in a specific physical block in a specific data plane in a specific input / output channel. The user page is read by (a specific section) of the physical page. The processing unit 133 instructs the flash controller 135 to read the user data from the physical address specified in the storage unit 139 through the drive access interface 137 in response to the read command, and stores the user data to the data specified by the read command Buffer 120 (step S1330). When the reading operation is completed, the processing unit 133 writes a completion element to the completion queue 530 (step S1340) to notify the host device 110 about the completion of the corresponding reading operation.

For example, the host device 110 may store the user data to be written in the data buffer 120, and store the write command in the submission queue 510 (step S1110) to instruct the open channel solid state hard disk 130 to write the user data. To a specific physical page (a specific section) in a specific active block in a specific data plane in a specific input / output channel, wherein the write command includes an address in the data buffer 120 that stores user data to be written Information. The processing unit 133 responds to a write command from Read the user data to be written at the specified address in the data buffer 120, and instruct the flash controller 135 to program the user data to the physical bit specified by the write command in the storage unit 139 through the drive access interface 137 Address (step S1330). When the writing operation is completed, the processing unit 133 writes a completion element to the completion queue 530 (step S1340) to notify the host device 110 about the completion of the corresponding writing operation.

After multiple accesses, a physical page may contain valid and invalid sections (also known as expired sections), where the valid section stores valid user data and the invalid section stores invalid (old) use Information. In some embodiments, when the main device 110 detects that the available space of the storage unit 139 is insufficient, the read command as described above may be used to instruct the processing unit 133 to read and collect user data in a valid section. Then, The host device 110 uses the write command as described above to instruct the processing unit 133 to rewrite the collected valid user data to the empty physical page of the idle block or active block, so that these data areas contain invalid user data The block can be changed into a free block, and after erasing, it can provide data storage space. The program described above is called Garbage Collection (GC).

FIG. 7 is a schematic diagram of garbage recycling according to some embodiments. Assume that a physical page of the data block includes four sections, and each section can store a piece of user data: After multiple accesses, the 0th section 711 of the physical page P1 in the data block 710 is stored valid User data for, the rest stores invalid user data. The first section 733 of the physical page P2 in the data block 730 stores valid user data, and the rest stores invalid user data. The second and third sections 755 and 757 of the physical page P3 in the data block 750 store effective User data, the rest stores invalid user data. In order to collect valid user data in the physical pages P1 to P3 and store them in the new physical page P4 in the physical block 770, a garbage collection process may be performed, including a series of read and write commands.

In addition, after a certain number of erasures (for example, 500 times, 1000 times, 5000 times, etc.), the physical blocks in the storage unit 139 will be listed as bad blocks due to poor data retention capabilities. No longer use. In order to extend the service life of the physical blocks, the main device 110 continuously monitors the erasure times of each physical block. When the number of erasures of a data block exceeds the erasure threshold, the main device 110 may instruct the processing unit 133 to read user data in this data block (source block) using the read command as described above. Next, the main device 110 selects an idle block with the least number of erasures as the destination block, and uses the write command as described above to instruct the processing unit 133 to write the previously read user data to the selected destination block. Page of available entities in. The procedure described above is called Wear Leveling. FIG. 8 is a schematic diagram of wear loss averaging according to some embodiments. Assume that the number of erasures of the data block 810 has exceeded the erasure threshold, and the number of erasures of the idle block 830 is the least of all physical blocks in this input / output channel: the main device 110 starts the wear average and divides the data blocks. The user data of the physical pages P5 to P6 in 810 are moved to the physical pages P7 to P8 in the idle block 830, wherein the wear average process includes a series of read and write commands.

In addition, the host device 110 can record the number of readings of each data block and use the number of readings as a condition for starting the wear average program. For example, in one month, the data block 810 has the lowest number of reads and the number of erases does not exceed the erase threshold. The main device 110 may select all the blocks in the idle block or the same input / output channel. There are idle blocks with the highest number of erasures in idle blocks, such as: idle block 830 as the destination block, and data block 810 as the source block. The wear-out averaging process is started to use data block 810. The user data (or cold data) is moved to the idle block 830, where the wear average process includes a series of read and write commands.

However, using the read and write commands as described above to complete the garbage collection or wear averaging process will make queue 115 consume a lot of space to store a series of read and write commands and completion components, and the data buffer 120 also needs It takes a large amount of bandwidth to transmit the data read from the storage unit 139 and the data to be written to the storage unit 139, and it takes a lot of space to store the data read from the storage unit 139. In addition, the host device 110 and the processing unit 133 also need to consume a large amount of computing resources to process this series of read and write commands, which will make the open channel solid state hard disk 130 unable to maintain appropriate computing resources and respond to the data of the host device 110 in a timely manner. The access command causes the system performance of the open channel solid state hard disk 130 to decrease.

In order to solve the shortcomings of the above-mentioned embodiments, an embodiment of the present invention proposes a method for internally moving data in flash memory. This method for internally moving data is applicable to a system where the physical storage comparison table 117 is maintained by the main device 110, such as: Channel solid state drive system 100. FIG. 9 is a flowchart of a method for internally transferring data in a flash memory according to an embodiment of the present invention. The host device 110 may periodically monitor the usage status of each input / output channel, for example, the number of available idle blocks, the number of erasing or reading times of each physical block, and the like. When the main device 110 detects that the use status of an input / output channel in the open channel solid state hard disk 130 satisfies the condition of data movement, it generates an Internal Movement command and writes it to the submission queue 510 (step S9110), To indicate The open channel solid state hard disk 130 moves user data of a source block in a specific input / output channel to a destination block in the same input / output channel. The condition for data transfer may be that the number of idle blocks is lower than the idle threshold. Or the number of erasures or reads of the data block (source block) is higher than the erase threshold or read threshold, respectively. In addition, it is better to move only valid user data to the destination block, but for higher execution efficiency or when most of the user data is valid, all user data can be moved to the destination block.

After the internal transfer command is written to the submission queue 510, the main device 110 sends a delivery doorbell to the processing unit 133 (step S1120) to notify the processing unit 133 that the data access command has been written into the submission queue 510. After receiving the doorbell (step S1310), the processing unit 133 reads the internal movement command from the submission queue 510 (step S9310), and instructs the flash controller 135 to drive the access interface 137 on the specific input / output channel in response to the internal movement command. A CopyBack Procedure is started between the source block and the destination block (step S9320). Although in the most ideal case, the earliest arriving data access command read by the processing unit 133 in step S9310 is an internal transfer command, but when there is another earlier arriving data access command in the submission queue 510, the processing is performed. The unit 133 will take some time to read and execute the data access commands that arrive earlier, and then read and execute the internal move command in step S9310. Although the embodiment of the present invention cannot show the reading and execution of these earlier arriving data access commands in FIG. 6, the present invention is not limited thereby. After the processing unit 133 completes the internal transfer operation, the processing unit 133 writes a completion component to the completion queue 530 (step S9330) to notify the host device 110 that the corresponding internal transfer command has been completed. In step S1130, the main device 110 may perform an interrupt service process. A program (ISR, Interrupt Service Routine) is used to read the completed components in the completion queue 530 and update the entity storage comparison table 117 according to the internal moving operation that has been performed. For example, the physical address (that is, the source block) of a logical block address in the physical storage comparison table 117 is updated to a new physical address (that is, the destination block). Although in the most ideal case, the earliest arrival confirmation message read by the processing unit 133 at step S1130 corresponds to the internal move command, but when there are other earlier arrival confirmation messages in the completion queue 530, the processing unit 133 will After taking some time to read the confirmation messages that arrived earlier and performing the corresponding processing, then in step S1130, the confirmation messages corresponding to the internal move command are read, and the entity storage comparison table 117 is updated accordingly. Although the embodiment of the present invention cannot show the reading and corresponding processing of these earlier confirmation messages in FIG. 6, the present invention is not limited thereby. In another embodiment, the host device 110 updates the entity storage comparison table 117 before step S9110 or step S9110, instead of waiting until step S1130 or step S1130 to update the entity storage comparison table 117. In another embodiment, in step S1130, the main device 110 further determines whether the destination block is filled with user data and writes end-of-block information. If it is, the entity storage comparison table 117 is updated, and if not, then Do not update the entity storage lookup table 117.

Internal move commands can be defined using a structured format. FIG. 10 is a data format diagram of an internal move command according to an embodiment of the present invention. The internal move command can be a 64-bit command. The 0th byte of the 0th double block of the internal transfer command 1000 records an opcode 1010, which is used to notify the open channel solid state hard disk 130 that this is an internal transfer command. The 2nd to 3rd byte of the 0th double block of the internal transfer command 1000 records the command identification code 1030, and the command identification code 1030 is preferably a sequential production Health, as the basis for identifying the internal move command 1000, is also used to associate a corresponding completion element in the completion queue 530 with the internal move command 1000. The internal transfer command 1000 instructs the open channel solid state hard disk 130 to perform a data transfer operation of a specific input / output channel by using a section as a basic unit, but is not limited thereto.

The internal move command 1000 of the 12th double block of bits 0 to 5 records the number of moving segments of 1080, with a maximum value of 64. Therefore, an internal move command 1000 can instruct the open channel solid state hard disk 130 to be moved during the data transfer operation. User data for up to 64 segments in a particular input / output channel.

The 10th to 11th double blocks of the internal transfer command 1000 record the physical sector information 1070. If the physical address of the physical block is represented by 32 bits, and the value of the number of moving sections 1080 is 1, the 10th double-byte record of the internal move command 1000 stores the user data in the section address of the source block ( Source address), the eleventh double-byte record segment address (destination address) where user data is stored in the destination block. By copying and writing back the program, the processing unit 133 can program the user data of the source address to the destination address.

If the value of the moving segment number 1080 is greater than 1, or the physical address of the physical block is represented by 64 bits, the physical segment information 1070 records the memory address of the data buffer 120. At this time, the source address and the destination bit The addresses are stored in the data buffer 120 in pairs. In step S9310, the processing unit 133 reads the internal move command 1000 from the submission queue 510 and obtains the paired source address from the data buffer 120 according to the record of the physical section information 1070 and the value of the number of moved sections 1080. The destination address. By copying and writing back the program, the processing unit 133 can program a plurality of user data from a plurality of source addresses to a plurality of designated destination addresses.

In another embodiment, the 6th to 7th double words of the internal transfer command 1000 record the main memory address 1050 with a Physical Region Page Entry (PRP) or a Scatter Gather List (SGL), In addition, the 8th to 9th double words of the internal move command 1000 extend the memory address 1060 with a physical area page record or a fragment collection list record. When the value of the moving segment number 1080 is greater than 1, the physical segment information 1070 can record the first source address, and the main memory address 1050 can record the first destination address. In another embodiment, the main memory address 1050 can record the first source address, and the deferred memory address 1060 can record the first destination address. In another embodiment, the main memory address 1050 can record the first pair of source address and destination address. When the memory space covered by the main memory address 1050 cannot record all the pair of source addresses and For the destination address, the deferred memory address 1060 can record the remaining paired source address and destination address.

The internal shift command 1000 of the 12th double block has a 24-25 bit record write mode (M1) 1020, and the 12th double block has a 26-27 bit record read mode (M2) 1040. The write mode and read mode can each include two states, such as: preset mode and SLC mode. When it indicates the SLC mode, the processing unit 133 instructs the flash controller 135 to read or write data of one page in the SLC mode through the driving access interface 137. When it indicates the preset mode, the processing unit 133 instructs the flash controller 135 to read or write data of a page in the preset mode by driving the access interface 137. The preset mode uses TLC as an example. This page can be an MSB page, a CSB page, or an LSB page. In other embodiments, the write mode may include four states, such as: SLC mode; MLC mode; TLC mode; and QLC mode. In addition, the number of write modes is preferably the same as the programming mode of the storage unit 139. For example, the storage unit 139 is QLC and adopts 3-pass programming. The first section of programming is only written into the MSB page, the second section of programming is written into the CSB page and the LSB page, and the third section is programmed again. When writing to a TSB page, the writing mode can include three modes, including: SLC mode, TLC mode, and QLC mode (preset mode). When it indicates the QLC mode, the processing unit 133 instructs the flash controller 135 to request a specific I / O channel to write the user data of the MSB page, CSB page, LSB page, or TSB page in each memory unit by driving the access interface 137. . The above settings can also be applied to the read mode. It should be noted that the setting values of the reading mode and the writing mode may be different. For example, the reading mode is an SLC mode but the writing mode is a preset mode. Assuming that the storage unit 139 is QLC, the main device 110 may output multiple internal transfer commands 1000 and read 4 user data from the source address of the source block in SLC mode, and sequentially program to the destination area in QLC mode. Destination address of the block.

Figure 11 is a data format diagram of the completed component. The completion element 1100 may be a 16-byte message. The 0 to 1 byte record command identification code 1130 of the third double block of the completion element 1100 should be consistent with the command identification code 1030 of the internal transfer command 1000, so that the completion element 1100 is associated with a specific internal removal Order 1000. The 0 to 1 double-word storage execution completion table 1110 of the completion component 1100 is used to record the access result of each user data. The 17th to 31st bit record status field 1120 of the third double block of the completion element 1100 is used to record the execution result of the internal move command 1000.

Before step S9110, the main device 110 system can store a plurality of usage records 119, and each record stores the usage status information of the physical block of an input / output channel. Perform data access operations on each open channel SSD 130 Industry (for example, erasing, reading, writing, internal relocation, etc.), the main device 110 may update the usage status information in the corresponding usage record and determine whether the data transfer conditions of the corresponding input / output channels are met. For example, the number of idle blocks of the corresponding input / output channel is reduced by 1, the number of erasures of a physical block of the corresponding input / output channel is increased by 1, or the number of reads of a data block of the corresponding input / output channel is increased by 1. Wait. In some embodiments, when the use record 119 indicates that the number of idle blocks of the corresponding input / output channel is lower than the idle threshold, it means that the number of idle blocks is too small, and a garbage collection process needs to be started to increase the number of idle blocks. . In some embodiments, when the use record 119 indicates that the number of erasures of a physical block of the corresponding input / output channel is higher than the erasure threshold, the host device initiates a wear averaging process to avoid user data encountering the problem of data storage.

In the process of reading or writing data, you may encounter read failure or write failure. When the above situation is encountered, the status field 1120 of the completion component 1100 will be set to "1", and the bit corresponding to the user data that failed to read or write will be set to "1" ". At this time, the host device 110 must first determine whether the failure is a read failure or a write failure. If it is a read failure, start an error management program, such as RAID, to repair the user data of the source address; if it is a write If it fails, a new destination address is determined for the user data.

It can be known from the above description that if a failure occurs during the internal removal process, the main device 110 needs to spend a lot of time and computing resources to determine the cause and correct the error. In order to solve the above-mentioned shortcomings, in other embodiments, the host device 110 does not determine a destination address for the user data of each source address, but allows the open channel solid state hard disk 130 to determine it. The solid state hard disk 130 then uploads the determined destination address to the memory address of the data buffer 120 designated by the main device 111 according to the instruction of the internal transfer command 1000, such as the main memory address 1050, the extended memory address 1060, or the entity. Memory address specified by section information 1070. Finally, the completion device 1100 is used to notify the host device 110 that the destination address has been uploaded. After that, the host device 110 may update the entity storage lookup table 117 according to the destination address.

When user data needs to be moved in multiple sections, in detail, before step S9110, the main device 110 can store the source addresses of multiple user data in the data buffer 120, and store the source addresses in the data. The memory address of the buffer 120 is stored in one of the main memory address 1050, the extended memory address 1060, or the physical section information 1070 in the internal transfer command 1000, the main memory address 1050, the extended memory address 1060, or the physical section The other of the information 1070 is a destination address for the open channel solid state hard disk 130 to upload user data. In step S9110, the internal transfer command 1000 is written into the delivery queue 510. The source address can be represented by a logical unit number, a data plane number, a physical block number, a physical page number, and a section number. In step S9310, the processing unit 133 reads and judges the operation code 1010 of the internal move command 1000, and then reads the number of moved sections 1080 of the internal move command 1000, the main memory address 1050, the deferred memory address 1060, or the physical area. The value of the segment information 1070, and then the memory address of the data buffer 120 to obtain the source address of the plurality of user data. Next, in step S9320, the processing unit 133 determines a destination address for each user data. For example, an idle block with erasure times is selected as the destination block, and the flash controller 135 is instructed to drive the access interface 137. Perform a copy-write procedure on the source and destination blocks of a particular input-output channel. When writing any When each destination address fails, the processing unit 133 programs the user data to the next page (the first section); or directly writes all the remaining pages of this physical character line into dummy data, and then Program user data to the MSB page (first section) of the next physical character line, or re-instruct the flash controller 135 to request the source block of a specific input / output channel through the drive access interface 137 Perform a copy-write procedure with the destination block to move the user data to the MSB page of the next physical character line, or program the user data to another destination block. In step S9330, after the copy and write procedure is successfully executed, the processing unit 133 can store the destination addresses of all user data in the data buffer 120, and write the completion element 1100 to the completion queue 530. In step S1130, after receiving the completion component 1100, the main device 110 reads all the purposes from the data buffer 120 according to the value of the number of moved sections 1080, the main memory address 1050, the extended memory address 1060, or the physical section information 1070. Address, and update the physical storage lookup table 117 accordingly.

When only one section of user data needs to be moved, in detail, in step S9110, the main device 110 can store a source address to the physical section information 1070 in the internal move command 1000, and set the main memory address 1050 The value is used for the destination address of the open channel solid state hard disk 130 for uploading user data, and the internal transfer command 1000 is written to the submission queue 510. In step S9310, when the processing unit 133 reads the source address of the physical section information 1070 in the internal move command 1000, determines a destination address for the source address, and instructs the flash controller 135 to drive the access interface 137 through the driver. Requires specific I / O channels to perform a copy-write procedure. In step S9330, after the copy and write procedure is successfully executed, the processing unit 133 uploads the destination address of the user data to the main memory address. The memory address corresponding to 1050 is written into the completion element 1100 to the completion queue 530. In step S1130, the main device 110 reads the completed component 1100 and reads the destination address from the data buffer 120 according to the value of the main memory address 1050, and updates the physical storage comparison table 117 accordingly.

FIG. 12 is a schematic diagram of an internal moving operation of a waste collection program according to an embodiment of the present invention. The main device 111 can write an internal move command to the submission queue 510. The internal move command includes multiple sets of physical locations of the source section and the destination section. The first group contains the physical locations of the source section 711 and the destination section 771, the second group contains the physical locations of the source section 733 and the destination section 773, and the third group contains the physical locations of the source section 755 and the destination section 775. , And the fourth group contains the physical locations of the source section 757 and the destination section 777. Then, the flash controller 135 drives the access sub-interface 1210 to execute the copy-back and write-back procedure. The access sub-interface 1210 instructs the DMA-Direct Memory Access Circuit 1230 to read the data of the source sections 711, 733, 755, and 757, and collects and stores the data in the register 1250, and then instructs the direct data access circuit 1230 writes the data of an entire physical page in the register 1250 into the physical page P4 (including the sections 771, 773, 775, and 777) in the physical block 770.

FIG. 13 is a schematic diagram of an internal moving operation according to a wear averaging program according to an embodiment of the present invention. The main device 111 can write an internal move command to the submission queue 510. The internal move command includes multiple sets of physical locations of the source section and the destination section. For example, the first group contains the first source section in the physical page P5 of the physical block 810 and the physical location of the first destination section in the physical page P7 of the physical block 830, and the second group contains the physical page P5 of the physical block 810. The second source section in the second block and the physical bit in the second destination section in the physical page P7 of the physical block 830 Settings, and so on. Then, the flash controller 135 drives the access sub-interface 1310 to execute the copy-back and write-back procedure. The access sub-interface 1310 instructs the direct data access circuit 1330 to read the data of the eight source sections in the physical pages P5 and P6 and stores them in the register 1350. Then, the direct data access circuit 1330 instructs the direct data access circuit 1330 to register the two entities in the register 1350 The data of the page is written into the physical pages P7 and P8 in the physical block 830.

In addition, the user data does not need to be uploaded to the data buffer 120 during the execution of the copy-back program. The flash controller 135 outputs a read-back read command to the source block of the storage unit 139, so that the user data read from the source address is temporarily stored in a register (cache register or page register) of the storage unit 139. in. Then, the flash controller 135 outputs the program command copied back to the destination block of the storage unit 139, so that the user data temporarily stored in the register 1250 is programmed to the destination address. Since user data does not need to be uploaded to the data buffer 120, the time for transmitting user data from the source block to the data buffer 120 and from the data buffer 120 to the destination block can be saved, which can increase openness The system performance of the channel solid state hard disk 130 achieves the purpose of the present invention.

Although the above-mentioned elements are included in the drawings 1 to 3, it is not excluded that more technical advantages can be achieved by using more additional elements without violating the spirit of the invention. In addition, although the flowcharts in Figures 6 and 9 are executed in a specified order, those skilled in the art can modify the order between these steps without violating the spirit of the invention. Therefore, the present invention is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited by this.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. Rather, the invention encompasses modifications and similar arrangements apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest way to encompass all obvious modifications and similar arrangements.

Claims (22)

A flash memory internal data transfer method executed by a host device includes: generating an internal transfer command when detecting that a use state of an input / output channel in a solid-state hard disk meets a condition; and providing the above; The internal moving command instructs the solid-state hard disk to perform an internal data moving operation in the input / output channel. The flash memory data internal moving method according to the first patent application scope includes: writing the internal moving command to a submission queue; and sending a doorbell to a processing unit of the solid-state hard disk, so that The processing unit reads the internal transfer command from the delivery queue, and instructs a flash controller to request the input / output channel to execute a copy-write program to use a source location in the input / output channel according to the internal transfer command. This information is moved to a destination location. According to the flash memory data internal moving method as described in the first item of the patent application scope, the method includes: storing multiple data moving records in a data buffer before providing the internal moving command, wherein, among the above data moving records, Each includes a pair of a source location and a destination location, and any one of the source location and the destination location is identified by a logical unit number, a data plane number, a physical block number, a physical page number, and a section The number indicates; and a memory address pointing to a first data movement record is stored to the internal movement command, so that the solid-state hard disk obtains the source location and the physical address from the data buffer. The internal data transfer method of the flash memory according to item 3 of the scope of patent application, comprising: after receiving a completion component corresponding to the internal transfer command from the solid-state hard disk, according to the source location and the destination location Update a physical storage comparison table, wherein the physical storage comparison table indicates where the data of each logical block address is actually stored in a storage unit in the solid-state hard disk. According to the flash memory data internal moving method as described in the first item of the patent application scope, the method includes: storing multiple data moving records in a data buffer before providing the internal moving command, wherein, among the above data moving records, Each includes a source location, and the source location is represented by a logical unit number, a data plane number, a physical block number, a physical page number, and a section number; and a memory address storing a pointer to a first data transfer record To the internal move command, the solid-state hard disk obtains the source location from the data buffer, determines a destination location based on the source location, and stores the destination location into the data buffer. The internal data transfer method of the flash memory according to item 5 of the scope of the patent application, comprising: obtaining the above-mentioned destination location corresponding to each of the above-mentioned source locations from the above-mentioned data buffer; and according to the above-mentioned source location and the above-mentioned destination The location updates a physical storage lookup table, where the physical storage lookup table indicates where the data of each logical block address is actually stored in a storage unit in the solid state hard disk. A flash memory internal data transfer device includes: a main device that generates an internal transfer command when it detects that a use status of an input / output channel in a solid-state hard disk meets a condition; and provides the above-mentioned internal transfer The command instructs the solid-state hard disk to perform an internal data transfer operation in the input / output channel. According to the flash memory data internal transfer device described in item 7 of the patent application scope, including: a submission queue; wherein the main device writes the internal transfer command to the submission queue; and sends a doorbell to A processing unit of the solid-state hard disk, so that the processing unit reads the internal transfer command from the delivery queue, and instructs a flash controller to request the input / output channel to execute a copy-write-back program to execute the above-mentioned internal transfer command according to the internal transfer command User data from a source location in the input / output channel is moved to a destination location. According to the flash memory data internal moving device described in item 7 of the patent application scope, including: a data buffer; wherein the main device stores multiple data moving records to the data buffer before providing the internal moving command. Area, wherein each of the above-mentioned data transfer records includes a one-to-one source location and an entity address, and any one of the above-mentioned source location and the above-mentioned destination location is represented by a logical unit number, a data plane number, an entity Block number, physical page number, and section number indication; and storing a memory address pointing to the first data transfer record to the internal transfer command, so that the solid-state hard disk obtains the source location and the above from the data buffer The physical address. According to the flash memory data internal moving device according to item 9 of the patent application scope, wherein the main device receives a completion component corresponding to the internal moving command from the solid-state hard disk, according to the above source location and the above The destination location updates a physical storage lookup table, where the physical storage lookup table indicates where the data of each logical block address is actually stored in a storage unit in the solid state hard disk. According to the flash memory data internal moving device described in item 7 of the patent application scope, including: a data buffer; wherein the main device stores multiple data moving records to a data buffer before providing the internal moving command. Area, wherein each of the above-mentioned data transfer records includes a source location, and the above-mentioned source location is represented by a logical unit number, a data plane number, a physical block number, a physical page number, and a section number; and A memory address of a data transfer record to the internal transfer command enables the solid-state hard disk to obtain the source location from the data buffer, determine a destination location based on the source location, and store the destination location to a data Buffer. According to the flash memory data internal moving device according to item 11 of the patent application scope, wherein the main device obtains the above-mentioned destination location corresponding to each of the above-mentioned source locations from the above-mentioned data buffer area; and The destination location updates a physical storage lookup table, where the physical storage lookup table indicates where in the storage unit in the solid state hard disk the data of each logical block address is actually stored. According to the flash memory data internal moving device according to item 7 of the patent application scope, wherein the above-mentioned use state of the input / output channel in the solid-state hard disk satisfies the above-mentioned condition, it refers to a storage unit in the solid-state hard disk. Not enough free space. According to the flash memory data internal moving device according to item 7 of the patent application scope, wherein the above-mentioned use state of the input / output channel in the solid-state hard disk satisfies the above condition refers to a physical block in the input / output channel The number of erasures exceeds a threshold. A flash memory data internal moving method is executed by a processing unit in a solid-state hard disk and includes: obtaining an internal moving command generated by a host device, wherein the internal moving command instructs the solid-state hard disk to a An internal data transfer operation is performed in the input / output channel, including a memory address pointing to a first data transfer record in a data buffer; multiple data transfer records are obtained starting from the above memory address in the data buffer In which, each of the above-mentioned data transfer records includes a source location; determining a destination location in the input / output channel for each of the above source locations; instructing a flash controller to request the input / output channel to perform a copy back The writing program moves the user data of each of the above source locations in the input and output channels to the determined destination location; and responds to the destination location of each of the above source locations to the host device. The flash memory data internal transfer method according to item 15 of the scope of patent application includes: after receiving a delivery doorbell from the main device, reading the internal transfer command from a delivery queue. The flash memory data internal moving method according to item 15 of the scope of patent application, comprising: when writing to any of the above destination locations fails, re-determining a destination location; and instructing the above flash control The processor requests the input / output channel to execute a copy-back write procedure to move the user data of the corresponding source location to the re-determined destination location. The internal data transfer method of the flash memory according to item 15 of the scope of the patent application, which includes: after the copy-write-back procedure is executed, storing the destination locations corresponding to all the source locations to the data buffer; storing A memory address pointing to a first destination position in the data buffer to a completion element; and writing the completion element to a completion queue. A flash memory data internal moving device includes: a flash controller; and a processing unit coupled to the flash controller to obtain an internal moving command generated by a main device, wherein the internal moving The command instructs a solid state hard disk to perform an internal data transfer operation in an input / output channel, including a memory address pointing to a first data transfer record in a data buffer; from the above memory position in the data buffer Start to obtain multiple data transfer records, where each of the data transfer records includes a source location; determine a destination location in the input / output channel for each of the source locations; instruct the flash controller request The input / output channel executes a copy and write procedure to move the user data of each of the source locations in the input / output channel to the determined destination location; and responds to the destination location of each of the source locations to the master Device. According to the flash memory data internal moving device according to item 19 of the patent application scope, wherein the processing unit receives a delivery doorbell from the main device, and reads the internal moving command from a delivery queue. The flash memory data internal moving device according to item 19 of the scope of patent application, wherein when writing to any of the above destination locations fails, the processing unit newly determines a destination location; and instructs the above destination location; The flash controller requires the I / O channel to execute a copy-back program to move the data of the corresponding source position to the re-determined destination position. According to the flash memory data internal moving device according to item 19 of the patent application scope, wherein after the copy-write-back program is executed, the processing unit stores the destination locations corresponding to all the source locations to the data buffer Area; storing a memory address pointing to a first destination location in the data buffer to a completion element; and writing the completion element to a completion queue.