TWI790568B - Work status control method for memory device and data storage system - Google Patents

Abstract

A work status control method for a memory device and a data storage system are disclosed. The method includes: detecting a status of a host system; sending a first control command to a memory device in response to that the status of the host system is a idle status. The first control command is configured to adjust a buffer time for the memory device changing from a first work status to a second work status.

Description

Working state control method and data storage system of memory device

The present invention relates to a memory control technology, and in particular to a working state control method and a data storage system of a memory device.

Compared with traditional hard disks, memory devices have the advantages of fast access speed and small size. However, in the use of the memory device, data needs to be moved and sorted frequently to release more writing space for writing new data. Generally speaking, the memory device can perform data migration and sorting in the background, such as after booting, before shutting down, or during switching working states. However, in practice, the time for the memory device to move and organize data in the background is often insufficient. Once the cache area of the memory device is full, the memory device will actively slow down, thereby reducing the working efficiency of the memory device.

The invention provides a working state control method and a data storage system of a memory device, which can increase the working efficiency of the memory device by prolonging the buffer time when the memory device switches between different working states.

An embodiment of the present invention provides a method for controlling the working state of a memory device, which is used in a host system. The host system is coupled to the memory device. The working state control method includes: detecting the state of the host system; and sending a first control command to the memory device in response to the state of the host system being an idle state. The first control instruction is used to adjust the buffer time for the memory device to switch from the first working state to the second working state.

An embodiment of the present invention further provides a data storage system, which includes a host system and a memory device. The memory device is coupled to the host system and used for storing data from the host system. The host system is used to detect the status of the host system. The host system is further configured to send a first control command to the memory device in response to the state of the host system being an idle state. The memory device is used for adjusting the buffer time for switching from the first working state to the second working state according to the first control instruction.

Based on the above, when the state of the host system is the idle state, the host system can send the first control command to the memory device. The first control instruction can be used to adjust the buffer time for the memory device to switch from the first working state to the second working state. By prolonging the buffer time when the memory device switches between different working states, more sufficient time can be provided for the memory device to perform background data sorting, thereby improving the working efficiency of the memory device.

FIG. 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Referring to FIG. 1 , the data storage system includes a host system 11 and a memory device 12 . The host system 11 can store data into the memory device 12 or read data from the memory device 12 . For example, the host system 11 is any system that can actually cooperate with the memory device 12 to store data, such as a computer system, a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, etc., and the memory The device 12 can be a flash drive, a memory card, a solid state drive (Solid State Drive, SSD), a secure digital (Secure Digital, SD) card, a small flash (Compact Flash, CF) card or an embedded storage device, etc. non-volatile memory device.

In one embodiment, the host system 11 may include a connection interface 111 , a sensor 112 and a processor 113 . The connection interface 111 is used for coupling to the memory device 12 and communicating with the memory device 12 . For example, the connection interface 111 can transmit data to or receive data from the memory device 12 . The sensor 112 can be used to sense environmental information. For example, the sensor 112 may include an image capturing device such as a lens or other types of sensors, which is not limited by the present invention.

The processor 113 is coupled to the connection interface 111 and the sensor 112 . The processor 113 can be responsible for the whole or part of the operation of the host system 11 . For example, the processor 113 may include a central processing unit (CPU) or other programmable general-purpose or special-purpose microprocessors, digital signal processors (Digital Signal Processor, DSP), programmable controllers, special application Integrated circuit (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD) or other similar devices or a combination of these devices.

In one embodiment, the host system 11 may also include any practically required hardware devices, such as storage media, battery units, network interface cards, keyboards (or touchpads), screens and/or speakers, and the like.

In one embodiment, the memory device 12 includes a connection interface 121 , a memory module 122 and a memory controller 123 . The connection interface 121 is used for connecting to the connection interface 112 of the host system 11 and communicating with the host system 11 through the connection interface 112 . For example, the connection interfaces 111 and 121 can conform to Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) or universal serial Various connection interface standards such as Universal Serial Bus (USB). In one embodiment, the connection interfaces 111 and 121 conform to the NVM Express (NVMe) specification.

The memory module 122 is used for storing data written by the host system 11 . For example, the memory module 122 may include a single-level cell (Single Level Cell, SLC) NAND flash memory module (ie, a memory cell can store 1 bit of flash memory module), multi-level Cell (Multi Level Cell, MLC) NAND flash memory module (that is, a memory cell can store 2 bits of flash memory module), triple level cell (Triple Level Cell, TLC) NAND flash memory module Flash memory module (that is, a flash memory module that can store 3 bits in a memory cell) and/or a quad-level cell (Quad Level Cell, QLC) NAND flash memory module (that is, a A memory cell can store 4 bits of flash memory module). For example, the memory cells in the memory module 122 store data by changing the threshold voltage. In one embodiment, the memory module 122 is also called a flash memory module.

The memory module 122 includes a plurality of physical units. Each physical unit may include multiple memory cells. For example, a physical unit may include one or more physical pages, one or more physical blocks, or one or more other memory cell management units. Memory cells belonging to the same physical page can be programmed simultaneously to store data. Memory cells belonging to the same physical block can be erased at the same time to clear data.

In one embodiment, the memory module 122 includes a cache area 1221 and a storage area 1222 . Each memory cell in each physical unit in the cache area 1221 can store N bits. Each memory cell in each physical unit in the storage area 1222 can store M bits. Both M and N are integers, and M is greater than N. For example, N can be 1 and M can be 2, 3 or 4. For example, the physical units in the cache area 1221 can operate in SLC (or virtual SLC) mode, while the physical units in the storage area 1222 can operate in MLC, TLC or QLC mode.

In one embodiment, the speed and/or reliability of writing data into a physical unit in the cache area 1221 is higher than the speed and/or reliability of writing data into a physical unit in the storage area 1222 . In one embodiment, the capacity of one physical unit in the storage area 1222 (that is, the amount of stored data) is greater than the capacity of one physical unit in the cache area 1221 .

The memory controller 123 is coupled to the connection interface 121 and the memory module 122 . The memory controller 123 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and to write, read and erase data in the memory module 122 according to the instructions of the host system 11. operation. In addition, the memory controller 123 can also control the overall operation of the memory device 12 . In one embodiment, the memory controller 123 is also called a flash memory controller.

In one embodiment, the maximum number of physical units in the cache area 1221 is less than the maximum number of physical units in the storage area 1222 . When the physical units in the cache area 1221 have not been used up, the data from the host system 11 can be written to the physical units in the cache area 1221 at a faster speed and/or with higher reliability. Afterwards, the memory controller 123 can perform background data sorting during the operation of the memory device 12 to move valid data from the physical units in the cache area 1221 to the physical units in the storage area 1222 . Wherein, the valid data refers to data belonging to a Logical Block Address (LBA). After copying all valid data stored in a certain physical unit in the cache area 1221 to the storage area 1222, the physical unit in the cache area 1221 can be erased (also called release) to receive data from the host system again. 11 new information.

Generally speaking, the time for the memory controller 123 to perform the background data sorting is quite limited. For example, the memory controller 123 may only execute the background data arrangement temporarily after the memory device 12 is turned on, before it is turned off, during switching working states, or when the access load of some memory devices 12 is low. Once the physical units in the cache area 1221 are used up (that is, there are no available physical units in the cache area 1221), the data from the host system 11 needs to be written directly at a slower speed and/or with lower reliability To the physical unit in storage area 1222. In other words, during the operation of the memory device 12, if there is enough time for the memory controller 123 to perform background data sorting, so as to release available physical units in the cache area 1221 as much as possible, then from the host system 11 The data can be stored in the memory device 12 (that is, the cache area 1221 ) at a faster speed and/or with a higher reliability.

In one embodiment, the processor 113 can detect the current state of the host system 11 . In response to the current state of the host system 11 being the idle state, the processor 113 may send a control command (also referred to as a first control command) to the memory device 12 . The first control command can be used to adjust the buffer time for the memory device 12 to switch from a certain working state (also called the first working state) to another working state (also called the second working state).

In one embodiment, the system performance of the memory device 12 in the first working state is higher than the system performance of the memory device 12 in the second working state. In an embodiment, the first working state may refer to power state 0 (Power State 0, PS0) in the NVMe specification. PS0 is also called normal working state. In an embodiment, the second working state may refer to power state 1 (PS1) in the NVMe specification. Compared with PS0, in the PS1 state, the system performance and power consumption of the memory device 12 will be reduced.

In one embodiment, the first control command is further used to instruct the memory device 12 to switch from the first working state to the second working state. In an embodiment, the adjusted buffer time may be greater than a preset value of the buffer time. That is to say, the processor 113 can use the first control instruction to instruct the memory device 12 to switch from the first working state to the second working state, and at the same time use the first control instruction to instruct the memory device 12 to extend the The buffer time for switching from the first working state to the second working state.

In one embodiment, when the memory controller 123 switches the working state of the memory device 12 according to the first control command, the memory controller 123 can execute the The above-mentioned background data is sorted to move valid data from at least one physical unit (also called the first physical unit) in the cache area 1221 to at least one physical unit (also called the second physical unit) in the storage area 1222 . In one embodiment, by prolonging the buffer time, the memory controller 123 can have more time to execute the background data sorting before switching to the second working state, thereby improving the performance of the cache area 1221. The release efficiency of available solid units.

In one embodiment, in response to the state of the host system 11 being not the idle state, the processor 113 may send another control command (also referred to as a second control command) to the memory device 12 . The second control command can be used to instruct the memory device 12 to return from the second working state to the first working state and restore the buffer time to a preset value.

FIG. 2 is a schematic diagram of an operation sequence of working state control according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 2 , it is assumed that the memory device 12 is in a first working state (eg PS0 or normal working state) before the time point T(0). At time point T(0), in response to the host system 11 being in an idle state, the memory device 12 may receive a first control command from the host system 11 . In response to the first control command, after the buffer time BF(T), at the time point T(1), the memory device 12 can switch its working state, that is, switch from the first working state to the second working state (for example, PS1 ). It should be noted that, within the buffer time BF(T), the memory device 12 can continue to execute the background data sorting, and temporarily does not complete the switching of the working state.

After being switched to the second working state, the memory device 12 can continue to operate in the second working state between time points T(1) and T(2). After the time point T(2), in response to the host system 11 leaving the idle state (that is, returning to the normal operation state), the memory device 12 can receive a second control command from the host system 11 and return to the first control command according to the second control command. working status.

FIG. 3 is a schematic diagram of adjusting buffer time between switching working states according to an embodiment of the present invention. Referring to FIG. 3 , in response to the first control command, the memory device 12 can adjust the buffer time BF(T) from the preset BF(0) to BF(1), and the time length corresponding to BF(1) is greater than The length of time corresponding to BF(0). Then, in response to the second control command, the memory device 12 can restore the buffer time BF(T) to a preset BF(0).

Returning to FIG. 1 , in one embodiment, the processor 113 can detect whether the operator of the host system 11 has left. If the processor 113 determines that the operator of the host system 11 has left, the processor 113 may determine that the current state of the host system 11 is an idle state. On the contrary, if the processor 113 determines that the operator of the host system 11 has not left (for example, the operator of the host system 11 continues to operate the host system 11 ), the processor 113 may determine that the current state of the host system 11 is not an idle state.

In one embodiment, the processor 113 can determine whether the current state of the host system 11 is an idle state through the sensor 112 . For example, assuming that the sensor 112 includes a camera, then when the user continues to appear in front of the camera, the processor 113 can determine based on the image captured by the sensor 112 that the operator of the host system 11 has not left and the current status of the host system 11 is Status is not idle. On the contrary, when the user does not appear in front of the camera, the processor 113 can determine according to the image captured by the sensor 112 that the operator of the host system 11 has left and the current state of the host system 11 is idle.

In one embodiment, the processor 113 can also analyze the current user's operating state of the host system 11 to determine whether the operator of the host system 11 has left and/or whether the current state of the host system 11 is idle. For example, the processor 113 can continuously detect the operation status of the input/output devices such as the mouse, the keyboard, the control panel and/or the touch screen of the host system 11 by the user. When the user does not operate the input/output device within a certain period of time, the processor 113 may determine that the operator of the host system 11 has left. On the contrary, if the user continues to use or operate the input/output device within the time range, the processor 113 may determine that the operator of the host system 11 has not left.

In one embodiment, when the host system 11 is in an idle state (such as a state where the operator of the host system 11 has left), the host system 11 can use the first control command to instruct the memory device 12 to enter a relatively power-saving mode. The second working state allows the memory device 12 to have more time to execute the background data sorting before entering the second working state. In particular, when the host system 11 is in an idle state (such as a state where the operator of the host system 11 has left), even if the memory device 12 takes more time to switch between working states, the operating experience of the host system 11 will not be affected. would be too large to be ignored.

In one embodiment, after the host system 11 leaves the idle state (for example, the operator of the host system 11 returns), the host system 11 can use the second control command to instruct the memory device 12 to return to a higher working efficiency The first working state of the system is automatically operated based on the preset buffer time. In particular, the internal parameters of the memory device 12 (including the buffer time) are generally set to appropriate values before leaving the factory. Therefore, after the host system 11 returns to the normal operating state, allowing the memory device 12 to operate autonomously based on the preset buffer time can avoid excessive interference with the operation of the memory device 12, thereby keeping the memory device 12 in a better state. working status.

FIG. 4 is a flow chart of a method for controlling the working state of a memory device according to an embodiment of the present invention. Please refer to FIG. 4 , in step S401 , the state of the host system is detected. In step S402, it is determined whether the state of the host system is an idle state. In response to the state of the host system being an idle state, in step S403, a first control command is sent to the memory device. The first control instruction is used to adjust the buffer time for the memory device to switch from the first working state to the second working state. In addition, if the state of the host system is not idle state, step S401 may be repeatedly executed.

FIG. 5 is a flowchart of a method for controlling the working state of a memory device according to an embodiment of the present invention. Please refer to FIG. 5 , in step S501 , the state of the host system is detected. In step S502, it is judged whether the state of the host system is an idle state. In response to the state of the host system being an idle state, in step S503, sending a first control command to the memory device to adjust the buffer time for the memory device to switch from the first working state to the second working state . In step S504, in response to the first control instruction, the memory device switches from the first working state to the second working state. In addition, if it is determined in step S502 that the state of the host system is not an idle state, then step S501 may be repeatedly executed.

When the memory device is in the second working state, in step S505, it is determined whether the state of the host system is an idle state. If the state of the host system is idle, step S505 may be repeated. If the state of the host system is not the idle state, in step S506, a second control command is sent to the memory device to restore the adjusted buffer time to a preset value. In step S507, in response to the second control instruction, the memory device returns from the second working state to the first working state. After step S507, step S501 may be executed repeatedly.

However, each step in FIG. 4 and FIG. 5 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 4 and FIG. 5 can be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods shown in FIG. 4 and FIG. 5 can be used together with the above exemplary embodiments, or can be used alone, which is not limited by the present invention.

To sum up, the embodiments of the present invention propose that when the host system is in an idle state (for example, the operator of the host system has left), the buffer time when the memory device switches working states can be moderately extended. In this way, without affecting the operating experience of the host system, the time for the memory device to perform background data sorting can be moderately extended, thereby improving the working efficiency of the memory device.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

11: Host system 111, 121: Connection interface 112: sensor 113: Processor 12: Memory device 122:Memory module 1221: cache area 1222: storage area 123: Memory controller T(0), T(1), T(2): time points BF(T), BF(0) , BF(1): buffer time S401~S403, S501~S507: steps

FIG. 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an operation sequence of working state control according to an embodiment of the present invention. FIG. 3 is a schematic diagram of adjusting buffer time between switching working states according to an embodiment of the present invention. FIG. 4 is a flow chart of a method for controlling the working state of a memory device according to an embodiment of the present invention. FIG. 5 is a flowchart of a method for controlling the working state of a memory device according to an embodiment of the present invention.

S401~S403: steps

Claims (9)

A working state control method of a memory device, used in a host system, wherein the host system is coupled to the memory device, and the working state control method includes: detecting the state of the host system; and responding to the host system The state is an idle state, and a first control command is sent to the memory device, wherein the first control command is used to adjust a buffer time for the memory device to switch from a first working state to a second working state , and within the buffer time, the memory device executes a background data arrangement to move valid data from at least one first physical unit to at least one second physical unit. The working state control method as described in claim 1, wherein the step of detecting the state of the host system includes: detecting whether an operator of the host system has left; and if the operator of the host system has left, It is determined that the state of the host system is the idle state. The working state control method as claimed in claim 1, wherein the first control command is further used to instruct the memory device to switch from the first working state to the second working state. The working state control method according to claim 1, wherein a system performance of the memory device in the first working state is higher than a system performance of the memory device in the second working state. The working state control method according to claim 1, wherein the adjusted buffer time is greater than a preset value of the buffer time. The working state control method as described in claim 1, wherein each memory cell in the at least one first physical unit is used to store N bits, and each memory cell in the at least one second physical unit is used to store M bits, and M is greater than N. The working state control method as described in claim 1, further comprising: in response to the state of the host system being not the idle state, sending a second control command to the memory device, wherein the second control command is used to indicate The memory device returns from the second working state to the first working state and restores the buffer time to a preset value. A data storage system, comprising: a host system; and a memory device coupled to the host system and used to store data from the host system, wherein the host system is used to detect the status of the host system, the host system It is further used to send a first control command to the memory device in response to the state of the host system being an idle state, and the memory device is used to adjust switching from a first working state to a first working state according to the first control command. A buffer time of a second working state, and during the buffer time, the memory device executes a background data arrangement to move valid data from at least one first physical unit to at least one second physical unit. The data storage system as claimed in claim 8, wherein the memory device is further configured to switch from the first working state to the second working state according to the first control command.

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