TW202125206A - Memory management method and memory device - Google Patents

Abstract

A memory management method and a memory device are provided. The method includes: dividing at least one physical block in a memory device to a reservation area; receiving a power-off command from a host system; and storing data in a buffer memory of the memory device to the reservation area when receiving the power-off command.

Description

Memory management method and memory device

The present invention relates to a memory management technology, and particularly relates to a memory management method and a memory device.

Generally speaking, in order to improve the performance of the memory device, a part of the memory space is reserved for over-provisioning (OP) use when the memory device leaves the factory. When the memory space available for normal use in the memory device is insufficient, the memory space reserved for OP can be used to speed up the access of the memory device. However, whether it is generally used memory space or memory space used as OP, in fact, it may be full in the current memory management mechanism. Once all the available memory space in the memory device is full (or is about to be full), when receiving a power-off command from the host system, the memory device will take extra time to repeatedly perform such as garbage collection Wait for the process to free up new memory space to store the data moved from the buffer memory by the memory device in response to the upcoming power failure.

The invention provides a memory management method and a memory device, which can effectively improve the data processing speed before the memory device is powered off.

An embodiment of the present invention provides a memory management method, which is used in a memory device including a buffer memory and a memory module. The memory module includes a plurality of physical blocks. The memory management method includes: dividing at least one first physical block of the plurality of physical blocks into a reserved area; receiving a power-off command from a host system; and when the power-off command is received, The data in the buffer memory is stored in the reserved area.

An embodiment of the present invention further provides a memory device, which includes a connection interface, a buffer memory, a memory module, and a memory controller. The connection interface is used for coupling to the host system. The memory module includes a plurality of physical blocks. The memory controller is coupled to the connection interface, the buffer memory and the memory module. The memory controller is used for dividing at least one first physical block among the plurality of physical blocks into a reserved area. The memory controller is further configured to receive a power-off command from the host system via the connection interface. When receiving the power-off command, the memory controller is further used to store the data in the buffer memory to the reserved area.

Based on the above, at least one first physical block of the memory device can be divided into a reserved area. Afterwards, if a power-off command is received from the host system, the data in the buffer memory can be quickly stored to the reserved area to effectively improve the data processing speed and power-off speed of the memory device before power-off .

FIG. 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. 1, the memory device 10 includes a connection interface 11, a memory controller 12, a memory module 13 and a buffer memory 14. The connection interface 11 is used to connect to the host system 15 and is, for example, compatible with Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), high-speed peripheral component connection interface (Peripheral Component Interconnect Express, Various connection interface standards such as PCI Express) or Universal Serial Bus (USB).

The memory controller 12 is coupled to the connection interface 11, the memory module 13 and the buffer memory 14. The memory controller 12 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and perform data writing, reading and erasing in the memory module 13 according to the instructions of the host system 15 In addition to other operations. In addition, the memory controller 12 controls the overall operation of the memory device 10.

The memory module 13 is used to store data written by the host system 15. For example, the memory module 13 may include a single level cell (SLC) NAND flash memory module (that is, a flash memory module in which one memory cell can store 1 bit), and a multi-level cell (SLC) NAND flash memory module. Multi-level cell (MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), triple level cell (TLC) NAND flash memory module Flash memory module (that is, a flash memory module that can store 3 bits in a memory cell) and/or a quad level cell (QLC) NAND type flash memory module (that is, one The memory cell can store a 4-bit flash memory module). The buffer memory 14 can be used to temporarily store data received from the host system 15 or data read from the memory module 13.

The host system 15 can store data in the memory device 10 or read data from the memory device 10. For example, the host system 15 is any system that can substantially cooperate with the memory device 10 to store data, such as a computer system, a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, etc., and the memory Device 10 can be a flash drive, a memory card, a solid state drive (SSD), a secure digital (SD) card, a compact flash (CF) card, or an embedded storage device, etc. Non-volatile memory storage device.

FIG. 2 is a schematic diagram of a management memory module according to an embodiment of the present invention. 1 and 2, the memory module 13 includes a plurality of physical blocks 201(0)~201(n) and 202(1)~202(m), and each physical block includes a predetermined number Memory cell. The memory cells in the memory module 13 store data by changing the threshold voltage. For example, multiple memory cells can be programmed in units such as pages to change the threshold voltage of the memory cells. In addition, each physical block can be a minimum erasure unit.

The memory controller 12 can logically divide the physical block (also called the second physical block) 201(1)~201(n) into the usage area 210 and the physical block (also called the first physical block) ) 202(1)~202(m) are logically divided into the reserved area 220. The physical blocks 201(1)~201(n) divided into the usage area 210 can be used normally. For example, when the host system 15 sends a write command to the memory device 10, the memory controller 12 can according to the logical address (such as a logical block address) indicated by the write command. The data is written to the physical block mapped by the logical address in the usage area 210. Alternatively, when the host system 15 sends a read command to the memory device 10, the memory controller 12 can use the logical address (for example, a logical block address) indicated by the read command from the entity mapped from the logical address Read data in the block, and send the read data to the host system 15.

In one embodiment, the physical blocks 201(1) to 201(n) divided into the use area 210 may include physical blocks that have stored user data, free physical blocks that are erased and to be used, A physical block dedicated to storing system data (such as a logical-to-physical mapping table) and/or a spare physical block used to replace a damaged physical block. In addition, at least a part of the capacity of the physical blocks 201(1) to 201(n) divided into the usage area 210 can be provided to the host system 15 to manage the available capacity of the memory device 10.

On the other hand, the memory controller 12 can restrict the physical blocks 202(1) to 202(m) divided into the reserved area 220 to be used only when a power-off command from the host system 15 is received. For example, when the host system 15 detects a power-off signal, the host system 15 can transmit a power-off command to the memory device 10 according to the power-off signal. The memory controller 12 can receive the power-off command via the connection interface 11. According to the power-off command, the memory controller 12 can store the data in the buffer memory 14 to the reserved area 220.

In other words, if the power-off command from the host system 15 is not received, during the operation of the memory device 10, the physical blocks 202(1)~202(m) divided into the reserved area 220 can be continuously prohibited from being used . In this way, it can be ensured that at least most of the physical blocks in the physical blocks 202(1)~202(m) divided into the reserved area 220 are usually idle (that is, they have been erased and have not been programmed) . When a power-off command from the host system 15 is received, the data in the buffer memory 14 can be immediately stored in the physical blocks 202(1)~202(m) divided into the reserved area 220, thereby improving the memory The power-off speed of the device 10.

In an embodiment, the capacity of the physical blocks 202(1)-202(m) divided into the reserved area 220 is not provided to the host system 15 for use. In other words, the host system 15 will not regard the capacity of the physical blocks 202(1) to 202(m) divided into the reserved area 220 as the usable capacity of the memory device 10. In this way, the user data from the host system 15 can be prevented from occupying the capacity of the reserved area 220.

In one embodiment, when the host system 15 detects a power-off signal indicating that the S3, S4, or S5 mode is about to enter the working mode, the host system 15 may send a power-off command to the memory device 10. The memory controller 12 can power off the memory device 10 according to the power off command. In addition, the above-mentioned operation of storing data in the buffer memory 14 to the reserved area 220 may be executed by the memory controller 12 in response to the power-off command and completed before the memory device 10 is actually powered off.

In one embodiment, when the memory device 10 is powered off and powered on again, the memory controller 12 can copy the data stored in the reserved area 220 to the physical block 201 (1 )~201(n). In other words, the reserved area 220 is only used to store the data moved from the buffer memory 14 before the power is off. After the memory device 10 is powered on again, the data in the reserved area 220 can be stored to the originally set physical address in the use area 210 according to the corresponding logical-to-physical mapping relationship. For example, when the memory device 10 is powered on again, the memory controller 12 can query the logical-to-physical mapping table according to the logical address of the data in the reserved area 220 to obtain the physical block mapped by the logical address. Then, the memory controller 12 can copy or move the data from the reserved area 220 to the physical block and instruct the memory module 13 to erase the physical block originally used to temporarily store the data in the reserved area 220. The erased physical blocks in the reserved area 220 can be restored to an idle state for use when the memory device 10 is powered off next time.

In an embodiment, the capacity of the physical blocks 202(1)~202(m) in the memory module 13 divided into the reserved area 220 can account for 1% of the total capacity of all the physical blocks of the memory module 13. % To 28% (for example, 7%), and the present invention is not limited thereto.

FIG. 3 is a flowchart of a memory management method according to an embodiment of the invention. Referring to FIG. 3, in step S301, at least one first physical block in the memory module is divided into a reserved area. In step S302, it is determined whether a power-off instruction is received from the host system. When the power-off instruction is received, in step S303, the data in the buffer memory is stored in the reserved area. In addition, if the power-off instruction is not received, in step S304, the reserved area can be continuously prohibited from being used.

However, each step in FIG. 3 has been described in detail as above, and will not be repeated here. It is worth noting that each step in FIG. 3 can be implemented as multiple program codes or circuits, and the present invention is not limited. In addition, the method in FIG. 3 can be used in conjunction with the above exemplary embodiments, or can be used alone, and the present invention is not limited.

In summary, at least one first physical block of the memory device can be divided into a reserved area. Afterwards, if a power-off command is received from the host system, the data in the buffer memory can be quickly stored to the reserved area to effectively improve the data processing speed and power-off speed of the memory device before power-off .

10: Memory device 11: Connection interface 12: Memory controller 13: Memory module 14: Buffer memory 15: host system 210: Use area 220: reserved area 201(1)~201(n), 202(1)~202(m): physical block S301~S304: steps

FIG. 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a management memory module according to an embodiment of the present invention. FIG. 3 is a flowchart of a memory management method according to an embodiment of the invention.

S301~S304: steps

Claims (10)

A memory management method for a memory device including a buffer memory and a memory module, wherein the memory module includes a plurality of physical blocks, and the memory management method includes: Dividing at least one first physical block of the plurality of physical blocks into a reserved area; Receive a power-off command from a host system; and When the power-off command is received, the data in the buffer memory is stored in the reserved area. The memory management method described in item 1 of the scope of patent application further includes: The at least one first physical block divided into the reserved area is restricted to be used only when the power-off command is received. The memory management method described in item 1 of the scope of patent application further includes: Power off the memory device according to the power off instruction; and When the memory device is powered on again, the data stored in the reserved area is copied to at least one second physical block of the plurality of physical blocks that is not divided into the reserved area. In the memory management method described in claim 1, wherein the capacity of the at least one first physical block divided into the reserved area is not provided to the host system for use. As for the memory management method described in claim 1, wherein the capacity of the at least one first physical block divided into the reserved area accounts for 1% to 28% of the total capacity of the plurality of physical blocks between. A memory device includes: A connection interface for coupling to a host system; A buffer memory; A memory module including multiple physical blocks; and A memory controller coupled to the connection interface, the buffer memory and the memory module, The memory controller is used for dividing at least one first physical block among the plurality of physical blocks into a reserved area, The memory controller is further used to receive a power-off command from the host system via the connection interface, and When receiving the power-off command, the memory controller is further used to store the data in the buffer memory to the reserved area. For the memory device described in item 6 of the scope of patent application, the memory controller is further used to restrict the at least one first physical block divided into the reserved area to be used only when the power-off command is received . According to the memory device described in item 6 of the scope of patent application, the memory controller is further used to power off the memory device according to the power-off command, and After the memory device is powered on again, the memory controller is further used to copy the data stored in the reserved area to at least one second entity in the plurality of physical blocks that is not divided into the reserved area Block. In the memory device described in item 6 of the scope of patent application, the capacity of the at least one first physical block divided into the reserved area is not provided to the host system for use. The memory device described in item 6 of the scope of patent application, wherein the capacity of the at least one first physical block divided into the reserved area accounts for between 1% and 28% of the total capacity of the plurality of physical blocks .

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