TWI790512B - Storage control method and storage system - Google Patents

Abstract

A storage control method and a storage system are disclosed. The method includes: detecting a usage status of a cache buffer region of a storage device; determining a write target region to be a first storage region of the storage device or a second storage region of the storage device according to the usage status of the cache buffer region; if the write target region is determined to be the first storage region, storing a first data from a host system to the first storage region with a buffering of the cache buffer region; and if the write target region is determined to be the second storage region, storing a second data from the host system to the first storage region without the buffering of the cache buffer region.

Description

Storage control method and storage system

The present invention relates to a storage control technology, and in particular to a storage control method and a storage system.

With the evolution of memory storage technology, the use of Solid State Drive (SSD) is becoming more and more popular. Generally, a solid state drive is configured with a cache area and a storage area. The data access speed of memory cells belonging to the cache area is faster, but the storage capacity of each memory cell is smaller. On the contrary, the data access speed of the memory cells belonging to the storage area is relatively slow, but the storage capacity of each memory cell is relatively large. Therefore, when the capacity of the cache area is exhausted, if the data is continuously stored in the solid-state hard disk, the data must be changed to be stored in the storage area of the solid-state hard disk, thereby causing the data storage speed to drop significantly.

The invention provides a storage control method and a storage system, which can improve the data access efficiency of a storage device.

An embodiment of the present invention provides a storage control method, including: detecting the use status of the cache buffer of the storage device; determining the write target area as the storage device according to the use status of the cache buffer The first storage area or the second storage area of the storage device, wherein the data writing speed of the cache buffer is higher than the data writing speed of the second storage area, and all the data writing speeds of the second storage area The data writing speed is higher than the data writing speed of the first storage area; if the write target area is determined to be the first storage area, the first data from the host system will be buffered through the cache stored in the first storage area; and if the write target area is determined to be the second storage area, the first storage area from the host system is not passed through the cache of the cache buffer The second data is stored in the second storage area.

An embodiment of the present invention further provides a storage system, which includes a host system and a storage device. The storage device is coupled to the host system and has a cache buffer, a first storage area and a second storage area. The host system is used to detect the usage status of the cache buffer. The host system is further configured to determine the write target area as the first storage area or the second storage area according to the usage status of the cache buffer. The data writing speed of the cache buffer is higher than the data writing speed of the second storage area. The data writing speed of the second storage area is higher than the data writing speed of the first storage area. If the write target area is determined to be the first storage area, the storage device is used to store the first data from the host system in the first storage after passing through the cache of the cache buffer district. If the write target area is determined to be the second storage area, the storage device is further configured to store the second data from the host system in the second storage area without going through the cache of the cache buffer Two storage areas.

Based on the above, according to the usage state of the cache buffer of the storage device, the write target area can be dynamically determined as the first storage area of the storage device or the second storage area of the storage device. If the write target area is determined to be the first storage area, the first data from the host system can be stored in the first storage area after being cached in the cache buffer. However, if the write target area is determined to be the second storage area, the second data from the host system can be stored in the second storage area without going through the cache of the cache buffer. the second storage area. Wherein the data writing speed of the cache buffer is higher than the data writing speed of the second storage area, and the data writing speed of the second storage area is higher than the data writing speed of the first storage area write speed. Thereby, the data storage efficiency of the storage device can be effectively improved.

FIG. 1 is a functional block diagram of a storage system according to an embodiment of the present invention. Referring to FIG. 1 , the storage system includes a storage device 10 and a host system 11 . The host system 11 is coupled to the storage device 10 and can store data into the storage device 10 or read data from the storage device 10 .

The host system 11 includes a connection interface 111 and a processor 112 . The connection interface 111 is coupled to the processor 112 . The connection interface 111 is used for connecting the storage device 10 . The host system 11 can communicate with the storage device 10 through the connection interface 111 . For example, the connection interface 111 may be compatible with the Serial Advanced Technology Attachment (SATA) standard, the high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) standard, or the Universal Serial Bus (Universal Serial Bus, USB ) standards and other connection interface standards, the present invention is not limited.

The processor 112 can control a part or the whole operation of the host system 11 . For example, the processor 112 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (Digital Signal Processor, DSP), programmable controllers, special Application Specific Integrated Circuits (ASIC), Programmable Logic Device (Programmable Logic Device, PLD) or other similar devices or a combination of these devices.

The storage device 10 includes a connection interface 101 , a controller 102 , a storage module 103 and a storage module 104 . The connection interface 101 is used for connecting the host system 11 . The storage device 10 can communicate with the host system 11 through the connection interface 101 . For example, the connection interface 111 may also conform to connection interface standards such as SATA standard, PCI Express standard, or USB standard, which is not limited in the present invention.

The controller 102 is coupled to the connection interface 101 , the storage module 103 and the storage module 104 . The controller 102 is used for controlling the storage module 103 and the storage module 104 . In addition, the controller 102 can also control the entire or partial operations of the storage device 10 . For example, the controller 102 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic device (PLD) or other similar devices or a combination of these devices.

The storage module 103 is used for storing data written by the host system 11 . It should be noted that the storage unit (also called memory cell) in the storage module 103 stores data by changing the voltage (also called threshold voltage). For example, the storage module 103 may include a solid state drive (SSD) or similar flash memory module.

In one embodiment, the storage module 103 may include a single level cell (single level cell, SLC) NAND flash memory module (that is, a flash memory module in which one memory cell can store 1 bit) , Multi-level cell (MLC) NAND flash memory module (that is, a memory cell can store 2 bits of flash memory module), triple level cell (TLC) NAND-type flash memory module (that is, a memory cell that can store 3 bits of flash memory module), quad level cell (quad level cell, QLC) NAND-type flash memory module (that is, A memory cell can store 4-bit flash memory modules) and/or other types of flash memory modules.

The storage module 103 includes a cache buffer 1031 and a storage area (also called a first storage area) 1032 . The cache buffer 1031 and the storage area 1032 respectively include a plurality of memory cells. Each of these memory cells can be programmed to change its threshold voltage to store a corresponding bit (also called a data bit). A single memory cell in the cache buffer 1031 can store n data bits. A single memory cell in the storage area can be used to store m data bits. Both n and m are positive integers, and m is greater than n. For example, n can be 1 and m can be 2, 3 or 4.

In one embodiment, the memory cells in the cache buffer 1031 store data in a virtual SLC (pSLC) programming mode, and the memory cells in the storage area 1032 store data in a TLC programming mode. In this embodiment, a single memory cell in the cache buffer 1031 can be used to store 1 data bit (ie n=1), and a single memory cell in the storage area 1032 can be used to store 3 data bits (i.e. m=3).

In one embodiment, the memory cells in the cache buffer 1031 store data in the pSLC programming mode, and the memory cells in the storage area 1032 store data in the QLC programming mode. In this embodiment, a single memory cell in the cache buffer 1031 can be used to store 1 data bit (ie n=1), and a single memory cell in the storage area 1032 can be used to store 4 data bits (ie m=4). By analogy, the values of n and m can be adjusted according to the stylized mode adopted, as long as it meets the specification that m is greater than n.

The storage module 104 can also be used to store data written by the host system 11 . For example, the storage module 104 includes a storage area (also referred to as a second storage area) 1041 . The storage area 1041 includes a plurality of storage units. However, it should be noted that, different from the storage module 103, the storage unit in the storage module 104 stores data through magnetic changes. For example, the storage module 104 may include a mechanical hard disk (Hard disk drive, HDD) (also called a traditional hard disk or hard disk drive).

Based on the differences and/or inherent physical differences between the cache buffer 1031, the storage area 1032, and the storage area 1041 for the use of storage units, the data writing speed (or write bandwidth) of the cache buffer 1031 may vary. The data writing speed (or writing bandwidth) of the storage area 1041 is higher than the data writing speed (or writing bandwidth) of the storage area 1041, and the data writing speed (or writing bandwidth) of the storage area 1041 can be higher than the data writing speed (or writing frequency) of the storage area 1032 Width). For example, in one embodiment, the average data writing speed of the cache buffer 1031 may be about 1GB/s, the average data writing speed of the storage area 1041 may be about 140MB/s, and the average data writing speed of the storage area 1032 The input speed can be about 30~50MB/s.

In one embodiment, the processor 112 of the host system 11 can detect the usage status of the cache buffer 1031 . For example, the usage status of the cache buffer 1031 may reflect the current available capacity (also referred to as remaining capacity) in the cache buffer 1031 . For example, assume that the total capacity of the cache buffer 1031 is 2GB. When the cache buffer 1031 stores 1.5 GB of valid data, the available capacity of the cache buffer 1031 is about 0.5 GB. In other words, the more valid data currently stored in the cache buffer 1031 , the smaller the current available capacity in the cache buffer 1031 . Conversely, if the valid data currently stored in the cache buffer 1031 is less, the current available capacity in the cache buffer 1031 is larger.

In one embodiment, the controller 102 of the storage device 10 can continuously update the usage status of the cache buffer 1031 . In addition, the controller 102 can send a notification message to the host system 11 . The notification message can reflect the usage status of the cache buffer 1031 . In other words, the processor 112 of the host system 11 can know the usage status of the cache buffer 1031 (eg, the current available capacity of the cache buffer 1031 ) according to the notification message.

In one embodiment, the processor 112 may determine a write target area as one of the storage area 1032 and the storage area 1041 according to the usage status of the cache buffer 1031 . For example, the target writing area may indicate the target writing location (or target writing disk) of the data (ie, the data to be stored) from the host system. The processor 112 can set the determined write target area to a management table in the storage device 10 . Afterwards, the controller 102 can query the management table to store the data from the host system 11 according to the currently set writing target area.

In one embodiment, it is assumed that the write target area is determined as the storage area 1032 . When the writing target area is the storage area 1032 , the controller 102 can store the data (also referred to as first data) from the host system 11 to the storage area 1032 after being cached in the cache buffer 1031 .

In one embodiment, it is assumed that the write target area is determined as the storage area 1041 . In the state where the write target area is the storage area 1041, the controller 102 can directly store the data (also called the second data) from the host system 11 to the storage area without going through the cache of the cache buffer 1031. District 1041.

In one embodiment, the processor 112 may determine the write target area as one of the storage area 1032 and the storage area 1041 according to the available capacity of the cache buffer 1031 . In one embodiment, the processor 112 may determine whether the available capacity of the cache buffer 1031 is greater than a certain threshold (also referred to as a first threshold). If the available capacity of the cache buffer 1031 is greater than the first threshold, the processor 112 may determine the write target area as the storage area 1032 . On the contrary, if the available capacity of the cache buffer 1031 is not greater than the first threshold value, the processor 112 may not adjust the write target area, that is, maintain the write target area at one of the current storage area 1032 and the storage area 1041 one.

In one embodiment, the processor 112 may determine whether the available capacity of the cache buffer 1031 is smaller than another threshold (also referred to as a second threshold). If the available capacity of the cache buffer 1031 is smaller than the second threshold, the processor 112 may determine the write target area as the storage area 1041 . Conversely, if the available capacity of the cache buffer 1031 is not less than the second threshold value, the processor 112 may not adjust the write target area, that is, maintain the write target area at one of the current storage area 1032 and the storage area 1041 one.

In one embodiment, the first threshold may be about 80%-90% of the total capacity of the cache buffer 1031, and the second threshold may be about 10%-20% of the total capacity of the cache buffer 1031 . In an embodiment, both the first threshold and the second threshold can be other values, as long as the first threshold is greater than the second threshold.

FIG. 2 is a schematic diagram of a path for storing data in a state where the writing target area is the first storage area according to an embodiment of the present invention. Referring to FIG. 2 , the controller 102 can receive data 201 from the host system 11 . When the writing target area is the storage area 1032 (namely the first storage area), the controller 102 can cache the data 201 in the cache buffer 1031 first. For example, the data 201 can be stored in the cache buffer 1031 by pSLC programming mode. Later, the controller 102 can execute a data sorting operation, so as to copy the data 201 to the storage area 1032 through the data sorting operation for a longer period of storage. For example, the data 201 can be stored in the storage area 1032 by TLC or QLC programming mode.

It should be noted that, in the data sorting operation, valid data in the m physical units (or memory cells) in the cache buffer 1031 can be collectively copied to the n physical units (or memory cells) in the storage area 1032 to store in. For example, assuming that a physical unit is a physical page, n=1 and m=4, the valid data in the four physical pages in the cache buffer 1031 can be collectively copied to one physical page in the storage area 1032 for storage . Thereafter, the data in the four physical pages in the cache buffer 1031 can be marked as invalid and waiting to be erased. After the four physical pages are erased, the storage space of the four physical pages can be regarded as a part of the available capacity of the cache buffer 1031 . In other words, in one embodiment, the controller 102 can reduce the amount of valid data in the cache buffer 1031 and increase the available capacity of the cache buffer 1031 through the data sorting operation.

FIG. 3 is a schematic diagram of a path for storing data in a state where the writing target area is the second storage area according to an embodiment of the present invention. Referring to FIG. 3 , the controller 102 can receive data 301 from the host system 11 . When the writing target area is the storage area 1041 (ie, the second storage area), the controller 102 can directly store the data 301 in the storage area 1041 for long-term preservation. In particular, when the writing target area is the storage area 1041 , the data 301 does not need to be cached in the cache buffer 1031 before being stored in the storage area 1041 , as shown in FIG. 3 .

It should be noted that the data writing path shown in the embodiment of FIG. 2 is that the available capacity of the cache buffer 1031 is relatively sufficient (for example, the available capacity of the cache buffer 1031 is greater than or between the first threshold and the second threshold value) in the case of the data writing path. In this state, for the host system 11 , the writing speed of the data (for example, the data 201 ) can be about the average data writing speed of the cache buffer 1031 (for example, 1 GB/s).

However, the data writing path shown in the embodiment of FIG. 3 is that the available capacity of the cache buffer 1031 is relatively insufficient (for example, the available capacity of the cache buffer 1031 is less than the second threshold value or between the first threshold value and the second threshold value. The data writing path in the case of between two thresholds). In this state, for the host system 11 , the writing speed of the data (for example, the data 301 ) can still be roughly maintained at the average data writing speed of the storage area 1041 (for example, 140MB/s).

In one embodiment, when the available capacity of the cache buffer 1031 is relatively insufficient or even completely used up, if the write target area is not adjusted to the storage area 1041 (that is, the write target area is continuously set to the storage area 1032 ), the controller 102 skips the cache buffer 1031 and directly stores the data in the storage area 1032 in TLC or QLC programming mode. At this time, for the host system 11 , the data writing speed may drop to the average data writing speed of the storage area 1032 (for example, 30-50 MB/s). In other words, at this time, the host system 11 may obviously detect that the writing speed of the storage device 10 has dropped significantly, thereby causing a bad user experience. However, this situation can be effectively avoided by the control mechanism of the embodiment shown in FIG. 2 and FIG. 3 .

In one embodiment, when the cache buffer 1031 (or the storage module 103) is in an idle state (for example, when the write target area is the storage area 1041 and/or the controller 102 directly stores the data 301 to the storage area 1041 ), the controller 102 may perform the aforementioned data collation operation on the cache buffer 1031 to increase the available capacity of the cache buffer 1031 . After increasing the available capacity of the cache buffer 1031, when a preset condition is met (for example, the available capacity of the cache buffer 1031 is greater than the first threshold value), the processor 112 can adjust the write target area to the storage area 1032 again , so as to increase the writing speed of subsequent data.

In one embodiment, the storage device 10 has both a solid state disk (such as the storage module 103 ) and a mechanical hard disk (such as the storage module 104 ). Therefore, in an embodiment, the storage device 10 may also be called a hybrid hard disk or a composite hard disk.

FIG. 4 is a flowchart of a storage control method according to an embodiment of the invention. Referring to FIG. 4 , in step S401 , the usage status of the cache buffer of the storage device is detected. In step S402, the write target area is determined as the first storage area of the storage device or the second storage area of the storage device according to the usage status of the cache buffer, wherein the cache buffer The data writing speed of the area is higher than the data writing speed of the second storage area, and the data writing speed of the second storage area is higher than the data writing speed of the first storage area. If the write target area is determined to be the first storage area, in step S403, the first data from the host system is stored in the first storage area after being cached in the cache buffer. If the write target area is determined to be the second storage area, in step S404, store the second data from the host system in the second storage area without going through the cache of the cache buffer district.

FIG. 5 is a flow chart of a storage control method according to an embodiment of the invention. Please refer to FIG. 5 , in step S501 , the available capacity of the cache buffer of the storage device is detected. In step S502, it is determined whether the available capacity of the cache buffer is greater than a first threshold. If the available capacity of the cache buffer is larger than the first threshold, in step S503, the write target area is determined as the first storage area of the storage device. In step S504, the first data from the host system is stored in the first storage area after being cached in the cache buffer.

If the available capacity of the cache buffer is not greater than the first threshold, in step S505, it is determined whether the available capacity of the cache buffer is less than the second threshold. If the available capacity of the cache buffer is smaller than the second threshold, in step S506, the write target area is determined as the second storage area of the storage device. In step S507, the second data from the host system is stored in the second storage area without going through the cache of the cache buffer. In addition, if it is determined in step S505 that the available capacity of the cache buffer is not less than the second threshold value, then the currently set write target area may not be adjusted (that is, the current write target area setting is maintained).

However, each step in FIG. 4 and FIG. 5 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 4 and FIG. 5 can be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods shown in FIG. 4 and FIG. 5 can be used together with the above exemplary embodiments, or can be used alone, which is not limited by the present invention.

To sum up, the write target area in the storage device can be dynamically determined as the first storage area or the second storage area according to the usage status of its cache buffer. If the write-in target area is determined as the first storage area, the first data from the host system can be stored in the first storage area after being cached in the cache buffer. However, if the write target area is determined to be the second storage area, the second data from the host system can be directly stored in the second storage area without going through the cache of the cache buffer. In this way, the traditional problem of greatly reducing the data storage speed of the storage device due to the exhaustion of the cache area of the solid-state hard disk (or flash memory) can be effectively improved and/or the data access efficiency of the storage device can be improved.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: storage device 11: Host system 101, 111: connection interface 112: Processor 10: storage device 102: Controller 103, 104: storage module 1031: cache buffer 1032, 1041: storage area 201, 301: Information S401~S404, S501~S507: steps

FIG. 1 is a functional block diagram of a storage system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a path for storing data in a state where the writing target area is the first storage area according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a path for storing data in a state where the writing target area is the second storage area according to an embodiment of the present invention. FIG. 4 is a flowchart of a storage control method according to an embodiment of the invention. FIG. 5 is a flow chart of a storage control method according to an embodiment of the invention.

S401~S404: steps

Claims (10)

A storage control method, comprising: detecting an available capacity of a cache buffer of a storage device; in response to the available capacity being greater than a first threshold, passing a first data from a host system through the cache buffer and store a second data from the host system in the storage without going through the cache of the cache buffer in response to the available capacity being less than a second threshold A second storage area of the device, wherein the data writing speed of the cache buffer is higher than the data writing speed of the second storage area, and the data writing speed of the second storage area is higher than that of the first storage area data writing speed. The storage control method as described in claim 1, further comprising: in response to the available capacity being greater than the first threshold value, determining a write target area as the first storage area; and in response to the available capacity being smaller than the second A threshold value is used to determine the writing target area as the second storage area, wherein the first threshold value is greater than the second threshold value. The storage control method as described in Claim 1 further includes: sending a notification message from the storage device to the host system, wherein the notification message reflects the usage status of the cache buffer. The storage control method as described in claim 1, further comprising: In response to the available capacity being less than the second threshold, during the period of storing the second data from the host system in the second storage area, performing a data defragmentation operation on the cache buffer to increase the cache The available capacity of the buffer. The storage control method as described in claim 1, wherein the storage unit in the cache buffer and the first storage area stores data by changing the voltage, and the storage unit in the second storage area stores data by changing the voltage. Magnetic changes to store data. A storage system, comprising: a host system; and a storage device coupled to the host system and having a cache buffer, a first storage area and a second storage area, wherein the host system is used to detect the An available capacity of the cache buffer, in response to the available capacity being greater than a first threshold, the storage device is used to store a first data from the host system into the first storage after passing through the cache of the cache buffer area, in response to the available capacity being less than a second threshold value, the storage device is further configured to store a second data from the host system in the second storage area without going through the cache of the cache buffer, and the cache The data writing speed of the fetch buffer is higher than the data writing speed of the second storage area, and the data writing speed of the second storage area is higher than the data writing speed of the first storage area. The storage system as claimed in claim 6, wherein: in response to the available capacity being greater than the first threshold, the storage device is further configured to A write target area is determined as the first storage area; and in response to the available capacity being less than the second threshold value, the storage device is further used to determine the write target area as the second storage area, wherein the first The threshold value is greater than the second threshold value. The storage system according to claim 6, wherein the storage device is further configured to send a notification message to the host system, and the notification message reflects the usage status of the cache buffer. The storage system as claimed in claim 6, wherein in response to the available capacity being less than the second threshold value, during storing the second data from the host system in the second storage area, the storage device is further used for A data cleaning operation is performed on the cache buffer to increase the available capacity of the cache buffer. The storage system according to claim 6, wherein the cache buffer and the storage units in the first storage area store data by changing the voltage, and the storage units in the second storage area store data by magnetic Changes to store data.

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