TWI810876B - Method and computer program product and apparatus for data access in response to host discard commands - Google Patents

Abstract

The invention is related to a method, a computer program product, and an apparatus for executing host discard commands. The method includes: allocating space in a random access memory (RAM) to store an extended discard table including multiple entries each records a logical address of user data that has been discarded; receiving a host discard command, which indicates a first logical address of user data that is discarded, from a host side; appending a new entry including the first logical address to the extended discard table; and setting a start-address register and an end-address register in a performance engine to redefine an address arrange that holds the extended discard table in the RAM. By using the installation of the performance engine with the usage of the extended discard table, it avoids the processing unit to consume excessive computation resource to determine if a logical address of user data that is to be written, which is advised by a host write command, or a logical address of user data that is to be read, which is advised by a host read command, falls within logical address ranges that have been discarded.

Description

Data access method and product computer program and device in response to host discard command

The invention relates to a storage device, in particular to a data access method, a product computer program and a device in response to a host discarding command.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address for accessing NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of NOR flash memory in time. material. In contrast, NAND flash memory is not random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the CPU needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , read, write, discard, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory). In order to improve the execution performance of the flash memory controller, the present invention proposes a data access method, product computer program and device in response to host discarding commands.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem to be solved.

This specification relates to a data access method in response to a host discarding command, executed by a processing unit, including: configuring space in a random access memory for an extended discarding table, including a plurality of items, and each item records that it has been discarded The logical address of the user data; receive the host discard command from the host end, point out the first logical address of the user data that is no longer used; add a new item including the first logical address to the extended formula discarding table; and setting a start address register and an end address register in the performance engine for redefining the address range of the extended discard table stored in the random access memory, so that the performance engine borrows The extended discard table is searched from the address range in the random access memory to determine whether the user data of a specific logical address is no longer used.

This manual also relates to a computer program product, including program codes. When the processing unit executes the program code, the above-mentioned data access method in response to the host discarding command is implemented.

The specification further relates to a data access device for responding to a host discarding a command, including: a random access memory; a performance engine; and a processing unit. The random access memory is used to allocate space for the extended discard table, which includes a plurality of entries, and each of the entries records the logical address of the discarded user data. The performance engine includes a start address register and an end address register, which are used to define an address range in the random access memory for storing the extended discard table. The processing unit is used for receiving a host discarding command from the host end, which indicates a first logical address of the user data that is no longer used; adding a new item including the first logical address to the extended discarding table; and Setting the start address register and the end address register in the performance engine is used to redefine the address range of the extended discard table stored in the random access memory, so that the performance The engine searches the extended discard table in the address range of the random access memory to determine whether the user data of a specific logical address is no longer used.

One of the advantages of the above-mentioned embodiment is that through the setting of the performance engine and the use of the extended discard table, it is avoided that the processing unit consumes too much computing resources to judge the logical address of the user data to be written by the host write command or the host reads the data. Whether the logical address of the user data to be read by the command falls within the previously discarded logical address range.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

The following description is a preferred implementation mode of the invention, and its purpose is to describe the basic spirit of the invention, but not to limit the invention. For the actual content of the invention, reference must be made to the scope of the claims that follow.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, components and/or components, but do not exclude the possibility of adding More technical characteristics, numerical values, method steps, operation processes, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a priority order, a pre-relationship, or an element An element preceding another element, or a chronological order in performing method steps, is only used to distinguish elements with the same name.

It must be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements may be interpreted in a similar fashion, eg, "between" versus "directly between," or "adjacent" versus "directly adjacent," and so forth.

Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110 , a flash memory controller 130 and a flash memory module 150 , and the flash memory controller 130 and the flash memory module 150 may be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, notebook computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The host interface (Host Interface) 137 of the host terminal 110 and the flash memory controller 130 can be Universal Serial Bus (Universal Serial Bus, USB), advanced technology attachment (advanced technology attachment, ATA), serial advanced technology attachment (serial advanced technology attachment, SATA), peripheral component interconnect express (PCI-E), universal flash memory storage (Universal Flash Storage, UFS), embedded multimedia card (Embedded Multi-Media Card, eMMC) and other communication protocols communicate with each other. The flash memory interface (Flash Interface) 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other through a double data rate (Double Data Rate, DDR) protocol, for example, open NAND flash (Open NAND Flash Interface, ONFI), dual Double data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in various ways, such as using general-purpose hardware (for example, a single processor, multiple processors with parallel processing capabilities, graphics processing units, or other processors with computing capabilities), and The functions described later are provided when the software and/or firmware instructions are executed. The processing unit 134 receives host commands through the host interface 131, such as read commands (Read Command), write commands (Write Command), discard commands (Discard Command), erase commands (Erase Command), etc., schedule and execute these commands . The flash controller 130 further includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, used to configure the space as a data buffer, store user data (also called host data) that is read from the host end 110 and will be written into the flash memory module 150, and read from the flash memory module 150. The group 150 reads and outputs user data to the host 110 . The random access memory 136 can also store data needed during execution, such as variables, data tables, host-to-flash address mapping table (H2F table for short), flash memory and host address Comparison table (Flash-to-Host Address Mapping Table, F2H table for short), etc. The flash memory interface 139 includes a NAND flash memory controller (NAND Flash Controller, NFC), which provides functions required for accessing the flash memory module 150, such as command sequencer (Command Sequencer), low density parity check (Low Density Parity Check, LDPC) wait.

In some embodiments, the processing unit 134 can comply with eMMC specifications, such as Section 6.6.12 of EMBEDDED MULTI-MEDIA CARD (e MMC), ELECTRICAL STANDARD (5.1) published in January 2019, through the host interface 131 A discard command (Discard Command) is received from the host 110 . In some other embodiments, the processing unit 134 can comply with the UFS specification, such as section 11.3.26 of UNIVERSAL FLASH STORAGE (UFS), Version 3.1 published in January 2020, and receives the release from the host terminal 110 through the host interface 131. Mapping command (UNMAP Command). If the parameter "bProvisioningType" of the unit descriptor (Unit Descriptor) in the unmap command is set to "02h", it means that this is a discard command. The host end 110 can send the above-mentioned host discarding command to the flash memory controller 130, in order to point out the logical address of the user data that is no longer used, such as the main page number (Host Page Number), logical block address ( Logical Block Address, LBA) and other means. Different from the host erase command, when the flash memory controller 130 executes the host discard command, it does not need to physically erase the memory unit used to store the data at the specified logical address, but only needs to mark the data at the logical address no longer exist. When appropriate, the flash memory controller 130 executes a garbage collection program to collect and erase the physical memory unit corresponding to the marked logical address.

A bus architecture (Bus Architecture) 132 can be configured in the flash memory controller 130 for coupling components to transmit data, addresses, control signals, etc. These components include a host interface 131, a processing unit 134, a RAM 136, A performance engine (Performance Engine) 137, a direct memory access (Direct Memory Access, DMA) controller 138, a flash memory interface 139, and the like. In some embodiments, the host interface 131 , the processing unit 134 , the RAM 136 , the performance engine 137 , the DMA controller 138 and the flash memory interface 139 may be coupled to each other through a single bus. In other embodiments, a high-speed bus can be configured in the flash memory controller 130 for coupling the processing unit 134, the performance engine 137, the DMA controller 138, and the RAM 136 to each other, and a low-speed bus can be configured for processing The unit 134 , the DMA controller 138 , the host interface 131 and the flash memory interface 139 are coupled to each other. The DMA controller 138 can move data between components through the bus structure 132 according to the instructions of the processing unit 134, for example, move the data of a specific data buffer (Data Buffer) in the host interface 131 or the flash memory interface 139 to the RAM 136 specific address, move the data of the specific address in the RAM 136 to the specific data register in the host interface 131 or the flash memory interface 139 .

A bus comprises parallel physical wires connecting two or more components in flash memory controller 130 . A bus is a shared transmission medium. At any one time, only two devices can use these lines to communicate with each other and transfer data. Data and control signals can travel bidirectionally along the data and control lines respectively between components, but on the other hand, address signals can only travel unidirectionally along the address lines. For example, when the processing unit 134 wants to read data at a specific address of the RAM 136 , the processing unit 134 transmits the address to the RAM 136 on the address line. Then, the data at this address will be returned to the processing unit 134 on the data line. In order to complete the data reading operation, the control signal will be transmitted using the control line.

The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (Gigabytes, GB), or even several terabytes (Terabytes, TB), for storing a large amount of user data, Such as high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array can include single-level cells (Single Level Cells, SLCs), multi-level cells (Multiple Level Cells, MLCs) and triple-level cells (Triple Level Cells). Level Cells, TLCs), four-level cells (Quad-Level Cells, QLCs), or any combination of the above. The processing unit 134 writes user data to a designated address (destination address) in the flash memory module 150 through the flash memory interface 139 , and reads user data from a designated address (source address) in the flash memory module 150 . The flash memory interface 139 uses several electronic signals to coordinate data and command transmission between the flash memory controller 130 and the flash memory module 150 , including a data line (Data Line), a clock signal (Clock Signal) and a control signal (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to FIG. 2, the interface 151 in the flash memory module 150 may include four input and output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each of which is connected to four NAND flash memory units, for example, the channel CH#0 is connected to NAND flash memory units 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory unit can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11 , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in parallel, or write user data to the enabled NAND flash memory unit.

In some previous embodiments, the flash memory controller 130 may allocate space in the RAM 136 for a discard queue (Discard Queue). The discard queue includes a plurality of nodes, and each node is used to store information of a logical address range for discarding user data indicated by a host discard command. Table 1 shows a sample discard queue: Table 1 node number start address length 0 P#100 32 1 P#200 4 2 P#300 64 3 P#500 8 For example, each node stores the starting main page number and length indicated by a discard command. The 0th to 3rd example nodes mentioned above contain the following information. The previously received 4 discard commands respectively instruct the main page P#100~P#131, P#200~P#203, P#300~ The user data of P#363 and P#500~P#507 are discarded. However, each time the processing unit 134 receives the host read command from the host terminal 110 through the host interface 131 , it needs to spend computing resources to search the discard queue to determine whether the user data to be read by the host read command has been discarded. If the read user data has been discarded, the processing unit 134 replies to the host 110 with an error message or a dummy value (Dummy Value) through the host interface 131 . When the processing unit 134 receives the host write command from the host terminal 110 through the host interface 131 each time, it also needs to spend computing resources to search the discard queue to determine whether the logical address of the user data to be written by the host write command falls. Enter a previously discarded logical address range.

In order to reduce the burden on the processing unit 134 to improve the overall performance of the flash memory controller 130, the flash memory controller 130 can allocate space in the RAM 136 for an expanded discard table (Expanded Discard Table), and use a dedicated performance engine 137 to search the expanded discard table. Drop table. The extended discard list can contain 1024 items, and each item records the logical address of discarded user data, or a null value (NULL value). It should be noted that those skilled in the art can configure more or less space in the RAM 136 to store the extended discard table according to the needs of the system, and the present invention is not limited to only containing 1024 items in the extended discard table. Table 2 shows an example extended drop table: Table 2 item number logical address 0 P#100 1 P#101 : : 31 P#131 32 P#200 33 P#201 34 P#202 35 P#203 36 P#300 37 P#301 : : 99 P#363 100 P#500 101 P#501 : : 107 P#507 Compared with Table 1, conceptually, the information of the 0th item in Table 1 can be expanded into the 0th to 31st items in Table 2, respectively recording the main page numbers P#100 to P#131; Table 1 The information of the first item in Table 2 can be expanded into the 32nd to 35th items in Table 2, recording the main page numbers P#200 to P#203 respectively, and so on. The processing unit 134 can perform sorting when adding items to the extended discard table according to the information carried in the host discard command, so that the logical addresses can be arranged in ascending or descending exponents, so as to facilitate the dedicated performance engine 137 to search.

Refer to Figure 3. The performance engine 137 may include a start address register 322 and an end address register 324 for enabling the processing unit 134 to define an address range of the extended discard table in the RAM 136 . Since the number of items stored in the extended discard list is variable, whenever the content of the extended discard table is updated, the processing unit 134 will reset the start address register 322 and the end address register 324 for searching Circuitry 310 is capable of searching within the address range of RAM 136 specified by start address register 322 and end address register 324 . For example, corresponding to the contents of Table 2, the start address register 322 stores the memory address “ExpDiscardTable_start”, and the end address register 324 stores ExpDiscardTable_star+107. The performance engine 137 may include eight target registers 330#0˜330#7 for instructing the processing unit 134 to instruct the search circuit 310 to search up to eight main page numbers in the extended drop list. The performance engine 137 may include eight result registers 350#0~350#7 for allowing the search circuit 310 to respectively store search results corresponding to the target registers 330#0~330#7. For example, the result register 350#0 stores the search result of the main page number indicated by the target register 330#0, the result register 350#1 stores the search result of the main page number indicated by the target register 330#1, and so on. For example, the result register can be a 16-bit register, wherein the 15th bit stores the information of whether it is a hit, and if it is a hit, the 14th to 0th bits store the number of the hit item in the extended discard table. The processing unit 134 can read the value of any one of the result registers 350#0~350#7 to obtain the information whether the main page number in the corresponding target register appears in the extended discard table, and, if it is hit, the main page number Which item in the extended discard table the number exists in. It should be noted that those skilled in the art can configure more or fewer pairs of target registers and result registers in the performance engine 137 according to the needs of the system, and the present invention is not limited to only containing eight pairs of target registers in the performance engine 137. register and result register. Those skilled in the art can use known circuits to implement the search circuit 310, which is used to allow the search circuit 310 to complete linear search (Linear Search), binary search (Binary Search), exponential search (Exponential Search) in the extended discard table. ), Fibonacci Search, etc.

In some embodiments, a dedicated wire connection can be used between the processing unit 134 and the performance engine 137, so that the processing unit 134 can set the start address register 322, the end address register 324 and the target register 330#0~330 through the dedicated wire #7, and read the search results from the result registers 350#0~350#7.

In some other embodiments, the processing unit 134 can set the start address register 322, the end address register 324 and the target register 330#0~330#7 in the performance engine 137 through the shared bus architecture 132, and from the performance engine The result registers 350#0~350#7 in 137 read the search results.

In some embodiments, a dedicated wire connection can be used between the performance engine 137 and the RAM 136, so that the performance engine 137 can read the value of a specific address in the RAM 136 through the dedicated wire.

In other embodiments, the performance engine 137 can read the value of a specific address in the RAM 136 through the shared bus architecture 132 and the DAM controller 138 .

In response to the technical solution of the extended discard table and the performance engine 137, an embodiment of the present invention proposes a method for executing a host discard command, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly for processing the host drop command received from the host side 110 . Referring to Figure 4, the detailed steps are as follows:

Step S410 : Receive the first (next) host discard command from the host 110 through the host interface 131 , the host discard command is used to indicate the logical address of the user data that is no longer used.

Step S420: Update the content of the extended discard table stored in the RAM 136 according to the logical address of the discarded user data indicated by the host discard command. Items in the updated extended discard table are sorted in ascending or descending order according to logical addresses.

Step S430: Set the start address register 322 and the end address register 324 in the performance engine 137 according to the updated extended discard table.

Assume that before the execution of step S420 in a loop, the extended discard table is as shown in Table 2: when the processing unit 134 receives the user data indicating to discard the main pages P#400~P#403 (step S410), the table The extended discard table of 2 can be updated as shown in Table 3 below (step S420): Table 3 item number logical address 0 P#100 1 P#101 : : 31 P#131 32 P#200 33 P#201 34 P#202 35 P#203 36 P#300 37 P#301 : : 99 P#363 100 P#400 101 P#401 102 P#402 103 P#403 104 P#500 105 P#501 : : 111 P#507 Next, the processing unit 134 sets the end address register 324 to ExpDiscardTable_star+111 (step S430 ).

In response to the technical solution of the extended discard table and the performance engine 137, the embodiment of the present invention proposes a method for updating the extended discard table after the host write command is executed, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions . This method is executed iteratively to adaptively update the extended drop table after each host write command is executed. Referring to Figure 5, the detailed steps are as follows:

Step S510 : Execute the first (next) host write command for writing the user data of the specified logical address into the flash memory module 150 through the flash memory interface 139 .

Step S520: Determine whether the logical address written in the user data appears in the extended discard list. If yes, the flow continues to the processing of step S530; otherwise, the flow continues to the processing of step S510. The processing unit 134 can set the logical addresses to the target registers 330#0~330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0~330#7 and drives the performance engine 137, it can proceed to process other tasks. After a preset period of time, the processing unit 134 checks the result registers 350#0~350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard list. After all the logical addresses are judged, the processing unit 134 proceeds to the next step.

Step S530: Delete the corresponding item of the logical address appearing in the extended discard table.

Step S540: Set the end address register 324 in the performance engine 137 according to the updated extended discard table.

Assume that before the execution of step S510 in a loop, the extended discard table is as shown in Table 2: when the processing unit 134 finishes executing the host write command of the user data of the main pages P#200~P#203 (step S510 ), the processing unit 134 sets the logical addresses P#200~P#203 to the target registers 330#0~330#3 in the performance engine 137, and drives the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended drop list (step S520). When it is found that the logical addresses P#200~P#203 all appear in the extended discard table (the path of "Yes" in step S520), the processing unit 134 can update the extended discard table as shown in Table 4 below (step S530) : Table 4 item number logical address 0 P#100 1 P#101 : : 31 P#131 32 P#300 33 P#301 : : 95 P#363 96 P#500 97 P#501 : : 103 P#507 Next, the processing unit 134 sets the end address register 324 to ExpDiscardTable_star+103 (step S540 ).

In response to the technical solution of the extended discard table and the performance engine 137, an embodiment of the present invention proposes a method for executing a host read command, which is implemented when the processing unit 134 loads and executes related firmware or software instructions. This method is executed repeatedly, and is used to selectively reply false data or real user data to the host end 110 according to the content of the extended discard table when each host read command is executed. Referring to Figure 6, the detailed steps are as follows:

Step S610: extracting the first (next) host write command, instructing the flash memory controller 130 to read the user data at the specified logical address.

Step S620: Determine whether any logical address of the user data to be read appears in the extended discard list. If yes, the process continues to step S630; otherwise, the process continues to step S640. The processing unit 134 can set the logical addresses to the target registers 330#0~330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0~330#7 and drives the performance engine 137, it can proceed to process other tasks. After a preset period of time, the processing unit 134 checks the result registers 350#0~350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard table. After all the logical addresses are judged, the processing unit 134 proceeds to the next step.

Step S632 : For the logical addresses appearing in the extended drop list, the drive host interface 131 returns a false value to the host 110 .

Step S634 : drive the flash memory interface 139 to read user data of other logical addresses that do not appear in the extended discard list from the flash memory module 150 , and drive the host interface 131 to reply the read user data to the host 110 .

Step S640 : drive the flash memory interface 139 to read the user data of the specified logical address from the flash memory module 150 , and drive the host interface 131 to reply the read user data to the host 110 .

In some embodiments, flash controller 130 may allocate space in RAM 136 for an extended drop table and drop queue. If the logical address length of the discarded user data indicated by a master discard command exceeds or is equal to the specified number (for example, when it exceeds or is equal to 32), store the information carried in the master discard command in a node in the discard queue . If the logical address length of discarded user data indicated by a host discard command is less than a specified number, the information carried in the host discard command is stored in one or more consecutive items in the extended discard table. For example, when the previously received 4 discard commands respectively instruct the users of the main pages P#100~P#131, P#200~P#203, P#300~P#363 and P#500~P#507 When data is discarded, the information indicated by these 4 discard commands will be recorded in the discard queue shown in Table 5 below and the extended discard table shown in Table 6 below: Table 5 node number start address length 0 P#100 32 1 P#300 64 Table 6 item number logical address 0 P#200 1 P#201 2 P#202 3 P#203 4 P#500 5 P#501 : : 11 P#507

In response to the technical solutions of the discard queue, the extended discard table, and the performance engine 137, the embodiment of the present invention proposes a method for executing a host discard command, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly for processing the host drop command received from the host side 110 . With reference to Fig. 7, its difference with Fig. 4 is that Fig. 7 inserts the judgment of step S710 after step S410, and adds the processing of step S720 after the judgment is established, detailed description is as follows:

Step S710: Determine whether the logical address length of the discarded user data indicated by the host discard command exceeds or equals a specified number (for example, 32). If yes, the process continues to step S720; otherwise, the process continues to step S420.

Step S720: Update the content of the discard queue stored in the RAM 136 according to the logical address of the discarded user data indicated by the host discard command.

For technical details of steps S410 to S430 in FIG. 7 , reference may be made to the corresponding description in FIG. 4 , and details are not repeated for simplicity.

In response to the technical solutions of the discard queue, the extended discard table, and the performance engine 137, the embodiment of the present invention proposes a method for updating the discard queue and the extended discard table after the host write command is executed, which is loaded and executed by the processing unit 134 It is implemented when related firmware or software commands are used. This method is iteratively used to adaptively update the discard queue and the extended discard table after each host write command is executed. Referring to FIG. 8 , the difference between it and FIG. 5 is that in FIG. 8 , the judgment of step S810 is added after step S510 , and the processing of step S820 is added after the judgment is established. The details are as follows:

Step S810: Determine whether the logical address for writing the user data appears in the discarding queue. If yes, the flow continues to the processing of step S820; otherwise, the flow continues to the processing of step S510.

Step S820: Update the content in the discard queue to reflect the execution result of the host write command. Assume that before the execution of step S510 in a loop, the discard queue is as shown in Table 5: when the processing unit 134 finishes executing the host write command of the user data of the main page P#100~P#131 (step S510) , the processing unit 134 can delete the 0th node in the discard queue and become as shown in Table 7 below (step S820): Table 7 node number start address length 0 P#300 64

For the technical details of steps S510, S530 to S430 in FIG. 8, reference may be made to the corresponding description in FIG. 5, which will not be repeated for simplicity. It should be noted here that, with the assistance of the performance engine 137 , the operations of steps S520 to S540 can be performed in parallel with the operations of steps S810 to S820 .

In response to the technical solutions of the discard queue, the extended discard table, and the performance engine 137, an embodiment of the present invention proposes a method for executing a host read command, which is implemented when the processing unit 134 loads and executes related firmware or software instructions. This method is executed repeatedly, and is used to selectively reply false data or real user data to the host end 110 according to the content of the discard queue and the extended discard table when each host read command is executed. Referring to FIG. 9, the difference between it and FIG. 6 is that it replaces steps S620, S632, and S634 in FIG. 6 with steps S910, S922, and S924 respectively, and the details are as follows:

Step S910: Determine whether the logical address of the user data to be read appears in at least one of the extended drop list and the drop queue. If yes, the process continues to step S922; otherwise, the process continues to step S640. The processing unit 134 can set the logical addresses to the target registers 330#0~330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0~330#7 and drives the performance engine 137, it can then search the discard queue to determine whether these logical addresses appear in the discard queue. After a preset period of time, the processing unit 134 checks the result registers 350#0~350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard table. After all the logical addresses are judged, the processing unit 134 proceeds to the next step.

Step S922 : For each logical address appearing in the extended discard list or the discard queue, the driving host interface 131 returns a false value to the host 110 .

Step S924: drive the flash memory interface 139 to read user data of other logical addresses that do not appear in the extended discard list and discard queue from the flash memory module 150, and drive the host interface 131 to reply the read user data to the host terminal 110.

All or part of the steps in the method of the present invention can be implemented by computer instructions, such as a firmware translation layer (Firmware Translation Layer, FTL) in a storage device, a driver program for specific hardware, and the like. In addition, it can also be implemented in other types of programs. Those skilled in the art can write the methods of the embodiments of the present invention into computer instructions, which will not be described again for the sake of brevity. The computer instructions implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable medium, such as DVD, CD-ROM, USB disk, hard disk, and can also be placed through a network (for example, the Internet, or other appropriate means of accessing a web server.

Although the elements described above are included in FIGS. 1 to 3 , it is not excluded that more additional elements may be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts in FIG. 4 to FIG. 9 are executed in a specified order, those skilled in the art can modify the order of these steps under the premise of achieving the same effect without violating the spirit of the invention. Therefore, The invention is not limited to using only the sequence described above. In addition, those skilled in the art may also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereby.

Although the present invention is described using the above examples, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, the invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

10: Electronic device 110: Host side 130: Flash memory controller 131: host interface 132: busbar 134: processing unit 136: random access memory 137: Performance engine 138: Direct memory access controller 139: Flash interface 150: Flash memory module 151: interface 153#0~153#15: NAND flash memory unit CH#0~CH#3: channel CE#0~CE#3: enable signal 310: search circuit 322: start address register 324: End address register 330#0~330#7: target register 350#0~350#7: result register S410~S430: method steps S510~S540: method steps S610~S640: method steps S710~S720: method steps S810~S820: method steps S910~S924: method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the invention.

FIG. 3 is a block diagram of a performance engine and a random access memory according to an embodiment of the present invention.

Fig. 4 is a flowchart of a method for executing a host discard command according to an embodiment of the present invention.

FIG. 5 is a flowchart of a method for updating an extended discard table after a host write command is executed according to an embodiment of the present invention.

FIG. 6 is a flow chart of a method for executing a host read command according to an embodiment of the invention.

Fig. 7 is a flowchart of a method for executing a host discard command according to an embodiment of the present invention.

FIG. 8 is a flow chart of a method for updating a discard command and an extended discard table after a host write command is executed according to an embodiment of the present invention.

FIG. 9 is a flowchart of a method for executing a host read command according to an embodiment of the invention.

S410~S430: method steps

Claims (15)

A data access method in response to a host discarding command, executed by a processing unit, comprising: Allocate space in the random access memory for an extended discard table, wherein the extended discard table includes a plurality of items, and each of the items records the logical address of the user data that has been discarded; receiving a host discard command from the host end, wherein the host discard command indicates a first logical address of user data that is no longer used; adding a new entry including the first logical address to the extended discard table; and Setting the start address register and the end address register in the performance engine is used to redefine the address range of the extended discard table stored in the random access memory, so that the performance engine can The address range in the random access memory searches the extended discard table to determine whether the user data of a specific logical address is no longer used. The data access method in response to the discard command of the host as claimed in claim 1, wherein the plurality of entries in the extended discard table are arranged in ascending or descending exponentiation according to the logical address. The data access method in response to the host discarding command as described in claim 1, comprising: Executing a host write command to write user data at the second logical address to the flash memory module; and When the second logical address appears in the extended drop table, delete the item containing the second logical address from the extended drop table, and according to the updated extended drop table Set the end address register in the performance engine to redefine the address range of the extended discard table stored in the random access memory. The data access method in response to the host discarding command as described in claim 1, comprising: receiving a host read command from the host end, wherein the host read command indicates to read user data at the third logical address; and When the third logical address appears in the extended discard list, reply false data to the host. The data access method in response to the host discarding command as described in claim 1, comprising: Allocating space in the random access memory for the discarding queue, wherein the discarding queue includes a plurality of nodes, and each of the nodes is used to store a logical address range of discarded user data; judging whether the number of the first logical addresses of the unused user data indicated by the host discard command exceeds or equals a specified number; When the number of the first logical address exceeds or is equal to the specified number, add a new item including the first logical address to the extended discard table, and set the performance engine in The start address register and the end address register are used to redefine the address range of the extended discard table stored in the random access memory; and When the number of the first logical address is lower than the specified number, adding a new node including the first logical address to the discard queue. The data access method in response to the host discarding command as described in claim 5, comprising: Executing the host write command sent by the host end, wherein the host write command indicates to write the user data of the fourth logical address to the flash memory module; When the fourth logical address appears in the extended discard table, delete the corresponding item of the fourth logical address from the extended discard table, and set according to the contents of the updated extended discard table the end address register in the performance engine for defining a new address range in the random access memory; and When the fourth logical address appears in the discard queue, update the content in the discard queue to reflect the execution result of the host write command. The data access method in response to the host discarding command as described in claim 5, comprising: receiving a host read command from the host end, wherein the host read command indicates to read user data at the fifth logical address; and When the fifth logical address appears in the extended drop list or the drop queue, reply false data to the host. A computer program product, including program code, wherein, when the processing unit executes the program code, implement the data access method in response to the host discard command as described in any one of claims 1 to 7. A data access device responding to a host discarding command, comprising: The random access memory is used to allocate space to the extended discard table, wherein the extended discard table includes a plurality of items, and each of the items records the logical address of the user data that has been discarded; A performance engine, including a start address register and an end address register, used to define an address range for storing the extended discard table in the random access memory; and A processing unit, coupled to the random access memory and the performance engine, configured to receive a host discard command from a host, wherein the host discard command indicates a first logical address of user data that is no longer used; adding a new item including the first logical address to the extended discard table; and setting the start address register and the end address register in the performance engine to redefine the random an address range of the extended drop table stored in the random access memory, so that the performance engine searches the extended drop table in the address range in the random access memory to determine a specific Whether the user data of the logical address is no longer used. According to claim 9, in the data access device responding to the discard command of the host, the plurality of entries in the extended discard table are arranged in ascending or descending exponentiation according to the logical address. The data access device responding to the host discard command as described in claim 9, wherein the processing unit executes the host write command to write the user data of the second logical address to the flash memory module; and when the second logical address is written into the flash memory module; When the second logical address appears in the extended discard table, delete the item containing the second logical address from the extended discard table, and set the set value according to the content of the updated extended discard table. The end address register in the performance engine is used to redefine the address range of the extended discard table stored in the random access memory. The data access device responding to host discarding commands as described in claim 9, wherein the processing unit receives a host read command from the host side, wherein the host read command indicates the use of the third logical address for reading or information; and when the third logical address appears in the extended discard list, reply false information to the host. The data access device in response to a host discarding command as described in Claim 9, Wherein, the random access memory allocates space for the discarding queue, wherein the discarding queue includes a plurality of nodes, and each of the nodes is used to store a logical address range of discarded user data, Wherein, the processing unit judges whether the number of the first logical addresses of the unused user data indicated by the host discard command exceeds or equals to a specified number; when the number of the first logical addresses When the number exceeds or is equal to the specified number, add a new item containing the first logical address to the extended discard table, and set the start address register and the end bit in the performance engine an address register for redefining the address range of the extended discard table stored in the random access memory; and when the number of the first logical address is lower than the specified number, a new Adding a new node including the first logical address to the discard queue. The data access device responding to the host discarding command according to claim 13, wherein the processing unit executes the host write command sent by the host end, wherein the host write command indicates to write the fourth logic bit address user data to the flash memory module; when the fourth logical address appears in the extended discard table, delete the corresponding item of the fourth logical address from the extended discard table, and according to The content of the updated extended discard table sets the end address register in the performance engine to define a new address range in the random access memory; and when the fourth logical address is out When currently in the discard queue, update the content in the discard queue to reflect the execution result of the host write command. The data access device responding to host discarding commands as described in claim 13, wherein the processing unit receives a host read command from the host side, wherein the host read command indicates the use of the fifth logical address for reading or data; and when the fifth logical address appears in the extended discard list or the discard queue, reply false data to the host.

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