TW202340939A - Method and computer program product and apparatus for data access in response to host discard commands - Google Patents

Abstract

The invention is related to a method, a computer program product, and an apparatus for executing host discard commands. The method includes: allocating space in a random access memory (RAM) to store an extended discard table including multiple entries each records a logical address of user data that has been discarded; receiving a host discard command, which indicates a first logical address of user data that is discarded, from a host side; appending a new entry including the first logical address to the extended discard table; and setting a start-address register and an end-address register in a performance engine to redefine an address arrange that holds the extended discard table in the RAM. By using the installation of the performance engine with the usage of the extended discard table, it avoids the processing unit to consume excessive computation resource to determine if a logical address of user data that is to be written, which is advised by a host write command, or a logical address of user data that is to be read, which is advised by a host read command, falls within logical address ranges that have been discarded.

Description

Data access methods and product computer programs and devices that respond to host discard commands

The present invention relates to storage devices, and in particular, to a data access method, product computer program and device in response to a host discard command.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processor (Host) can provide any address to access the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in a timely manner. material. On the contrary, NAND flash memory does not have random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write a sequence of Bytes values to the NAND flash memory to define the type of request command (Command) (such as , read, write, discard, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory). In order to improve the execution performance of the flash memory controller, the present invention proposes a data access method, product computer program and device in response to a host discard command.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

This specification relates to a data access method in response to a host discard command, which is executed by a processing unit and includes: configuring space in a random access memory for an extended discard table, including a plurality of items, and each of the items records that it has been discarded The logical address of the user data; receiving a host discard command from the host end, indicating the first logical address of the user data that is no longer used; adding a new item containing the first logical address to the extended format Discard table; and set the start address register and end address register in the performance engine to redefine the address range of the extended discard table stored in the random access memory, so that the performance engine can borrow The extended discard table is searched from the address range in the random access memory to determine whether user data at a specific logical address is no longer in use.

This manual also relates to a computer program product, including program code. When the processing unit executes the program code, the data access method in response to the host discard command as described above is implemented.

This specification further relates to a data access device that responds to a host discard command, including: a random access memory; a performance engine; and a processing unit. The random access memory is used to allocate space for the extended discard table, which contains a plurality of entries, and each entry records a logical address of discarded user data. The performance engine includes a start address register and an end address register, which are used to define an address range in the random access memory where the extended discard table is stored. The processing unit is configured to receive a host discard command from the host, which indicates a first logical address of user data that is no longer used; add a new entry including the first logical address to the extended discard table; and Setting the start address register and the end address register in the performance engine are used to redefine the address range of the extended discard table stored in the random access memory, so that the performance The engine determines whether the user data at a specific logical address is no longer in use by searching the extended discard table in the address range in the random access memory.

One of the advantages of the above embodiment is that through the setting of the performance engine and the use of the extended discard table, the processing unit is prevented from consuming too much computing resources to determine the logical address of the user data to be written by the host write command or the host read. Whether the logical address of the user data to be read by the command falls within the previously discarded logical address range.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority, precedence relationship between them, or that they are one element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The host interface (Host Interface) 137 between the host 110 and the flash memory controller 130 can be a Universal Serial Bus (USB), an advanced technology attachment (ATA), or a serial advanced technology attachment (ATA). Communication protocols such as SATA), peripheral component interconnect express (PCI-E), Universal Flash Storage (UFS), and embedded multi-media card (eMMC) communicate with each other. The flash interface (Flash Interface) 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other through a double data rate (Double Data Rate, DDR) communication protocol, such as Open NAND Flash (Open NAND Flash Interface, ONFI), dual Double data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware instructions, the functions described later are provided. The processing unit 134 receives host commands through the host interface 131, such as read command (Read Command), write command (Write Command), discard command (Discard Command), erase command (Erase Command), etc., schedules and executes these commands. . The flash memory controller 130 also includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, is used to configure the space as a data buffer to store user data (also called host data) read from the host 110 and about to be written to the flash memory module 150, and from the flash memory module. The group 150 reads and outputs the user data to the host 110 . The random access memory 136 can also store data needed during execution, such as variables, data tables, host-to-Flash Address Mapping Table (H2F table for short), flash memory and host addresses. Comparison table (Flash-to-Host Address Mapping Table, referred to as F2H table), etc. The flash memory interface 139 includes a NAND Flash Controller (NFC), which provides functions required for accessing the flash memory module 150, such as a command sequencer (Command Sequencer) and a low density parity check (LDPC). wait.

In some embodiments, the processing unit 134 may comply with the specifications of eMMC, such as Section 6.6.12 of EMBEDDED MULTI-MEDIA CARD (e·MMC), ELECTRICAL STANDARD (5.1) published in January 2019, through the host interface 131 Receive a discard command (Discard Command) from the host side 110. In other embodiments, the processing unit 134 may comply with the UFS specification, such as Section 11.3.26 of UNIVERSAL FLASH STORAGE (UFS), Version 3.1 published in January 2020, and receive the release from the host 110 through the host interface 131 Mapping command (UNMAP Command). If the parameter "bProvisioningType" of the Unit Descriptor in the unmapping command is set to "02h", it means that this is a discard command. The host 110 can send the host discard command as described above to the flash memory controller 130 to indicate the logical address of the user data that is no longer used, such as a host page number (Host Page Number), a logical block address ( Logical Block Address (LBA) and other methods. Different from the host erase command, when executing the host discard command, the flash memory controller 130 does not need to physically erase the memory unit used to store the data at the specified logical address. It only needs to mark that the data at this logical address is no longer available. exist. When appropriate, the flash memory controller 130 executes a garbage collection process to collect physical memory cells corresponding to the marked logical addresses and erase them.

The flash memory controller 130 can be configured with a bus architecture (Bus Architecture) 132 for coupling components to each other to transmit data, addresses, control signals, etc. These components include a host interface 131, a processing unit 134, a RAM 136, Performance Engine 137, Direct Memory Access (DMA) controller 138, Flash memory interface 139, etc. In some embodiments, the host interface 131, the processing unit 134, the RAM 136, the performance engine 137, the DMA controller 138, and the flash memory interface 139 may be coupled to each other through a single bus. In other embodiments, the flash memory controller 130 may be configured with a high-speed bus for coupling the processing unit 134, the performance engine 137, the DMA controller 138 and the RAM 136 to each other, and a low-speed bus for processing. The unit 134, the DMA controller 138, the host interface 131 and the flash memory interface 139 are coupled to each other. The DMA controller 138 can move data between components through the bus architecture 132 according to the instructions of the processing unit 134, for example, move the data from a specific data buffer (Data Buffer) in the host interface 131 or the flash memory interface 139 to the RAM 136. At a specific address, the data at a specific address in the RAM 136 is moved to a specific data register in the host interface 131 or the flash memory interface 139, etc.

The bus includes parallel physical lines that connect two or more components in the flash memory controller 130 . The bus is a shared transmission medium. At any time, only two devices can use these lines to communicate with each other and transfer data. Data and control signals can propagate in both directions between components along data and control lines respectively, but on the other hand, address signals can only propagate in one direction along address lines. For example, when the processing unit 134 wants to read data at a specific address of the RAM 136, the processing unit 134 transmits the address to the RAM 136 on the address line. Then, the data at this address will be returned to the processing unit 134 on the data line. In order to complete the data reading operation, control signals are transmitted using control lines.

The flash memory module 150 provides a large amount of storage space, usually hundreds of Gigabytes (GB) or even several Terabytes (TB), for storing large amounts of user data. For example, high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array may include Single Level Cells (SLCs), Multiple Level Cells (MLCs), or Triple Level Cells (Triple Level Cells). Level Cells (TLCs), Quad-Level Cells (QLCs), or any combination of the above. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and reads user data from a specified address (source address) in the flash memory module 150. The flash memory interface 139 uses several electronic signals to coordinate the transmission of data and commands between the flash memory controller 130 and the flash memory module 150, including data lines (Data Line), clock signals (Clock Signal) and control signals (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory units, for example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11. , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in a parallel manner, or write user data to the enabled NAND flash memory unit.

In some previous implementations, the flash memory controller 130 may configure space in the RAM 136 for a discard queue (Discard Queue). The drop queue contains multiple nodes, and each node is used to store information about the logical address range for discarding user data as instructed by the host drop command. Table 1 shows an example drop queue: Table 1 Node number start address length 0 P#100 32 1 P#200 4 2 P#300 64 3 P#500 8 For example, each node stores a starting master page number and length indicated by a discard command. As mentioned above, the 0th to 3rd example nodes contain the following information. The four previously received discard commands respectively indicate that the main pages P#100~P#131, P#200~P#203, and P#300~ The user data of P#363 and P#500~P#507 are discarded. However, each time the processing unit 134 receives a host read command from the host 110 through the host interface 131, it needs to consume computing resources to search the discard queue to determine whether the user data to be read by the host read command has been discarded. If the read user data has been discarded, the processing unit 134 returns an error message or a dummy value to the host 110 through the host interface 131 . When the processing unit 134 receives a host write command from the host 110 through the host interface 131 each time, it also needs to consume computing resources to search the discard queue to determine whether the logical address of the user data to be written by the host write command falls. Enter the logical address range that has been discarded before.

In order to reduce the load on the processing unit 134 and improve the overall performance of the flash controller 130, the flash controller 130 can allocate space in the RAM 136 for the expanded discard table (Expanded Discard Table), and use a dedicated performance engine 137 to search for the expanded discard table. Discard table. The extended discard table can contain 1024 items, each item records the logical address of discarded user data, or a NULL value. It should be noted that those skilled in the art can configure more or less space in the RAM 136 to store the extended discard table according to system requirements. The present invention is not limited to the extended discard table containing only 1024 items. Table 2 shows an example extended drop table: Table 2 Project number logical address 0 P#100 1 P#101 : : 31 P#131 32 P#200 33 P#201 34 P#202 35 P#203 36 P#300 37 P#301 : : 99 P#363 100 P#500 101 P#501 : : 107 P#507 Compared with Table 1, conceptually, the information of the 0th item in Table 1 can be expanded to the 0th to 31st items in Table 2, recording the main page numbers P#100 to P#131 respectively; Table 1 The information of the first item in Table 2 can be expanded to the 32nd to 35th items in Table 2, and the main page numbers P#200 to P#203 are respectively recorded, and so on. The processing unit 134 can perform sorting when adding items to the extended discard table based on the information carried in the host discard command, so that the logical addresses can be arranged in ascending or descending order to facilitate search by the dedicated performance engine 137 .

Refer to Figure 3. The performance engine 137 may include a start address register 322 and an end address register 324 for allowing the processing unit 134 to define the address range of the extended discard table in the RAM 136 . Since the number of items stored in the extended discard table is variable, whenever the contents of the extended discard table are updated, the processing unit 134 will reset the start address register 322 and the end address register 324 for searching. Circuit 310 is capable of searching within the address range of RAM 136 specified by start address register 322 and end address register 324. For example, corresponding to the contents of Table 2, the start address register 322 stores the memory address "ExpDiscardTable_start", and the end address register 324 stores ExpDiscardTable_star+107. The performance engine 137 may include eight target registers 330#0~330#7, which are used for the processing unit 134 to instruct the search circuit 310 to search up to eight main page numbers in the extended discard table. The performance engine 137 may include eight result registers 350#0~350#7, allowing the search circuit 310 to store search results corresponding to the target registers 330#0~330#7 respectively. For example, the result register 350#0 stores the search results for the main page number indicated by the target register 330#0, the result register 350#1 stores the search results for the main page number indicated by the target register 330#1, and so on. For example, the result register can be a 16-bit register, in which the 15th bit stores the information of whether there is a hit. If there is a hit, the 14th to 0th bits store the hit item number in the extended discard table. The processing unit 134 can read the value of any one of the result registers 350#0~350#7 to obtain the information of whether the main page number in the corresponding target register appears in the extended discard table, and, if it is hit, this main page The item in the extended discard table where the number exists. It should be noted that those skilled in the art can configure more or fewer pairs of target registers and result registers in the performance engine 137 according to the needs of the system. The present invention is not limited to only eight pairs of target registers in the performance engine 137. registers and result registers. Those skilled in the art can use conventional circuits to implement the search circuit 310 to allow the search circuit 310 to complete linear search (Linear Search), binary search (Binary Search), and exponential search (Exponential Search) in the extended discard table. ), Fibonacci Search, etc.

In some embodiments, dedicated wires may be used to connect the processing unit 134 and the performance engine 137, allowing the processing unit 134 to set the start address register 322, the end address register 324, and the target registers 330#0~330 through the dedicated wires. #7, and read the search results from the result registers 350#0~350#7.

In other embodiments, the processing unit 134 may set the start address register 322, the end address register 324, and the target registers 330#0~330#7 in the performance engine 137 through the shared bus architecture 132, and obtain the data from the performance engine 137. The result registers 350#0~350#7 in 137 read the search results.

In some embodiments, a dedicated wire may be used to connect the performance engine 137 and the RAM 136 to allow the performance engine 137 to read the value of a specific address in the RAM 136 through the dedicated wire.

In other embodiments, the performance engine 137 may read the value of a specific address in the RAM 136 through the shared bus architecture 132 and the DAM controller 138 .

In response to the technical solution of the extended discard table and the performance engine 137, an embodiment of the present invention proposes a method for executing a host discard command, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly to process the host discard command received from the host end 110 . Referring to Figure 4, the detailed steps are as follows:

Step S410: Receive the first (next) host discard command from the host terminal 110 through the host interface 131. The host discard command is used to indicate the logical address of the user data that is no longer used.

Step S420: Update the contents of the extended discard table stored in the RAM 136 according to the logical address of discarded user data indicated by the host discard command. The items in the updated extended discard table will be sorted in ascending or descending order according to the logical address.

Step S430: Set the start address register 322 and the end address register 324 in the performance engine 137 according to the updated extended discard table.

Assume that before step S420 in a loop is executed, the extended discard table is as shown in Table 2: When the processing unit 134 receives the user information indicating to discard the main pages P#400~P#403 (step S410), the table The extended discard table of 2 can be updated as shown in Table 3 below (step S420): Table 3 Project number logical address 0 P#100 1 P#101 : : 31 P#131 32 P#200 33 P#201 34 P#202 35 P#203 36 P#300 37 P#301 : : 99 P#363 100 P#400 101 P#401 102 P#402 103 P#403 104 P#500 105 P#501 : : 111 P#507 Next, the processing unit 134 sets the end address register 324 to ExpDiscardTable_star+111 (step S430).

In response to the technical solutions of the extended discard table and the performance engine 137, embodiments of the present invention propose a method for updating the extended discard table after the host write command is executed, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. . This method is executed iteratively to adaptively update the extended discard table after each host write command. Referring to Figure 5, the detailed steps are as follows:

Step S510: Execute the first (next) host write command to write the user data at the specified logical address into the flash memory module 150 through the flash memory interface 139.

Step S520: Determine whether the logical address to which the user data is written appears in the extended discard table. If yes, the process continues to the process of step S530; otherwise, the process continues to the process of step S510. The processing unit 134 may set the logical addresses to the target registers 330#0~330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0~330#7 and the driver performance engine 137, it can continue to process other tasks. After a preset period of time, the processing unit 134 checks the result registers 350#0~350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard table. After all logical addresses have been judged, the processing unit 134 continues the processing of the next step.

Step S530: Delete the corresponding entry of the logical address appearing in the extended discard table.

Step S540: Set the end address register 324 in the performance engine 137 according to the updated extended discard table.

Assume that before step S510 in a loop is executed, the extended discard table is as shown in Table 2: when the processing unit 134 completes executing the host write command of the user data of the main pages P#200~P#203 (step S510 ), the processing unit 134 sets the logical addresses P#200~P#203 to the target registers 330#0~330#3 in the performance engine 137, and drives the performance engine 137 to search the extended discard table to determine whether these logical addresses Appears in the extended discard table (step S520). When it is found that the logical addresses P#200~P#203 all appear in the extended discard table ("Yes" path in step S520), the processing unit 134 may update the extended discard table as shown in Table 4 below (step S530) : Table 4 Project number logical address 0 P#100 1 P#101 : : 31 P#131 32 P#300 33 P#301 : : 95 P#363 96 P#500 97 P#501 : : 103 P#507 Next, the processing unit 134 sets the end address register 324 to ExpDiscardTable_star+103 (step S540).

In response to the technical solutions of the extended discard table and performance engine 137, embodiments of the present invention propose a method for executing host read commands, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly and is used to selectively reply false data or real user data to the host 110 according to the contents of the extended discard table when each host read command is executed. Referring to Figure 6, the detailed steps are as follows:

Step S610: Extract the first (next) host write command to instruct the flash memory controller 130 to read the user data at the specified logical address.

Step S620: Determine whether any logical address of the user data to be read appears in the extended discard table. If yes, the process continues to the process of step S630; otherwise, the process continues to the process of step S640. The processing unit 134 may set the logical addresses to the target registers 330#0~330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0~330#7 and the driver performance engine 137, it can continue to process other tasks. After a preset period of time, the processing unit 134 checks the result registers 350#0~350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard table. After all logical addresses have been judged, the processing unit 134 continues the processing of the next step.

Step S632: For the logical address appearing in the extended discard table, the driver host interface 131 returns a false value to the host 110.

Step S634: The driver flash memory interface 139 reads user data of other logical addresses that do not appear in the extended discard table from the flash memory module 150, and drives the host interface 131 to reply the read user data to the host 110.

Step S640: drive the flash memory interface 139 to read the user data at the specified logical address from the flash memory module 150, and drive the host interface 131 to reply the read user data to the host 110.

In some embodiments, flash controller 130 may configure space in RAM 136 for the extended discard table and discard queue. If the length of the logical address for discarding user data indicated by a host discard command exceeds or is equal to a specified number (for example, exceeds or is equal to 32 hours), store the information carried in the host discard command in a node in the discard queue. . If the logical address length of discarded user data indicated by a host discard command is less than the specified number, the information carried in the host discard command is stored in one or more consecutive entries in the extended discard table. For example, when the four previously received discard commands respectively indicate that the users of the main pages P#100~P#131, P#200~P#203, P#300~P#363, and P#500~P#507 When data is discarded, the information indicated by these four discard commands will be recorded in the discard queue shown in Table 5 below and the extended discard table shown in Table 6 below: Table 5 Node number start address length 0 P#100 32 1 P#300 64 Table 6 Project number logical address 0 P#200 1 P#201 2 P#202 3 P#203 4 P#500 5 P#501 : : 11 P#507

In response to the technical solutions of the discard queue, the extended discard table and the performance engine 137, an embodiment of the present invention proposes a method for executing a host discard command, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly to process the host discard command received from the host end 110 . Referring to Figure 7, the difference from Figure 4 is that Figure 7 inserts the judgment of step S710 after step S410, and adds the processing of step S720 after the judgment is established. The detailed description is as follows:

Step S710: Determine whether the logical address length of the user data discarded as instructed by the host discard command exceeds or is equal to a specified number (for example, 32). If yes, the process continues to the process of step S720; otherwise, the process continues to the process of step S420.

Step S720: Update the content of the discard queue stored in the RAM 136 according to the logical address of the discarded user data indicated by the host discard command.

For technical details of steps S410 to S430 in Figure 7 , reference can be made to the corresponding description in Figure 4 , and will not be described again for the sake of simplicity.

In response to the technical solutions of the discard queue, the extended discard table and the performance engine 137, the embodiment of the present invention proposes a method for updating the discard queue and the extended discard table after the host write command is executed, which is loaded and executed by the processing unit 134 Implemented when executing relevant firmware or software instructions. This method is executed iteratively to adaptively update the discard queue and extended discard table after each host write command is executed. Referring to Figure 8, the difference from Figure 5 is that Figure 8 adds a new judgment of step S810 after step S510, and adds the processing of step S820 after the judgment is established. The details are as follows:

Step S810: Determine whether the logical address to which the user data is written appears in the discard queue. If yes, the process continues to the process of step S820; otherwise, the process continues to the process of step S510.

Step S820: Update the content in the discard queue to reflect the execution result of the host write command. Assume that before step S510 in a loop is executed, the discard queue is as shown in Table 5: when the processing unit 134 completes executing the host write command of the user data of the main pages P#100~P#131 (step S510) , the processing unit 134 can delete the 0th node in the discard queue to become as shown in Table 7 below (step S820): Table 7 Node number start address length 0 P#300 64

For the technical details of steps S510, S530 to S430 in Figure 8, please refer to the corresponding description in Figure 5, and will not be described again for the sake of simplicity. It should be noted here that, with the assistance of the performance engine 137, the operations of steps S520 to S540 may be performed in parallel with the operations of steps S810 to S820.

In response to the technical solutions of the discard queue, the extended discard table and the performance engine 137, an embodiment of the present invention proposes a host read command execution method, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly and is used to selectively reply false data or real user data to the host 110 according to the contents of the discard queue and the extended discard table when each host read command is executed. Referring to Figure 9, the difference between it and Figure 6 is that steps S620, S632, and S634 of Figure 6 are replaced by steps S910, S922, and S924 respectively. The detailed description is as follows:

Step S910: Determine whether the logical address of the user data to be read appears in at least one of the extended discard table and the discard queue. If yes, the flow continues to the processing of step S922; otherwise, the flow continues to the processing of step S640. The processing unit 134 may set the logical addresses to the target registers 330#0~330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0~330#7 and the driver performance engine 137, it can then search the discard queue to determine whether these logical addresses appear in the discard queue. After a preset period of time, the processing unit 134 checks the result registers 350#0~350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard table. After all logical addresses have been judged, the processing unit 134 continues the processing of the next step.

Step S922: For each logical address appearing in the extended discard table or discard queue, the driver host interface 131 returns a false value to the host 110.

Step S924: Drive the flash memory interface 139 to read other user data of logical addresses that do not appear in the extended discard table and discard queue from the flash memory module 150, and drive the host interface 131 to reply the read user data to the host. End 110.

All or part of the steps in the method described in the present invention can be implemented by computer instructions, such as a firmware translation layer (FTL) in a storage device, a driver for a specific hardware, etc. In addition, it can also be implemented in other types of programs. Those with ordinary skill in the art can write the methods of the embodiments of the present invention as computer instructions, which will not be described again for the sake of simplicity. Computer instructions implemented according to the methods of the embodiments of the present invention can be stored in appropriate computer-readable media, such as DVD, CD-ROM, USB disk, hard disk, or can also be placed in a computer that can be accessed through a network (for example, the Internet, or A web server accessible by other appropriate vehicles).

Although the above-described elements are included in FIGS. 1 to 3 , it does not rule out that more other additional elements may be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts of Figures 4 to 9 are executed in a specified order, those skilled in the art can modify the order of these steps without violating the spirit of the invention and achieving the same effect. Therefore, The present invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

10: Electronic devices 110: Host side 130:Flash controller 131:Host interface 132:Bus 134: Processing unit 136: Random access memory 137:Performance engine 138: Direct Memory Access Controller 139:Flash memory interface 150:Flash memory module 151:Interface 153#0~153#15: NAND flash memory unit CH#0~CH#3: Channel CE#0~CE#3: enable signal 310: Search circuit 322: Start address register 324: End address register 330#0~330#7: Target register 350#0~350#7: Result register S410~S430: Method steps S510~S540: Method steps S610~S640: Method steps S710~S720: Method steps S810~S820: Method steps S910~S924: Method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

FIG. 3 is a block diagram of a performance engine and a random access memory according to an embodiment of the present invention.

Figure 4 is a flow chart of a method for executing a host discard command according to an embodiment of the present invention.

FIG. 5 is a flow chart of a method for updating the extended discard table after the host write command is executed according to an embodiment of the present invention.

FIG. 6 is a flow chart of a method for executing a host read command according to an embodiment of the present invention.

Figure 7 is a flow chart of a method for executing a host discard command according to an embodiment of the present invention.

FIG. 8 is a flow chart of a discard command and an update method of an extended discard table after the host write command is executed according to an embodiment of the present invention.

FIG. 9 is a flow chart of a method for executing a host read command according to an embodiment of the present invention.

S410~S430: Method steps

Claims (15)

A data access method in response to a host discard command, executed by a processing unit, including: Configuring space in the random access memory for an extended discard table, wherein the extended discard table includes a plurality of entries, each of which records a logical address of discarded user data; Receive a host discard command from the host, wherein the host discard command indicates the first logical address of the user data that is no longer used; Add a new entry including the first logical address to the extended discard table; and Setting the start address register and the end address register in the performance engine are used to redefine the address range of the extended discard table stored in the random access memory, so that the performance engine uses the The address range in the random access memory searches the extended discard table to determine whether user data at a specific logical address is no longer in use. The data access method in response to a host discard command as described in claim 1, wherein the plurality of items in the extended discard table are arranged in ascending or descending order according to the logical address. The data access method in response to the host discard command as described in request 1 includes: Execute a host write command to write user data at the second logical address to the flash memory module; and When the second logical address appears in the extended discard table, delete the entry containing the second logical address from the extended discard table, and based on the updated extended discard table The content sets the end address register in the performance engine for redefining the address range of the extended discard table stored in the random access memory. The data access method in response to the host discard command as described in request 1 includes: Receive a host read command from the host end, wherein the host read command instructs to read the user data of the third logical address; and When the third logical address appears in the extended discard table, false data is returned to the host. The data access method in response to the host discard command as described in request 1 includes: Allocating space in the random access memory to a discard queue, wherein the discard queue includes a plurality of nodes, each of which is used to store a logical address range of discarded user data; Determine whether the number of the first logical addresses of the user data that is no longer used as indicated by the host discard command exceeds or is equal to a specified number; When the number of the first logical addresses exceeds or is equal to the specified number, a new entry including the first logical address is added to the extended discard table, and a parameter in the performance engine is set. The start address register and the end address register are used to redefine the address range of the extended discard table stored in the random access memory; and When the number of the first logical addresses is lower than the specified number, a new node including the first logical address is added to the discard queue. The data access method in response to the host discard command as described in request 5 includes: Execute the host write command sent by the host end, wherein the host write command instructs to write the user data at the fourth logical address to the flash memory module; When the fourth logical address appears in the extended discard table, delete the corresponding entry of the fourth logical address from the extended discard table, and set it according to the content of the updated extended discard table. The end address register in the performance engine is used to define a new address range in the random access memory; and When the fourth logical address appears in the discard queue, the content in the discard queue is updated to reflect the execution result of the host write command. The data access method in response to the host discard command as described in request 5 includes: Receive a host read command from the host end, wherein the host read command instructs to read the user data of the fifth logical address; and When the fifth logical address appears in the extended discard table or the discard queue, false data is returned to the host. A computer program product includes program code, wherein when a processing unit executes the program code, the data access method in response to a host discard command as described in any one of claims 1 to 7 is implemented. A data access device that responds to host discard commands, including: A random access memory for configuring space for an extended discard table, wherein the extended discard table includes a plurality of items, each of which records the logical address of discarded user data; A performance engine, including a start address register and an end address register, used to define the address range in the random access memory where the extended discard table is stored; and a processing unit coupled to the random access memory and the performance engine for receiving a host discard command from the host, wherein the host discard command indicates the first logical address of the user data that is no longer used; Add a new entry including the first logical address to the extended discard table; and set the start address register and the end address register in the performance engine to redefine the random Accessing an address range of the extended discard table stored in memory causes the performance engine to determine a specific Whether the user data of the logical address is no longer in use. The data access device for responding to a host discard command as described in claim 9, wherein a plurality of the entries in the extended discard table are arranged in ascending or descending order according to the logical address. The data access device responding to a host discard command as described in claim 9, wherein the processing unit executes a host write command to write user data at the second logical address to the flash memory module; and when the third When a second logical address appears in the extended discard table, delete the item containing the second logical address from the extended discard table, and set the item based on the updated contents of the extended discard table. The end address register in the performance engine is used to redefine the address range of the extended discard table stored in the random access memory. The data access device responding to a host discard command as described in claim 9, wherein the processing unit receives a host read command from the host, wherein the host read command indicates the use of reading the third logical address information; and when the third logical address appears in the extended discard table, reply false information to the host. A data access device responding to a host discard command as described in request 9, Wherein, the random access memory configures space for a discard queue, wherein the discard queue includes a plurality of nodes, and each node is used to store a logical address range of discarded user data, Wherein, the processing unit determines whether the number of the first logical addresses of the user data that is no longer used as indicated by the host discard command exceeds or is equal to a specified number; when the number of the first logical addresses of the When the number exceeds or is equal to the specified number, add a new item including the first logical address to the extended discard table, and set the start address register and the end bit in the performance engine an address register for redefining the address range of the extended discard table stored in the random access memory; and when the number of the first logical addresses is lower than the specified number, a new Add a new node including the first logical address to the drop queue. The data access device responding to a host discard command as described in claim 13, wherein the processing unit executes a host write command sent by the host, wherein the host write command indicates writing a fourth logical bit user data of the address to the flash memory module; when the fourth logical address appears in the extended discard table, delete the corresponding entry of the fourth logical address from the extended discard table, and based on The content of the updated extended discard table sets the end address register in the performance engine to define a new address range in the random access memory; and when the fourth logical address is out When the discard queue is now in the discard queue, the content in the discard queue is updated to reflect the execution result of the host write command. The data access device responding to a host discard command as described in claim 13, wherein the processing unit receives a host read command from the host, wherein the host read command indicates the use of reading the fifth logical address and when the fifth logical address appears in the extended discard table or the discard queue, reply false information to the host.

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