TWI737031B - Method and computer program product for reading data fragments of a page on multiple planes - Google Patents

Abstract

A computer program product being loaded and executed by a processing unit, includes program code to: provide a scheduling table; arrange each memory access instruction of a command queue into a cell of the scheduling table according to its physical address information; select two or more memory access instructions for one logical unit number (LUN) according to the content of the scheduling table; direct a flash interface to complete a multi-page read lite (MPR-lite) operation for reading data requested by the selected memory access instructions from the LUN; and reply the read data to a host.

Description

Method for reading fragment data of pages on multiple planes and computer program product

The invention relates to a flash memory device, in particular to a method for reading fragment data of pages on multiple planes and a computer program product.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host can provide any address for accessing the NOR flash memory device on the address pin, and obtain it from the data pin of the NOR flash memory device in time Data stored at that address. On the contrary, NAND flash memory devices are not random access, but serial access. NAND flash memory devices cannot access any random address like NOR flash memory devices. Instead, the host needs to write serial bytes (Bytes) into the NAND flash memory device to define the request command (Command) type (for example, read, write, erase, etc.), and the address used for this command. The address can point to a page (the smallest data block for writing in a flash memory device) or a block (the smallest data block for erasing in a flash memory device).

The read command provided by the traditional NAND flash memory usually allows the controller to read an entire cross-plane page data. However, as the length of the cross-plane page in the NAND flash memory device (such as 16KB) has exceeded the data length (such as 4KB) of the logical block address (Logical Block Address LBA) managed by the operating system executed by the host, the traditional A read operation that reads an entire cross-plane page data every time may reduce NAND when processing short data read commands from the host. The overall performance of flash memory. Therefore, the present invention provides a method and computer program product for reading fragment data of pages on multiple planes to perform optimized data reading operations for NAND flash memory with longer span pages.

In view of this, how to reduce or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

The present invention provides a method for reading fragment data of pages on multiple planes. The method is implemented by a processing unit when loading and executing firmware or software code, including: providing a schedule data table; A memory operation command is arranged into a cell in the scheduling table according to its physical address information; two or more memory operation commands are selected for a logical unit number according to the content of the scheduling table; the flash memory interface is driven to complete multiple operations. Page read simplified operation, read the data requested by the selected memory operation command from the logical unit number; and reply the read data to the host.

The present invention provides a computer program product for reading fragment data of pages on multiple planes, including program codes for implementing the above steps.

One of the advantages of the above embodiment is that by using the scheduling data table to collect two or more fragment reading operations into one MPR-lite operation, the performance of short data reading can be improved.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

100: Flash storage system architecture

110: host

130: Controller

131: Host Interface

133-0, 133-1: processor core

135: Command Queue

136: data cache

137: Flash memory interface

138: DMA controller

139: data buffer

150: LUNs

150#0~150#11:LUN

CH#0~CH#3: Channel CH

CE#0~CE#2: Chip enable signal

CQT, CQH: indicators

139#0: Access sub-interface

410#0~470#m: plane

P#0~P#(n): page

490#1~490#n: Super page

t _WB , t _RSNAP , t _DBSY , t _PR : time interval

900: Schedule data table

S1010~S1090: method steps

1100, 1200: MPR-Lite scheduling data table

FIG. 1 is an architecture diagram of a flash storage system according to an embodiment of the present invention.

Figure 2 is a schematic diagram of the connection between a flash memory interface and a logical unit number (Logical Unit Number LUN).

Figure 3 is a schematic diagram of the command queue.

Figure 4 is a schematic diagram of LUN data organization.

FIG. 5 is a timing diagram of segment reading of the flash interface operation.

Figure 6 is a schematic diagram of the sections on the page.

FIG. 7 is a simplified timing diagram of multi-page reading of flash memory interface operation.

Figure 8 is a schematic diagram of the organization of the plane and cross-plane pages in the LUN.

FIG. 9 is a schematic diagram of memory operation command scheduling according to some embodiments.

FIG. 10 is a flowchart of a method for scheduling memory operation commands according to an embodiment of the present invention.

11 and 12 are schematic diagrams of memory operation command scheduling according to an embodiment of the present invention.

13 and 14 are schematic diagrams of selecting memory operation commands according to an embodiment of the present invention.

The following descriptions are preferred implementations for completing the invention, and their purpose is to describe the basic spirit of the invention, but not to limit the invention. The actual content of the invention must refer to the scope of the claims that follow.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, elements, and/or components, but they do not exclude the possibility of adding More technical features, values, method steps, job processing, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a precedence, prerequisite relationship, or an element. Prior to another element, or the chronological order of execution of method steps, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being “connected” or “coupled” to another element, it can be directly connected or coupled to other elements, and intermediate elements may appear. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other terms used to describe the relationship between elements can also be interpreted in a similar manner, such as "between" and "directly between", or "adjacent" as opposed to "directly abutting" and so on.

1, the flash storage system architecture 100 includes a host (Host) 110, a controller (Controller, or Device) 130, and a logical block number (LUN) 150. This system architecture can be implemented on personal computers and laptops (Laptop PC), tablet computers, mobile phones, digital cameras, digital cameras and other electronic products. The controller 130 may include a multi-core processor 133, which is a single computing element, with two independent processor cores 133-0 and 133-1 for loading firmware or software module codes. The processor core 133-0 can use Universal Flash Storage (UFS), Fast Non-Volatile Memory Express (Nvme), and Universal Serial Bus (USB) through the host interface 131. ), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E) or other interface protocols to communicate with the host 110 . The processor core 133-1 can use the Double Data Rate (DDR) communication protocol through the flash memory interface 137, for example, Open NAND Flash Interface (ONFI), Double Data Rate Switch (DDR Toggle) Or other interface protocols to communicate with LUN 110.

The Logical Unit Number (LUN) 150 provides a large amount of storage space, usually hundreds of Gigabytes, or even Terabytes, which can be used to store a large amount of user data, such as high-resolution pictures, videos, and so on. The LUN 150 includes a control circuit and a memory array. The memory cells in the memory array can be triple level cells (TLCs) or quad-level cells (QLCs). The data buffer (Data Buffer) 139 can be used to buffer the user data read from the LUN 150 and will be knocked out to the host 110. Referring to Figure 2, the flash memory interface 137 may include four I/O Channels (hereinafter referred to as channel CH), including channels CH#0 to CH#3, and each channel CH is connected to three LUNs, for example, channel CH# 0 is connected to LUN150#0, 150#4, and 150#8. The processor core 133-1 can drive the flash memory interface 137 to send one of the enabling signals CE#0 to CE#2 to enable LUN 150#0 to 150#3, LUN 150#4 to 150#7, or LUN 150# 8 to 150#11, and then read user data from the enabled LUNs in parallel. In order to simplify the description, only the channel CH#0 to CH#1 and CE#0 to CE#1 are used to enable LUN 150#0~1 and LUN 150#4~5 as examples, but not limited to this.

The controller 130 can be configured with a command queue 135 for storing a plurality of flash memory operation commands. The flash memory operation commands are, for example, a read page (Read Page) command, a page programming (Program Page) command, and an erase area Block (Erase Block) commands and so on. The flash memory operation commands can be associated with host commands (Host Commands) issued by the host 110 but not yet processed, such as host read commands, host write commands, etc., or can be commands independently issued by the controller 130.

The command queue 135 can be implemented in a static random access memory (SRAM), and includes a collection of multiple entries. Each item in the command queue 135 can store a flash memory operation command and related information. The flash memory operation commands in the set can be stored in order according to the arrival time. The basic principle of the operation of the set is that the processor core 133-0 adds a flash memory operation command (which can be called enqueue) from the end position (as indicated by the index CQT), and the processor core 133-1 The starting position (as indicated by the indicator CQH) removes the flash memory operation command (which can be called dequeue). However, in order to optimize the data read operation, the first flash memory operation command added to the command queue 135 may not be the first to be removed. In addition, the controller 130 can also use a stack to store the aforementioned flash memory operation commands, and it is not limited thereto.

LUN 150 includes multiple planes (Planes). Referring to FIG. 4, taking LUN 150#0 as an example, it includes four planes (Planes), including planes 410 to 470. Each plane includes multiple physical blocks (Physical Blocks, referred to as blocks). Taking the plane 410 as an example, it includes blocks 410#0~m, where m is a positive integer. Each block includes multiple pages (Pages). Taking block 410#0 as an example, it includes pages P#0 to P#n, where n is a positive integer. Each page P includes a plurality of NAND memory cells (Memory Cells), and the NAND memory cell can be a three-layer cell or a four-layer cell. In some embodiments, when each NAND memory cell is a three-layer cell and can record 8 states, one word line Can include page P#0 (can be called the lowest bit page, MSB page), page P#1 (can be called the middle bit page, CSB, Center Significant Bit page) and page P#2 (can be called the highest bit page) Meta page, LSB page). When each NAND memory cell is a four-layer cell and can record 16 states, in addition to MSB, CSB, and LSB pages, it also includes TSB (which can be called top bit, TSB, Top Significant Bit) page. One block in different planes in the same LUN 150 can virtually form a big block, and big blocks in different LUNs 150 can virtually form a super block.

The data cache 136 and/or the data buffer (Data Buffer) 139 can store the logical-physical mapping table (Logical-Physical Mapping Table, L2P mapping table) that needs to be looked up when data is read. The L2P mapping table records the data of each piece of data. Mapping information between logical address and physical address. The data cache 136 can be implemented in SRAM, and the data buffer 139 can be implemented in a pre-allocated area in a dynamic random access memory (DRAM).

Although the memory cells in each block or page are TLCs or QLCs, the controller 130 can use a single-level cell (Single Logical Cells, SLCs) mode to program data into the block or page to improve The speed of data reading and data programming. In order to facilitate the management of the block programming mode, the controller 130 preferably creates and maintains a physical configuration table (Physical Configuration Table) to record the programming mode of each block, that is, the default mode (TLC or QLC) or the SLC mode. And save the entity configuration data table to the data cache 136. In the data reading operation, the controller 130 can identify the programming mode of each block or page by searching the physical configuration data table, and in this way, read the data of the block or page in an appropriate reading method .

The controller 130 can output a read page command to read a page of a block in a plane of the LUN 150, and can also output a read page multi-plane command to read different planes. Data of one page of one block. However, sometimes the host 110 does not need a whole page of data, but only 4KB of data in one page. At this time, the controller 130 can use a Snap Read command to read part of the data in a page. Regarding the fragment read operation, refer to Figure 5. Waveform 510 shows the clock type of the data line DQ[7:0] coupled between LUN 150 and flash memory interface 137, with 1 "CMD" clock indicating the main command sent from flash memory interface 137, and 5 "Addr" The clock indicates the physical address of LUN 137 to be read from the flash memory interface 137, and then a "CMD" clock indicates the Confirm command sent from the flash memory interface 137, and finally, "D _OUT " indicates Data output from LUN 150. Waveform 520 is an exemplary fragment read command of waveform 510. The main command is 00h and the confirmation command is 20h. Therefore, LUN 150 judges that this operation command is a fragment read command, which reads the specified page (physical address). Page information.

Part of the page data is, for example, 8KB data in a 16KB page data. Refer to Figure 6, where the 8KB data can be selected from three different sections in the page: the first 8KB section 625, the middle 8KB section 645, and the last 8KB section 665. The length of each 8KB section is preferably greater than or equal to 8KB. In addition, part of the page data can also be, for example, 4KB data in a 16KB page data, that is, a 16KB page is divided into a first 4KB section, a second 4KB section, a third 4KB section, and a fourth 4KB section, each 4KB section The length of the segment is preferably greater than or equal to 4KB.

In addition, because the LUN 150 includes multiple planes (Planes), the controller 130 can output a Multi-Page Read Lite (MPR-Lite) command to read multiple planes in the LUN 150. Refer to FIG. 6 for the fragment information on the page, for example: the first 8KB section 625 in the page P#0 of the planes 810 and 830, and the last 8KB section 665 of the page P#1 in the planes 830 and 850. MPR-Lite command can improve the reading performance of fragment data.

1, taking data reading as an example, the processor core 133-0 can obtain a data reading command from the host 110 through the host interface 131, where the data reading command provides the logical address of the target data. The processor core 133-0 can obtain the page position (physical address) of the target data in the LUN 150 by looking up the L2P mapping table and the logical address, and can know the programming mode of the target data from the physical configuration data table. Then, the processor core 133-0 generates a flash memory operation command to the command queue 135, where the flash memory operation The command includes the physical address of the target data.

The controller 130 can use the command queue 135 to store a plurality of flash memory operation commands, for example, 64 flash memory operation commands. The processor core 133-1 can create and maintain a Scheduling Table 900 and/or a Standby Table 910 in the data cache 136 to sort the flash memory operation commands in the command queue 135. Makes the execution of flash memory operation commands more efficient. Referring to FIG. 9, for example, the command queue 135 currently stores 13 read page commands, which are labeled "a" ~ "m". The processor core 133-1 records the page read command for reading a specific LUN 150 to a specific column in the schedule table 900, for example, arranges page read commands "b", "a", and "d" into the schedule table. In the schedule 900, the pages of LUN 150#0, LUN 150#4, and LUN 150#1 are read respectively. In this way, the processor core 133-1 can read the pages in a synchronous and interleaving operation mode. The commands "b", "a", and "d" are output to LUN 150#0, LUN 150#4, and LUN 150#1. The processor core 133-1 will read the page commands "c", "e" ~ "m" into the standby list, when the page read commands "b", "a", "d" in the schedule table 900 are executed After completion, the page read commands "e", "c", and "g" in the standby table are then arranged into the schedule table 900. After that, the page read commands "j", "f", and "k" in the standby table are placed into the schedule table 900, and finally, the page read commands "i", "m" in the standby table are arranged Enter the schedule 900. Therefore, 13 page read commands require 4 cycles to be executed. In some embodiments, the processor core 133-1 only creates and maintains the schedule 900, and sequentially stores the flash memory operation commands in the schedule 900, and the processor core 133-1 finishes executing the first row of flash After the memory operation command, continue to execute the next row of flash memory operation commands, and so on.

If the target data is 4KB or 8KB data in a page, the controller 130 can use the command queue 135 to store the fragment read command instead of the page read command. Or, use the MPR-Lite command to execute the fragment read command in the command queue 135, that is, integrate multiple fragment read commands into one MPR-Lite command. When multiple segment read commands are integrated into one MPR-Lite command, the controller 130 needs to change the multiple segment read commands to multiple A read page multi-plane command, the confirmation command is 32h, and the last fragment read command is unchanged, and the confirmation command is 20h. As a result, the controller 130 can not only execute the fragment read command in a synchronous and interleaved operation mode, It can also increase the execution efficiency of fragment read commands. Referring to Figure 11, the fragment read command "b" is to read the target data in LUN 150#0, and the fragment read commands "a" and "h" are to read the target data in different planes in LUN 150#4. The fragment read The commands "d" and "g" are for reading target data of different planes in LUN 150#1. Therefore, the controller 130 can read the fragments with the commands "a", "b", "d", "h" and " g" is executed by the MPR-Lite command. Therefore, the controller 130 can execute 5 fragment read commands together instead of 3 fragment read commands. In other words, the MPR-Lite command can execute The execution efficiency has increased by 66%.

In some embodiments, in response to the MPR Lite command as described above, the processor core 133-1 can implement the flash memory operation command sequence function as shown in FIG. 10 when loading and executing specific software or firmware commands. .

Step S1010: The processor core 133-1 provides the MPR-Lite scheduling data table in the data cache 136. Compared with the schedule table 900 and the standby table 910 shown in FIG. 9, the MPR-Lite schedule table provides a more detailed distinction for each LUN, which is conducive to integrating two or more fragment read commands into one MPR -lite operation.

Refer to the MPR-Lite scheduling data table 1100 shown in Figure 11. For each LUN, two columns "Plane0/1" and "Plane2/3" can be included, which are used to read the fragments according to the entity to be read The address is divided into cells in one of the columns. For example, the cell in the third column of the MPR-Lite schedule table 1100 is used to record read commands for reading data on the plane 810 and/or plane 830; and the cell in the fourth column is used to record reading The plane 850 and/or the fragment read command of the data on the plane 870.

In addition, when the data is programmed into the block, the preset programming mode may be used, such as the TLC or QLC mode, or the SLC mode may be used. Different programming modes require different data reading methods to read data correctly. Therefore, when multiple fragment read commands are integrated into one MPR-Lite command, in order to read data correctly, multiple fragments The target data to be read by the read command must use the same programming mode. Therefore, the MPR-Lite scheduling data table 1100 can be slightly adjusted to become the MPR-Lite scheduling data table 1200. Refer to Figure 12 for each LUN, can include three columns "Main P0/1", "SLC P2/3" and "QLC P2/3", which are used to assign each flash memory operation command according to the physical address to be read and the used The mode is divided into cells in one of the columns. For example, the cell in the fourth column of the MPR-lite schedule table 1200 is used to record flash memory operation commands for reading data on the plane 810 and/or plane 830, regardless of the reading mode used; The five-column cell is used to record the flash memory operation commands used to read data on the plane 850 and/or plane 870 in SLC mode; and the cell in the sixth column is used to record the read plane 850 and/or data in the QLC mode. Or flash memory operation command for data on plane 870.

Next, referring to FIG. 10, the processor core 133-1 repeatedly executes a loop (steps S1030 to S1090) for arranging each flash memory operation command in the command queue 135 to the MPR-Lite schedule The appropriate cell in the table. For each round, the details are as follows:

Step S1030: The processor core 133-1 obtains the physical address information of one or more unsorted flash memory operation commands from the command queue 135. If a flash memory operation command instructs to read data on the plane 830 and the plane 850, the processor core 133-1 can arrange the flash memory operation command to a cell in the field associated with the plane 830, for example The column "Plane0/1" in Figure 11 or the column "Main P0/1" in Figure 12.

Step S1050: Arrange each flash memory operation command to an appropriate cell in the MPR-Lite scheduling table according to the physical address and other related information. Referring to the use case of FIG. 11, the cell in the third column of the MPR-Lite schedule data table 1100 is used to record the read command "a", "c" and "segment reading of data on the plane 810 and/or plane 830. f"; and the cell in the fourth column is used to record read commands "h" and "i" for reading data on the plane 850 and/or plane 870.

In other embodiments of step S1050, other related information of the memory operation command may be Contains which mode the flash memory operation command uses to read. The processor core 133-1 can search the content of the physical configuration data table in the data cache 136, and know which mode the flash memory operation command needs to be read according to the programming mode of the block corresponding to the physical address Pick. Referring to the use case of FIG. 12, the cell in the fourth column of the MPR-Lite schedule data table 1200 is used to record the read commands "a" and "f" of the data on the plane 810 and/or plane 830; where The cell in the fifth column is used to record the fragment read commands "h" and "i" that use SLC mode to read data on plane 850 and/or plane 870; and the cell in the sixth column is used to record the use of QLC mode Read the plane 850 and/or the fragment read command "c" of the data on the plane 870.

Following the sorting result described in FIG. 11, FIG. 13 shows a use case of selecting flash memory operation commands. For example, in a batch, the processor core 133-1 drives the flash memory interface 137 to send a read page command to LUN 150#0, which is used to read the data at the physical address specified by the fragment read command "b"; send read Take the page multi-plane command to LUN 150#4 for reading the data of the physical address specified by the fragment read commands "a" and "h", and send the page multi-plane command to LUN 150#1 for reading Take the data of the physical address specified by the fragment read command "d", and send the fragment read command to LUN 150#1 to read the data of the physical address specified by the memory operation command "g" to form a MPR-lite operation.

Following the sorting result described in FIG. 12, FIG. 14 shows a use case of selecting memory operation commands. For example, in a batch, the processor core 133-1 judges that the programming of the target data is SLC mode, therefore, it drives the flash memory interface 137 to send a read page multi-plane command to LUN 150#0, which is used to read the fragment read command The data of the physical address specified by "b"; send the read page multi-plane command to LUN 150#4 for the data of the physical address specified by the fragment read commands "a" and "h", and send the fragment read command For LUN 150#1, it is used to read the data of the physical address specified by the fragment read command "d" to form an MPR-lite operation.

By referring to the sorting results of the MPR-Lite scheduling table, the processor core 133-1 can execute the fragment read command as described above in batches, but when the processor core 133-1 changes to The MPR-Lite command to read fragment data of pages on multiple planes not only improves the efficiency of data reading, but also improves the efficiency of fragment reading operations. In the 4K random read Q64/T4 test, compared to the fragment read command, the MPR-Lite command can increase the average read data hit rate by nearly 30-50%. The hit rate of a read is defined as the ratio of the data read from the LUN 150 through the flash memory interface 137 which is retained for reply to the host 110. For example, when all the 8K data read by the fragment read command are retained for reply to the host 110, the hit rate of this read is 100%. When only half of the 8K data read by the fragment read command is retained for reply to the host 110, the hit rate of this read is 50%.

All or part of the steps in the method of the present invention can be implemented by a computer program, such as a computer operating system, a specific hardware driver in the computer, or a software application program. In addition, it can also be implemented in other types of programs as shown above. Those with ordinary knowledge in the technical field can write the method of the embodiment of the present invention into a computer program, which will not be described for the sake of brevity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer readable data carrier, such as DVD, CD-ROM, USB disk, hard disk, and can also be placed on a network (for example, the Internet) Or other appropriate vehicle).

Although FIG. 1 includes the above-described elements, it is not excluded that, without violating the spirit of the invention, more other additional elements can be used to achieve better technical effects. In addition, although the flowchart in FIG. 10 is executed in a specified order, those skilled in the art can modify the sequence of these steps on the premise of achieving the same effect without violating the spirit of the invention. Therefore, the present invention does not It is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of the claims applied for must be in the broadest way The formula is explained to include all obvious modifications and similar settings.

S1010~S1090: method steps

Claims (10)

A computer program product used to read fragment data of pages on multiple planes, loaded and executed by a processing unit, including the following code: providing a scheduling data table; storing each memory in a command queue The operation command is arranged in a cell in the schedule table according to the physical address information of the memory operation command; two or more memory operation commands are selected for a logical unit number according to the content of the schedule table A multi-page read streamline operation is formed, where each selected memory operation command requests to read data less than the length of a cross-plane page; a flash memory interface is driven to complete the multi-page read streamline operation, from the logic The unit number reads the data requested by the selected memory operation command; and replies the read data to a host. The computer program product according to claim 1, wherein the multi-page reading simplified operation includes: driving the flash memory interface to send one or more page-reading multi-plane commands and then sending a fragment reading command to the logical unit number, and reading Get the data of the physical address specified by the selected memory operation command. The computer program product according to claim 2, wherein the read page multi-plane command and the fragment read command are respectively used to read fragment data on different cross-plane pages. The computer program product according to claim 2, wherein the read page multi-plane command and the fragment read command run in a mode. The computer program product according to claim 4, wherein the mode is a single-layer unit, a three-layer unit, or a four-layer unit mode. A method for reading fragment data of pages on multiple planes, executed by a processing unit, includes: providing a scheduling data table; and arranging each memory operation command in a command queue according to the actual memory operation command The body address information is arranged in a cell in the schedule table; according to the contents of the schedule table, two or more memory operation commands are selected for a logical unit number to form a multi-page read condensed operation. Each selected memory operation command requests to read data less than the length of a cross-plane page; drives a flash memory interface to complete the multi-page read streamline operation, and reads the selected memory operation from the logical unit number Command the requested data; and reply the read data to a host. The method for reading fragment data of pages on multiple planes according to claim 6, wherein the simplified multi-page reading operation includes: driving the flash memory interface to send one or more page-read multi-plane commands followed by a fragment read The command is given to the logical unit number, and the data of the physical address specified by the selected memory operation command is read. The method for reading fragment data of a page on a multi-plane according to claim 7, wherein the waiting data ready time required for the read page multi-plane command is shorter than the waiting data ready time required for the fragment read command. The method for reading fragment data of pages on multiple planes as described in claim 6, wherein each column in the scheduling data table is used to record information about reading memory operation commands on a specific plane in a specific logical unit number . The method for reading fragment data of pages on multiple planes according to claim 6, wherein each column in the scheduling data table is used to record and read a first plane and a second plane in a specific logical unit number. Use a first mode or the second plane and use the information of a memory operation command in a second mode.

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