CN111796759A

CN111796759A - Computer readable storage medium and method for fragment data reading on multiple planes

Info

Publication number: CN111796759A
Application number: CN201911076916.4A
Authority: CN
Inventors: 李冠德; 孙健玮; 邹定衡
Original assignee: Silicon Motion Inc
Current assignee: Silicon Motion Inc
Priority date: 2019-04-01
Filing date: 2019-11-06
Publication date: 2020-10-20
Anticipated expiration: 2039-11-06
Also published as: CN111796759B; TWI737031B; TW202038097A

Abstract

The invention proposes a computer-readable storage medium for fragment data reading on multiple planes, for storing computer program code that can be executed by a processing unit and that, when executed by the processing unit, implements the following steps: providing a scheduling data table; arranging each memory operation command in the command queue into a storage grid in a scheduling data table according to the physical address information of the memory operation command; selecting two or more memory operation commands for a logic unit number according to the content of the scheduling data table; driving a flash memory interface to complete multi-page reading simplified operation, and reading the data requested by the selected memory operation command from the logic unit number; and replying the read data to the host. By using the schedule data table to collect two or more segment read operations into one multi-page read compaction operation, the efficiency of short data read can be improved.

Description

Computer readable storage medium and method for fragment data reading on multiple planes

Technical Field

The present invention relates to data storage devices, and more particularly, to a computer readable storage medium and method for reading fragment data on multiple planes.

Background

Flash memory devices are generally classified into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device and a Host (Host) may provide any address on an address pin to access the NOR flash memory device and obtain data stored at the address from a data pin of the NOR flash memory device in a timely manner. In contrast, NAND flash memory devices are not random access, but are serial access. NAND flash memory devices cannot access any random address as NOR flash memory devices, but instead the host needs to write serial byte (Bytes) values into the NAND flash memory device to define the type of Command (Command) (e.g., read, write, erase, etc.) and the address used in the Command. The address may point to one page (the smallest block of data for a write operation in the flash memory device) or one block (the smallest block of data for an erase operation in the flash memory device).

Read commands provided by conventional NAND flash memory (NAND flash memory) typically enable a controller to read data across a flat page. However, as the length of a cross-plane page (e.g., 16KB) in a NAND flash memory device already exceeds the data length (e.g., 4KB) of a Logical Block address (Logical Block address lba) managed by an operating system executed by a host, a conventional read operation that reads an entire cross-plane page of data each time may reduce the overall performance of the NAND flash memory when processing a short data read command from the host. Therefore, embodiments of the present invention provide a computer readable storage medium and a method for fragment data reading on multiple planes, which perform optimized data reading operations for NAND flash memories with long cross-plane pages.

Disclosure of Invention

In view of the above, how to reduce or eliminate the deficiency of the related art is a problem to be solved.

The invention relates to a computer-readable storage medium for fragment data reading on multiple planes, for storing computer program code that can be executed by a processing unit and which, when executed by the processing unit, implements the steps of: providing a scheduling data table; arranging each memory operation command in the command queue into a storage grid in a scheduling data table according to the physical address information of the memory operation command; selecting two or more memory operation commands for a logic unit number according to the content of the scheduling data table; driving a flash memory interface to complete multi-page reading simplified operation, and reading data requested by a selected memory operation command from a logic unit number; and replying the read data to the host.

The invention relates to a fragment data reading method on multiple planes, which is executed by a processing unit and comprises the following steps: providing a scheduling data table; arranging each memory operation command in the command queue into a storage grid in a scheduling data table according to the physical address information of the memory operation command; selecting two or more memory operation commands for a logic unit number according to the content of the scheduling data table; driving a flash memory interface to complete multi-page reading simplified operation, and reading data requested by a selected memory operation command from a logic unit number; and replying the read data to the host.

One advantage of the foregoing embodiments is that the performance of short data reads can be improved by using the schedule data table to collect two or more segment read operations into a multi-page read compaction operation.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application.

FIG. 1 is a block diagram of a flash memory system according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of connection between a flash memory interface and a Logical Unit Number (Logical Unit Number LUN).

FIG. 3 is a schematic diagram of a command queue.

FIG. 4 is a data organization diagram of a LUN.

FIG. 5 is a timing diagram of a segment read of a flash interface operation.

FIG. 6 is a schematic view of a section in a page.

FIG. 7 is a simplified timing diagram for a multi-page read operation of a flash memory interface.

FIG. 8 is an organization diagram of the planar and cross-planar pages in a LUN.

FIG. 9 is a schematic diagram of memory operation command scheduling according to some embodiments.

FIG. 10 is a flowchart illustrating a method for scheduling memory operation commands according to an embodiment of the invention.

FIGS. 11 and 12 are schematic diagrams illustrating memory operation command scheduling according to an embodiment of the invention.

FIGS. 13 and 14 are schematic diagrams illustrating selection of a memory operation command according to an embodiment of the invention.

[ List of reference numerals ]

100 flash memory storage system architecture

110 host

130 controller

131 host interface

133-0, 133-1 processor core

135 command queue

136 data cache

137 flash memory interface

138 DMA controller

139 data buffer

150 LUNs

150#0～150#11 LUN

CH # 0-CH #3 channel CH

CE # 0-CE #2 chip enable control signal

CQT, CQH pointer

139#0 Access subinterface

Plane 410# 0-470 # m

P #0 to P # (n) pages

490#1 ~ 490# n superpage

t_WB、t_RSNAP、t_DBSY、t_PRTime interval

900 schedule data table

Method steps S1010-S1090

1100. 1200 MPR-Lite scheduling data Table

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same or similar components or process flows.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of further features, integers, steps, operations, elements, components, and/or groups thereof.

The use of terms such as "first," "second," "third," and the like in the description of the claims is used for modifying elements in the claims and is not intended to indicate a priority order in time, precedence relationship, or the temporal order in which one element precedes another element or performs steps in the method, but rather is used to distinguish between elements having the same name.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe relationships between components may be similarly interpreted, such as "between" and "directly between," or "adjacent" and "directly adjacent," etc.

Refer to fig. 1. The flash memory system architecture 100 includes a Host (Host)110, a Controller (or Device side Device)130, and a Logical Block Number (LUN) 150. The system architecture can be implemented in electronic products such as personal computers, notebook computers (Laptop PCs), tablet computers, mobile phones, digital cameras, digital video cameras, and the like. Controller 130 may include a multi-core processor 133 that is a single computing element, collocated with two independent processor cores 133-0 and 133-1 for loading program code for firmware or software modules. Processor core 133-0 may communicate with host 110 via host interface 131 using Universal Flash Storage (UFS), Non-volatile memory (Nvme), Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral component interconnect Express (PCI-E), or other interface protocols. Processor core 133-1 may communicate with LUN 110 via Flash Interface 137 using a Double Data Rate (DDR) communication protocol, such as Open NAND Flash Interface (ONFI), Double Data Rate switch (DDR Toggle), or other Interface protocol.

Logical Unit Number (LUN) 150 provides a large amount of storage space, typically hundreds of Gigabytes, and even Terabytes, that can be used to store large amounts of user data, such as high resolution pictures, movies, and the like. The LUN150 includes a control circuit and a memory array, and the memory Cells in the memory array may be Triple Level Cells (TLCs) or Quad-Level Cells (QLCs). Data buffer (DataBuffer)139 may be used to buffer user data that is read from LUN150 and about to be knocked out to host 110. Referring to fig. 2, the flash interface 137 may include four input/output Channels (I/O Channels, hereinafter referred to as Channels CH) including Channels CH #0 to CH #3, each channel CH being connected to three LUNs, for example, channel CH #0 being connected to LUNs 150#0, 150#4 and 150# 8. Processor core 133-1 may drive flash interface 137 to issue one of the activation signals CE #0 to CE #2 to activate LUNs 150#0 to 150#3, LUNs 150#4 to 150#7, or LUNs 150#8 to 150#11, and then read user data from the activated LUNs in a parallel manner. For simplicity, the LUNs 150# 0-1 and the LUNs 150# 4-5 will be described below by taking only the channels CH # 0-CH #1 and CE # 0-CE #1 as examples, but not limited thereto.

The controller 130 may configure the command queue 135 to store a plurality of flash memory operation commands, such as a Read Page (Read Page) command, a Program Page (Program Page) command, an Erase Block (Erase Block) command, and so on. The flash memory operation command may be related to a Host command (Host Commands) issued by the Host 110 but not yet processed, such as a Host read command, a Host write command, and the like, or may be a command autonomously issued by the controller 130.

The command queue 135 may be implemented in a Static Random Access Memory (SRAM) that includes a collection of entries (entries). Each entry in the command queue 135 may store one flash memory operation command and related information. The flash memory operation commands in the set can be stored in sequence according to the arrival time. The basic principle of operation of the set is to add a flash memory operation command (which may be referred to as enqueue) by processor core 133-0 from an ending location (such as the location pointed to by pointer CQT), and to remove a flash memory operation command (which may be referred to as dequeue) by processor core 133-1 from a starting location (such as the location pointed to by pointer CQH). However, to optimize the data read operation, the first flash memory operation command added to the command queue 135 need not be the first to be removed. In addition, the controller 130 may also use a Stack (Stack) to store the flash memory operation command, which is not limited to this.

The LUN150 includes a plurality of Planes (Planes), and referring to fig. 4, for example, the LUN150#0 includes 4 Planes (Planes), which includes: planes 410 through 470. Each plane includes a plurality of Physical Blocks (referred to as Blocks), which include Blocks 410# 0-m, for example, in plane 410, where m is a positive integer. Each block contains multiple Pages (Pages), exemplified by block 410#0, which contains Pages P #0 through P # n, n being a positive integer. Each page P includes a plurality of NAND Memory Cells (Memory Cells), and the NAND Memory Cells may be three-tier Cells or four-tier Cells. In some embodiments, when each NAND memory cell is a three-layer cell and can record 8 states, one word line can include page P #0 (which can be referred to as the lowest-bit page, MSB page), page P #1 (which can be referred to as the middle-bit page, CSB, Center significantpage), and page P #2 (which can be referred to as the highest-bit page, LSB page). When each NAND memory cell is a four-tier cell and can record 16 states, a TSB (Top Bit) page is included in addition to the MSB, CSB, and LSB pages. Blocks of one of the different planes in the same LUN150 may virtually form a Big Block (Big Block), and blocks of different LUNs 150 may virtually form a super Block (SuperBlock).

The Data cache 136 and/or the Data Buffer (Data Buffer)139 may store a Logical-Physical Mapping Table (L2P Mapping Table) that needs to be searched when Data is read, and the L2P Mapping Table records Mapping information of a Logical address and a Physical address of each piece of Data. The data cache 136 may be implemented in an SRAM, and the data cache 139 may be implemented in a pre-allocated portion of a Dynamic Random Access Memory (DRAM).

Although the memory Cells in each block or page are TLCs or QLCs, the controller 130 may employ a Single Logical Cells (SLCs) mode to program data into the block or page, so as to increase the speed of data reading and data programming. To facilitate management of the block programming mode, the controller 130 preferably creates and maintains a Physical Configuration Table (Physical Configuration Table) to record the programming mode of each block, i.e., the default mode (TLC or QLC) or SLC mode, and stores the Physical Configuration Table in the data cache 136. In a data reading operation, the controller 130 can identify the programming mode of each block or page by searching the physical configuration data table, and thus, the data of the block or page can be read in a proper reading manner.

The controller 130 may output a Read Page command for reading a Page of a block in one plane of the LUN150, and may also output a Read Page Multi-plane (Read Page Multi-plane) command for reading data of a Page of a block in a different plane. However, sometimes the host 110 does not need a full page of data, but only 4KB of data in one page. At this time, the controller 130 may utilize a fragment Read (Snap Read) command to Read a portion of data in one page. With respect to the fragment read operation, refer to fig. 5. Waveform 510 shows the clock type of data lines DQ [7:0] coupled between LUN150 and flash interface 137, with 1 "CMD" clock indicating the primary command transmitted from

flash interface

137, 5 "Addr" clocks indicating the physical address of the desired LUN 137 to be read transmitted from

flash interface

137, and 1 "CMD" clock indicating the Confirm (Confirm) command transmitted from flash interface 137, and finally, "DOUT" indicating the data output from LUN 150. Waveform 520 is an exemplary fragmented read command of waveform 510, the main command is 00h, and the confirm command is 20h, therefore, LUN150 determines that the operation command is a fragmented read command, and reads a portion of page data of a specified page (physical address).

The partial page data is, for example, 8KB data in 16KB page data, referring to fig. 6, wherein the 8KB data can be selected from three different sections in the page: a first 8KB segment 625, a middle 8KB segment 645, and a last 8KB segment 665, each 8KB segment preferably being greater than or equal to 8KB in length. In addition, the partial page data may also be, for example, 4KB data in 16KB page data, i.e., the 16KB page region is divided into a first 4KB segment, a second 4KB segment, a third 4KB segment and a fourth 4KB segment, and each 4KB segment is preferably greater than or equal to 4KB in length.

In addition, since the LUN150 includes multiple Planes (Planes), the controller 130 may output a Multi-Page Read reduce (MPR-Lite) command for reading fragment data on pages in the multiple Planes in the LUN150, referring to fig. 6, for example: the first 8KB segment 625 in page P #0 of

planes

810 and 830, and the last 8KB segment 665 in page P #1 of

planes

830 and 850. The MPR-Lite command may improve the read performance of fragment data.

Referring to FIG. 1, for data read, for example, the processor core 133-0 may obtain a data read command from the host 110 through the host interface 131, wherein the data read command provides a logical address of the target data. The processor core 133-0 can obtain the page location (physical address) of the target data in the LUN150 by looking up the L2P mapping table and the logical address, and can know the programming mode of the target data through the physical configuration table. Next, the processor core 133-0 generates a flash memory operation command to the command queue 135, wherein the flash memory operation command includes a physical address of the target data.

The controller 130 may utilize a command queue 135 to store a plurality of flash memory operation commands, such as: 64 flash memory operation commands. The processor core 133-1 may establish and maintain a schedule (SchedulingTable)900 and/or a pending Table (Standby Table)910 in the data cache 136 to order the flash memory operation commands in the command queue 135 so that the flash memory operation commands are executed more efficiently. Referring to FIG. 9, for example, command queue 135 currently stores 13 read page commands, labeled "a" through "m," respectively. The processor core 133-1 records the read page command for reading the specific LUN150 into a specific field of the schedule table 900, for example, enqueues the read page commands "b", "a", "d" into the schedule table 900 to read the pages of the LUN150#0, LUN150#4 and LUN150# 1, respectively, so that the processor core 133-1 can output the read page commands "b", "a", "d" to the LUN150#0, LUN150#4 and LUN150# 1 in a synchronous and interleaved (Interleaving) manner. The processor core 133-1 enqueues the read page commands "c", "e" to "m" into the table to be scheduled, and then enqueues the read page commands "e", "c" and "g" into the table to be scheduled 900 after the read page commands "b", "a" and "d" in the table to be scheduled 900 are executed. Then, the read page commands "j", "f", and "k" in the table to be hit are enqueued to the schedule table 900, and finally, the read page commands "i" and "m" in the table to be hit are enqueued to the schedule table 900. Therefore, it takes 4 cycles for 13 read page commands to complete. In some embodiments, the processor core 133-1 only establishes and maintains the schedule 900 and stores the flash memory operation commands to the schedule 900 in sequence, and after the processor core 133-1 completes executing the first column of flash memory operation commands, the processor core 133-1 continues to execute the next column of flash memory operation commands, and so on.

If the target data is 4KB or 8KB of data in a page, the controller 130 can utilize the command queue 135 to store fragment read commands instead of read page commands. Alternatively, the slice read command in the command queue 135 is executed by MPR-Lite command, i.e. multiple slice read commands are integrated into one MPR-Lite command. When the slice read commands are integrated into one MPR-Lite command, the controller 130 needs to change the slice read commands into multi-page read commands, wherein the confirm command is 32h, and the last slice read command is not changed, and the confirm command is 20h, so that the controller 130 can not only execute the slice read commands in a synchronous and staggered manner, but also increase the execution efficiency of the slice read commands. Referring to fig. 11, the slice read command "b" is to read target data in the LUN150#0, the slice read commands "a" and "h" are to read target data of different planes in the LUN150#4, and the slice read commands "d" and "g" are to read target data of different planes in the LUN150# 1, so that the controller 130 can execute the slice read commands "a", "b", "d", "h", and "g" as MPR-Lite commands, and thus the controller 130 can execute 5 slice read commands together instead of 3 slice read commands, in other words, the MPR-Lite command can improve the execution efficiency of the slice read commands by 66%.

In some embodiments, in response to the MPR Lite command as described above, the processor core 133-1 may perform the flash memory operation command ordering function shown in FIG. 10 when loading and executing a specific software or firmware command.

Step S1010: processor core 133-1 provides an MPR-Lite schedule data table in data cache 136. Compared to the schedule table 900 and the standby table 910 shown in fig. 9, the MPR-Lite schedule data table provides a fine distinction for each LUN, which is advantageous for integrating two or more slice read commands into one MPR-Lite operation.

Referring to the MPR-Lite schedule data table 1100 shown in fig. 11, two columns "Plane 0/1" and "Plane 2/3" may be included for each LUN, for dividing the fragment read command into one column of storage cells according to the physical address to be read. For example, the storage grid in the third column of the MPR-Lite schedule data table 1100 is used for recording a fragment read command for reading data on the plane 810 and/or the plane 830; and the fourth column of the memory cells therein is used for recording a fragment read command for reading data on plane 850 and/or plane 870.

In addition, since data is programmed to the block, a default programming mode may be adopted, such as: TLC or QLC mode, SLC mode may also be used. Therefore, when multiple slice read commands are integrated into one MPR-Lite command, the same program pattern is required for the target data to be read by the multiple slice read commands, and thus the MPR-Lite schedule data table 1100 may be slightly modified into the MPR-Lite schedule data table 1200, as shown in fig. 12, for each LUN, three columns "Main P0/1", "SLC P2/3" and "QLC P2/3" may be included for distinguishing each flash memory operation command into one column of storage cells according to the physical address to be read and the pattern used. For example, the storage grid in the fourth column of the MPR-lite schedule data table 1200 is used for recording flash memory operation commands for reading data on the plane 810 and/or the plane 830, regardless of the reading mode used; wherein the fifth column of cells is used to record flash memory operation commands for reading data on plane 850 and/or plane 870 using SLC mode; and the sixth column of cells therein is used to record flash memory operation commands for reading data on plane 850 and/or plane 870 using the QLC mode.

Next, referring to fig. 10, the processor core 133-1 repeatedly executes a loop (steps S1030 to S1090) for arranging each flash memory operation command in the command queue 135 into an appropriate storage cell in the MPR-Lite schedule data table. In each round, the details are as follows:

step S1030: processor core 133-1 retrieves physical address information for one or more not-yet-ordered flash memory operation commands from command queue 135. If a flash memory operation command indicates to read data on Plane 830 and Plane 850, processor core 133-1 may arrange the flash memory operation command into a storage cell in a field associated with Plane 830, such as column "Plane 0/1" in FIG. 11 or column "Main P0/1" in FIG. 12.

Step S1070: and arranging each flash memory operation command to an appropriate storage grid in the MPR-Lite scheduling data table according to the physical address and other related information. Referring to the use case of fig. 11, the storage grid in the third column of the MPR-Lite schedule data table 1100 is used to record fragment read commands "a", "c", and "f" for reading data on the plane 810 and/or the plane 830; and the fourth column of the memory cells therein is used for recording the fragment read commands "h" and "i" for reading data on the plane 850 and/or the plane 870.

In other embodiments of step S1070, other information related to the memory operation command may include the mode used by the flash memory operation command for reading. The processor core 133-1 can search the contents of the physical configuration table in the data cache 136 to determine which mode the flash memory operation command needs to be read according to the programming mode of the block corresponding to the physical address. Referring to the use case of fig. 12, a storage cell in the fourth column of the MPR-Lite schedule data table 1200 is used to record fragment read commands "a" and "f" for reading data on the plane 810 and/or the plane 830; wherein the fifth column of memory cells is used to record fragment read commands "h" and "i" for reading data on plane 850 and/or plane 870 using SLC mode; and the sixth column of cells therein is used to record a segment read command "c" for reading data on plane 850 and/or plane 870 using the QLC mode.

Following the sorting results described in FIG. 11, FIG. 13 shows a use case for selecting flash memory operation commands. For example, in one batch, processor core 133-1 drives flash interface 137 to send a read page command to LUN150#0 for reading the data at the physical address specified by the fragment read command "b"; sending a read page multi-plane command to LUN150#4 for reading the data at the physical addresses specified by the fragment read commands "a" and "h", sending a read page multi-plane command to LUN150# 1 for reading the data at the physical address specified by the fragment read command "d", and sending a fragment read command to LUN150# 1 for reading the data at the physical address specified by the memory operation command "g" to form an MPR-lite operation.

Following the sorting results described in FIG. 12, FIG. 14 shows a use case for selecting a memory operation command. For example, in one batch, the processor core 133-1 determines that the target data is programmed to SLC mode, and thus drives the flash interface 137 to send a read page multi-plane command to LUN150#0 for reading the data of the physical address specified by the segment read command "b"; sending a read page multi-plane command to LUN150#4 for the data at the physical addresses specified by the fragment read commands "a" and "h", and sending a fragment read command to LUN150# 1 for reading the data at the physical address specified by the fragment read command "d", to form an MPR-lite operation.

The processor core 133-1 may execute the fragment read command as described above batch by referring to the sorting result of the MPR-Lite schedule data table, but when the processor core 133-1 reads the fragment data of the page on the multi-plane by using the MPR-Lite command instead, the efficiency of data reading is improved, and the efficiency of the fragment read operation is improved. In the 4K random read Q64/T4 test, the MPR-Lite command can improve the average read data hit rate by about 30-50% compared to the fragmented read command. The hit rate of a read is defined as the proportion of read data from LUN150 that is retained by flash interface 137 to be returned to host 110. For example, when all the 8K data read by the segment read command is reserved to reply to the host 110, the hit rate of this read is 100%. When the 8K data read by the segment read command is only half reserved to be returned to the host 110, the hit rate of this read is 50%.

All or a portion of the steps of the methods described herein may be implemented in computer program code, such as the operating system of a computer, driver code for specific hardware in a computer, or software program code. In addition, other types of programs as shown above may also be implemented. Those skilled in the art can write the method of the present invention as a computer program code, which will not be described for the sake of brevity. The computer program implemented according to the embodiments of the present invention may be stored in a suitable computer readable data carrier, such as a DVD, a CD-ROM, a USB, a hard disk, or may be disposed in a network server accessible via a network (e.g., the internet, or other suitable carrier).

Although the components described above are included in fig. 1, it is not excluded that more additional components may be used to achieve better technical results without departing from the spirit of the present invention. Further, although the flowchart of fig. 10 is executed in the order specified, a person skilled in the art can modify the order of the steps without departing from the spirit of the invention to achieve the same effect, and therefore, the invention is not limited to use of only the order described above. In addition, a person skilled in the art may also integrate several steps into one step, or perform more steps in sequence or in parallel besides the steps, and the present invention is not limited thereby.

While the present invention has been illustrated by the above examples, it is noted that these descriptions are not intended to limit the present invention. Rather, this invention encompasses modifications and similar arrangements as would be apparent to one skilled in the art. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A computer-readable storage medium for fragment data reading on multiple planes, storing computer program code executable by a processing unit, the computer program code implementing the following steps when executed by the processing unit:

providing a scheduling data table;

arranging each memory operation command in a command queue to a storage grid in the scheduling data table according to the physical address information of the memory operation command;

selecting two or more memory operation commands for a logical unit number according to the contents of the scheduling data table, wherein each of the selected memory operation commands requests to read data less than the length of one cross-plane page;

driving a flash memory interface to complete multi-page reading simplified operation, and reading the data requested by the selected memory operation command from the logic unit number; and

and replying the read data to the host.

2. The computer-readable storage medium of fragment data reads on a multi-plane of claim 1, wherein the multi-page read reduce operation comprises: and driving the flash memory interface to send one or more page reading multi-plane commands and then send a fragment reading command to the logic unit number, and reading the data of the physical address specified by the selected memory operation command.

3. The computer-readable storage medium of fragment data read on a multi-plane of claim 2, wherein the read page multi-plane command and the fragment read command are each to read fragment data on a different cross-plane page.

4. The computer-readable storage medium of fragment data read on a multi-plane of claim 2, wherein the read page multi-plane command and the fragment read command operate in one mode.

5. The computer-readable storage medium of fragment data reading on a multi-plane of claim 4, wherein the mode is a single-layer unit, a three-layer unit, or a four-layer unit mode.

6. A method for reading fragment data on multiple planes, performed by a processing unit, the method comprising:

providing a scheduling data table;

and replying the read data to the host.

7. The method of claim 6, wherein the multi-page read compaction operation comprises: and driving the flash memory interface to send one or more page reading multi-plane commands and then send a fragment reading command to the logic unit number, and reading the data of the physical address specified by the selected memory operation command.

8. The method of claim 7, wherein the read page multi-plane command requires a data ready wait time shorter than the fragment read command.

9. The fragment data reading method on a multi-plane according to claim 6, wherein each column in the schedule data table is for recording information of reading a memory operation command on a specific plane in a specific logical unit number.

10. The fragment data reading method on a multi-plane according to claim 6, wherein each column in the schedule data table is used to record information of a memory operation command to read a first plane, a second plane and use a first mode, or the second plane and use a second mode in a specific logical unit number.