TWI781846B - Unbalanced plane management method, associated data storage device and controller thereof - Google Patents
Unbalanced plane management method, associated data storage device and controller thereof Download PDFInfo
- Publication number
- TWI781846B TWI781846B TW110145772A TW110145772A TWI781846B TW I781846 B TWI781846 B TW I781846B TW 110145772 A TW110145772 A TW 110145772A TW 110145772 A TW110145772 A TW 110145772A TW I781846 B TWI781846 B TW I781846B
- Authority
- TW
- Taiwan
- Prior art keywords
- block
- plane
- blocks
- super
- controller
- Prior art date
Links
Images
Landscapes
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Apparatus For Radiation Diagnosis (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
Description
本發明係有關於快閃記憶體(Flash memory)之存取(access),尤指一種非對稱型平面管理(Unbalanced Plane Management)方法以及資料儲存裝置及其控制器。 The present invention relates to flash memory (Flash memory) access, especially an asymmetric plane management (Unbalanced Plane Management) method, data storage device and its controller.
快閃記憶體可廣泛地應用於各種可攜式或非可攜式資料儲存裝置(例如:符合SD/MMC、CF、MS、XD或UFS標準之記憶卡;又例如:固態硬碟;又例如:符合UFS或EMMC規格之嵌入式(embedded)儲存裝置)中。以常用的NAND型快閃記憶體而言,最初有單階細胞(single level cell,SLC)、多階細胞(multiple level cell,MLC)等類型的快閃記憶體。由於記憶體的技術不斷地發展,較新的資料儲存裝置產品可採用三階細胞(triple level cell,TLC)快閃記憶體,甚至四階細胞(quadruple level cell,QLC)快閃記憶體。為了確保資料儲存裝置對快閃記憶體之存取控制能符合相關規範,快閃記憶體的控制器通常備有某些管理機制以妥善地管理其內部運作。 Flash memory can be widely used in various portable or non-portable data storage devices (for example: memory cards that meet SD/MMC, CF, MS, XD or UFS standards; another example: solid-state hard drives; another example : In an embedded storage device conforming to UFS or EMMC specifications). For the commonly used NAND flash memory, there are initially single level cell (SLC) and multiple level cell (MLC) types of flash memory. Due to the continuous development of memory technology, newer data storage device products can use triple level cell (TLC) flash memory, and even quadruple level cell (QLC) flash memory. In order to ensure that the access control of the data storage device to the flash memory complies with relevant regulations, the controller of the flash memory usually has some management mechanism to properly manage its internal operation.
依據相關技術,有了這些管理機制的資料儲存裝置還是有不足之處。舉例來說,多個快閃記憶體裸晶(Die)可被同時使用以提升存取效能。然而,某一個快閃記憶體裸晶的好區塊的數量可能限制這些快閃記憶體裸晶之各自的區塊的使用率。例如,在這些好區塊的數量很小、或者這些好區塊的分佈不平衡的情況下,無法得到需要的儲存容量。因此,需要一種新穎的方法及相關架構,以在沒有副作用或較不可能帶來副作用之狀況下實現具有可靠的管理 機制之資料儲存裝置。 According to related technologies, the data storage devices with these management mechanisms still have deficiencies. For example, multiple flash memory Dies can be used simultaneously to improve access performance. However, the number of good blocks for a certain Flash die may limit the utilization of the respective blocks of the Flash die. For example, when the number of these good blocks is small, or the distribution of these good blocks is unbalanced, the required storage capacity cannot be obtained. Therefore, there is a need for a novel method and related framework to achieve reliable management with no side effects or less likely to cause side effects Mechanism data storage device.
本發明之一目的在於提供一種非對稱型平面管理方法以及相關之資料儲存裝置及其控制器,以解決上述問題。 An object of the present invention is to provide an asymmetric plane management method, a related data storage device and its controller, so as to solve the above problems.
本發明之另一目的在於提供一種非對稱型平面管理方法以及相關之資料儲存裝置及其控制器,以在沒有副作用或較不可能帶來副作用之狀況下將可靠的管理機制賦予資料儲存裝置。 Another object of the present invention is to provide an asymmetric planar management method and a related data storage device and its controller, so as to provide a reliable management mechanism to the data storage device without or less likely to cause side effects.
本發明之至少一實施例提供一種非對稱型平面管理方法,其中該非對稱型平面管理方法係應用於一資料儲存裝置,該資料儲存裝置包含一非揮發性記憶體(non-volatile memory,NV memory),該非揮發性記憶體包含複數個非揮發性記憶體元件(NV memory element),以及該複數個非揮發性記憶體元件包含複數個區塊。該非對稱型平面管理方法可包含:設定一非平衡平面數量(unbalanced plane number),其中該非平衡平面數量小於一最大平面數量,且該最大平面數量代表該複數個非揮發性記憶體元件之各自的平面的數量的總和;選取該最大平面數量減去該非平衡平面數量的至少一平面,並將該至少一平面的至少一組區塊記錄至一區塊省略表(block skip table);依據區塊編號為索引,將未選取的平面的區塊組成超級區塊,其中所述超級區塊分別對應於所述區塊編號;以及記錄全部超級區塊的總容量以及該非平衡平面數量,以產生多種儲存容量的記錄中的一最新的記錄,以供進一步設定該資料儲存裝置的儲存容量組態,其中所述全部超級區塊包含所述超級區塊。 At least one embodiment of the present invention provides an asymmetric plane management method, wherein the asymmetric plane management method is applied to a data storage device, and the data storage device includes a non-volatile memory (non-volatile memory, NV memory ), the non-volatile memory includes a plurality of non-volatile memory elements (NV memory elements), and the plurality of non-volatile memory elements includes a plurality of blocks. The asymmetric plane management method may include: setting an unbalanced plane number (unbalanced plane number), wherein the unbalanced plane number is less than a maximum plane number, and the maximum plane number represents each of the plurality of non-volatile memory elements The sum of the number of planes; selecting at least one plane of the maximum number of planes minus the number of unbalanced planes, and recording at least one group of blocks of the at least one plane into a block skip table; according to the block The number is used as an index, and the blocks of the unselected planes are composed into super blocks, wherein the super blocks correspond to the block numbers respectively; and the total capacity of all super blocks and the number of unbalanced planes are recorded to generate various A newest record among the records of storage capacity is used for further setting the storage capacity configuration of the data storage device, wherein all the superblocks include the superblock.
本發明之至少一實施例提供一種資料儲存裝置,其可包含:一非揮發性記憶體,用來儲存資訊,其中該非揮發性記憶體包含複數個非揮發性記憶體元件,以及該複數個非揮發性記憶體元件包含複數個區塊;以及一控制器, 耦接至該非揮發性記憶體,用來控制該資料儲存裝置之操作。該控制器可包含一處理電路,其中該處理電路可依據來自一主機(host device)的複數個主機命令(host command)控制該控制器,以容許該主機透過該控制器存取該非揮發性記憶體。例如:該控制器設定一非平衡平面數量,其中該非平衡平面數量小於一最大平面數量,且該最大平面數量代表該複數個非揮發性記憶體元件之各自的平面的數量的總和;該控制器選取該最大平面數量減去該非平衡平面數量的至少一平面,並將該至少一平面的至少一組區塊記錄至一區塊省略表;該控制器依據區塊編號為索引,將未選取的平面的區塊組成超級區塊,其中所述超級區塊分別對應於所述區塊編號;以及該控制器記錄全部超級區塊的總容量以及該非平衡平面數量,以產生多種儲存容量的記錄中的一最新的記錄,以供進一步設定該資料儲存裝置的儲存容量組態,其中所述全部超級區塊包含所述超級區塊。 At least one embodiment of the present invention provides a data storage device, which may include: a non-volatile memory for storing information, wherein the non-volatile memory includes a plurality of non-volatile memory elements, and the plurality of non-volatile memory elements The volatile memory element includes a plurality of blocks; and a controller, Coupled to the non-volatile memory, used to control the operation of the data storage device. The controller can include a processing circuit, wherein the processing circuit can control the controller according to a plurality of host commands (host commands) from a host (host device), so as to allow the host to access the non-volatile memory through the controller body. For example: the controller sets an unbalanced plane number, wherein the unbalanced plane number is less than a maximum plane number, and the maximum plane number represents the sum of the respective plane numbers of the plurality of non-volatile memory elements; the controller Selecting at least one plane of the maximum number of planes minus the number of unbalanced planes, and recording at least one group of blocks of the at least one plane into a block omission table; the controller indexes the unselected Blocks of planes form super blocks, wherein the super blocks respectively correspond to the block numbers; and the controller records the total capacity of all super blocks and the number of unbalanced planes to generate records of various storage capacities A latest record for further setting the storage capacity configuration of the data storage device, wherein all the superblocks include the superblock.
本發明之至少一實施例提供一種資料儲存裝置之控制器,其中該資料儲存裝置包含該控制器與一非揮發性記憶體,該非揮發性記憶體包含複數個非揮發性記憶體元件,以及該複數個非揮發性記憶體元件包含複數個區塊。該控制器可包含一處理電路,其中該處理電路可依據來自一主機的複數個主機命令控制該控制器,以容許該主機透過該控制器存取該非揮發性記憶體。例如:該控制器設定一非平衡平面數量,其中該非平衡平面數量小於一最大平面數量,且該最大平面數量代表該複數個非揮發性記憶體元件之各自的平面的數量的總和;該控制器選取該最大平面數量減去該非平衡平面數量的至少一平面,並將該至少一平面的至少一組區塊記錄至一區塊省略表;該控制器依據區塊編號為索引,將未選取的平面的區塊組成超級區塊,其中所述超級區塊分別對應於所述區塊編號;以及該控制器記錄全部超級區塊的總容量以及該非平衡平面數量,以產生多種儲存容量的記錄中的一最新的記錄,以供進一步設定該資料 儲存裝置的儲存容量組態,其中所述全部超級區塊包含所述超級區塊。 At least one embodiment of the present invention provides a controller for a data storage device, wherein the data storage device includes the controller and a non-volatile memory, the non-volatile memory includes a plurality of non-volatile memory elements, and the The plurality of non-volatile memory elements comprise a plurality of blocks. The controller can include a processing circuit, wherein the processing circuit can control the controller according to a plurality of host commands from a host to allow the host to access the non-volatile memory through the controller. For example: the controller sets an unbalanced plane number, wherein the unbalanced plane number is less than a maximum plane number, and the maximum plane number represents the sum of the respective plane numbers of the plurality of non-volatile memory elements; the controller Selecting at least one plane of the maximum number of planes minus the number of unbalanced planes, and recording at least one group of blocks of the at least one plane into a block omission table; the controller indexes the unselected Blocks of planes form super blocks, wherein the super blocks respectively correspond to the block numbers; and the controller records the total capacity of all super blocks and the number of unbalanced planes to generate records of various storage capacities An up-to-date record for further configuration of the data The storage capacity configuration of the storage device, wherein all the superblocks include the superblock.
本發明的好處之一是,透過仔細設計之管理機制,本發明能針對該控制器的運作進行妥善的控制,尤其,使資料儲存裝置能利用不平衡平面的方式,例如,使用在超級區塊(Super Block)內可更改的數量的平面而不是使用全部數量的平面。於是,本發明能打破關於NAND型快閃記憶體的好區塊的數量的限制,以整合出最大的容量;或是,在特定的容量需求下,有效地整合出充足的超級區塊,達到最佳化效能。另外,依據本發明之實施例來實施並不會增加許多額外的成本。因此,相關技術的問題可被解決,且整體成本不會增加太多。相較於傳統架構,本發明能在沒有副作用或較不可能帶來副作用之狀況下達到資料儲存裝置之最佳化效能。 One of the advantages of the present invention is that, through a carefully designed management mechanism, the present invention can properly control the operation of the controller, especially, enabling data storage devices to utilize unbalanced planes, for example, in superblocks Changeable number of planes within (Super Block) instead of using the full number of planes. Therefore, the present invention can break the restriction on the number of good blocks of NAND flash memory to integrate the maximum capacity; or, under a specific capacity requirement, effectively integrate enough super blocks to achieve Optimize performance. In addition, the implementation according to the embodiments of the present invention does not add much extra cost. Therefore, the problems of the related art can be solved without increasing the overall cost too much. Compared with the traditional structure, the present invention can achieve the optimal performance of the data storage device without or less likely to cause side effects.
50:主機 50: Host
100:資料儲存裝置 100: data storage device
110:記憶體控制器 110: Memory controller
112:微處理器 112: Microprocessor
112C:程式碼 112C: code
112M:唯讀記憶體 112M: read-only memory
114:控制邏輯電路 114: Control logic circuit
116:緩衝記憶體 116: buffer memory
118:傳輸介面電路 118: Transmission interface circuit
120:非揮發性記憶體 120: Non-volatile memory
122,122-1,122-2~122-N:非揮發性記憶體元件 122,122-1,122-2~122-N: non-volatile memory components
0-0~0-199,1-0~1-199,2-0~2-199,3-0~3-199,4-0~4-199,5-0~5-199,6-0~6-199,7-0~7-199:區塊索引 0-0~0-199,1-0~1-199,2-0~2-199,3-0~3-199,4-0~4-199,5-0~5-199,6- 0~6-199,7-0~7-199: block index
S10,S12,S14,S16,S18,S20,S22:步驟 S10, S12, S14, S16, S18, S20, S22: steps
ORPHAN_BLOCK_TABLE:孤兒區塊表 ORPHAN_BLOCK_TABLE: Orphan block table
BLOCKSKIPIDX:區塊省略索引 BLOCKSKIPIDX: block skip index
第1圖為依據本發明一實施例之一種資料儲存裝置與一主機(host device)的示意圖。 FIG. 1 is a schematic diagram of a data storage device and a host device according to an embodiment of the present invention.
第2圖繪示針對超級區塊的一管理方案的示意圖。 FIG. 2 shows a schematic diagram of a management scheme for superblocks.
第3圖繪示依據本發明一實施例之一超級區塊管理方案。 FIG. 3 illustrates a superblock management scheme according to an embodiment of the present invention.
第4圖繪示壞區塊分佈的一個例子。 Figure 4 shows an example of bad block distribution.
第5圖繪示依據本發明另一實施例之一超級區塊管理方案。 FIG. 5 illustrates a superblock management scheme according to another embodiment of the present invention.
第6圖繪示依據本發明一實施例之一種非對稱型平面管理方法的一工作流程。 FIG. 6 shows a workflow of an asymmetric plane management method according to an embodiment of the present invention.
請參考第1圖,第1圖為依據本發明一第一實施例之一種資料儲存裝置100與一主機(Host Device)50的示意圖。例如:資料儲存裝置100可為固態
硬碟(Solid State Drive,SSD)。另外,主機50的例子可包含(但不限於):多功能行動電話(Multifunctional Mobile Phone)、平板電腦(Tablet)、以及個人電腦(Personal Computer)諸如桌上型電腦與膝上型電腦。依據本實施例,資料儲存裝置100可包含一控制器諸如記憶體控制器110,且可另包含非揮發性(Non-Volatile)記憶體120,其中該控制器係用來存取(Access)非揮發性記憶體120,且非揮發性記憶體120係用來儲存資訊。
Please refer to FIG. 1 , which is a schematic diagram of a
非揮發性記憶體120可包含複數個非揮發性記憶體元件122-1、122-2、...與122-N,其中符號「N」可代表大於一的正整數。例如:非揮發性記憶體120可為快閃記憶體(Flash memory),而非揮發性記憶體元件122-1、122-2、...與122-N可分別為複數個快閃記憶體晶片或複數個快閃記憶體裸晶,但本發明並不限於此。此外,資料儲存裝置100可以還包括揮發性記憶體元件以緩存資料,其中,揮發性記憶體元件較佳為動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)。上述揮發性記憶體元件可提供適當的資料暫存空間以緩存資料,或是僅提供小量的資料暫存空間以緩存小量資料,此架構又稱為部分DRAM(Partial DRAM)。另外,揮發性記憶體元件為非必要元件。
The
記憶體控制器110可包含處理電路諸如微處理器112、儲存器諸如唯讀記憶體(Read Only Memory,ROM)112M、控制邏輯電路114、緩衝記憶體116、與傳輸介面電路118,其中這些元件可透過匯流排彼此耦接。緩衝記憶體116較佳為靜態隨機存取記憶體(Static Random Access Memory,SRAM)。舉例來說,如果資料儲存裝置100更配置有上述DRAM,記憶體控制器110可利用緩衝記憶體116諸如SRAM作為第一層快取(Cache),並利用DRAM作為第二層快取。DRAM的資料儲存量較佳大於緩衝記憶體116的資料儲存量,而緩衝記憶體116所緩衝處理的資料可源自於DRAM或非揮發性記憶體120。
The
本實施例之唯讀記憶體112M係用來儲存程式碼112C,而微處理器
112則用來執行程式碼112C以控制對非揮發性記憶體120之存取。請注意,程式碼112C亦得儲存在緩衝記憶體116或任何形式之記憶體內。此外,控制邏輯電路114可包含至少一錯誤更正碼(Error Correction Code,ECC)電路(未顯示),以保護資料、及/或進行錯誤更正,而傳輸介面電路118可符合特定通訊標準(諸如串列高級技術附件(Serial Advanced Technology Attachment,SATA)標準、快捷外設互聯(Peripheral Component Interconnect Express,PCIE)標準或非揮發性記憶體快捷(Non-Volatile Memory Express,NVME)標準且可依據特定通訊標對主機50進行通訊。
The
於本實施例中,主機50可傳送複數個主機命令(Host Command)至資料儲存裝置100,記憶體控制器110再依據主機命令而對非揮發性記憶體120進行存取(例如讀取或寫入資料),其中上述資料較佳為源自於主機50之使用者資料。主機命令包括邏輯位址,例如:邏輯區塊位址(Logical Block Address,LBA)。記憶體控制器110可接收主機命令並將主機命令分別轉譯成記憶體操作命令(簡稱操作命令),再以操作命令控制非揮發性記憶體120讀取、寫入(Write)/編程(Program)非揮發性記憶體120當中特定實體位址之頁面(Page)。
In this embodiment, the
記憶體控制器110將資料的邏輯位址與實體位址之間的映射關係記錄於邏輯對實體位址(Logical-to-Physical Address,L2P)映射表,其中,實體位址可由通道(Channel)編號、邏輯單元編號(Logical Unit Number,LUN)、平面(Plane)編號、區塊編號、頁面編號以及偏移量(Offset)所組成。於某些實施例中,實體位址的實施可予以變化。例如,實體位址可包含通道編號、邏輯單元編號、平面編號、區塊編號、頁面編號、及/或偏移量。
The
L2P映射表可儲存於非揮發性記憶體120中之系統區塊中,且可分割成多個群組(Group)映射表,每一群組映射表記錄一段邏輯位址的映射關係。系統區塊較佳為加密區塊且以SLC模式進行資料的編程。記憶體控制器110可依
緩衝記憶體116的容量大小而將該多個群組映射表中的一部分或全部群組映射表從非揮發性記憶體120載入緩衝記憶體116,以供快速參考,但本發明不限於此。當使用者資料更新時,記憶體控制器110可依據使用者資料的最新映射關係來更新群組映射表的內容。群組映射表的大小較佳不大於非揮發性記憶體元件122-n的一個頁面(Page)的大小,例如16KB(kilobytes;千位元組),其中符號「n」可代表區間[1,N]中之任一正整數,但本發明不限於此。例如,群組映射表的大小可為4KB或1KB。
The L2P mapping table can be stored in the system block of the
非揮發性記憶體元件122-n可包含多個平面(Planes),諸如平面#0、#1、#2與#3,每一個平面包含多個區塊,每一區塊包含多個頁面。在此情況下,記憶體控制器110可將平面#0~#3之各自一個區塊組合成一個大區塊,則大區塊的大小等於一個區塊的大小的4倍。
The non-volatile memory device 122-n may include multiple planes, such as
記憶體控制器110可將多個通道,例如2個通道CH#0與CH#1,中各自的一個非揮發性記憶體元件122-n之各自的一個大區塊可組合成一個超級區塊(Super Block,SB),則超級區塊的大小等於一個區塊的大小的8倍,且此2個非揮發性記憶體元件122-n可由同一晶片啟用(Chip Enable,CE)訊號所控制,但本發明不限於此。例如,在通道數量等於4的設定下,諸如通道CH#0~CH#3,通道CH#0~CH#3中的各自的一個非揮發性記憶體元件之各自的一個大區塊亦可組成一個超級區塊,亦可由一個晶片啟用訊號所控制。
The
第2圖繪示針對超級區塊的一管理方案的示意圖。非揮發性記憶體元件122-1、122-2、...與122-N可實施成複數個快閃記憶體裸晶,諸如裸晶#0與#1,其中裸晶#0與#1可作為上述2個通道CH#0與CH#1中各自的一個非揮發性記憶體元件122-n,並以此架構為例說明超級區塊的組成。裸晶#0可具有4個平面,因此,裸晶#0中的區塊可由4組區塊索引(Block Index)來表示,例如其區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-199}與{3-0,3-1,...,3-199}。
相仿地,裸晶#1亦可具有4個平面,因此,裸晶#1中的區塊亦可由4組區塊索引來表示,例如其區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-199}與{3-0,3-1,...,3-199}。
FIG. 2 shows a schematic diagram of a management scheme for superblocks. The non-volatile memory elements 122-1, 122-2, . It can be used as a non-volatile memory element 122-n in each of the above two
當組成超級區塊時,裸晶#0~#1可分別置於通道CH#0與CH#1,如此一來,超級區塊中的區塊可由區塊索引來表示,例如具有區塊索引格式[Die#,PLN#,BLK#]的8組區塊索引{[0,0,0],[0,0,1],...,[0,0,199]}、{[0,1,0],[0,1,1],...,[0,1,199]}、{[0,2,0],[0,2,1],...,[0,2,149]}、{[0,3,0],[0,3,1],...,[0,3,199]}、{[1,4,0],[1,4,1],...,[1,4,199]}、{[1,5,0],[1,5,1],...,[1,5,199]}、{[1,6,0],[1,6,1],...,[1,6,199]}以及{[1,7,0],[1,7,1],...,[1,7,199]},並且在區塊索引格式[Die#,PLN#,BLK#]中的Die#、PLN#與BLK#分別代表裸晶編號、平面編號與區塊編號,其中,裸晶編號與平面編號較佳為累進值(例如具有固定增量的一系列數值),有時裸晶編號會以通道編號來替代。另外,在上述架構中,由於超級區塊中的區塊來自八個平面,此種超級區塊又可稱為八平面超級區塊或平衡平面架構。 When forming a super block, bare dies #0~#1 can be placed in channels CH#0 and CH#1 respectively, so that the blocks in the super block can be represented by block index, for example, have a block index 8 sets of block indexes {[0,0,0],[0,0,1],...,[0,0,199]}, {[0,1] in the format [Die#,PLN#,BLK#] ,0],[0,1,1],...,[0,1,199]}, {[0,2,0],[0,2,1],...,[0,2,149]} , {[0,3,0],[0,3,1],...,[0,3,199]}, {[1,4,0],[1,4,1],..., [1,4,199]}, {[1,5,0],[1,5,1],...,[1,5,199]}, {[1,6,0],[1,6,1 ],...,[1,6,199]} and {[1,7,0],[1,7,1],...,[1,7,199]}, and in block index format [Die# , PLN#, BLK#] in Die#, PLN# and BLK# represent die number, plane number and block number respectively, wherein, die number and plane number are preferably progressive values (for example, with a fixed increment A series of values), sometimes the die number is replaced by the channel number. In addition, in the above architecture, since the blocks in the super block come from eight planes, this kind of super block can also be called an eight-plane super block or balanced plane architecture.
假設在理想情況下,裸晶#0與#1之各自的平面#0~#3可具有相同數量的好區塊(Good Block),例如200個好區塊,即區塊#0~#199都是好區塊,沒有一個是壞區塊(Bad Block)。於是,在理想情況下,記憶體控制器110可將裸晶#0與#1中的平面#0~#3之相同區塊編號的區塊組合成超級區塊,因此,可組合成200個超級區塊。由於所有的區塊都是好區塊,記憶體控制器110在此情況下可以組合最多數量的超級區塊,因此,資料儲存裝置100(例如SSD)可以提供理想的儲存容量。假設每一裸晶的儲存容量為64GB(Gigabytes;十億位元組),,資料儲存裝置100可以提供128GB的儲存容量。由於裸晶中的區塊被組合成超級區塊,因此,資料儲存裝置100可以提供理想(較佳)的存取效能。
Assume that under ideal conditions, the
然而,在真實情況下,裸晶通常包括一部分的壞區塊。例如,裸晶
#0的平面#2的區塊#150~#199都是壞區塊,如符號「X」所示。於是,在真實情況下,記憶體控制器110將裸晶#0與#1中的平面#0~#3之相同區塊編號的區塊組合成超級區塊,如第2圖下半部中的超級區塊索引(Super Block Index){0,1,...,149}所示,其中,第2圖左下角所示區塊索引{0-0,0-1,...,0-149}、{1-0,1-1,...,1-149}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-149}可代表裸晶#0的區塊索引{0-0,0-1,...,0-149}、{1-0,1-1,...,1-149}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-149},而第2圖右下角所示區塊索引{4-0,4-1,...,4-149}、{5-0,5-1,...,5-149}、{6-0,6-1,...,6-149}與{7-0,7-1,...,7-149}可代表裸晶#1的區塊索引{0-0,0-1,...,0-149}、{1-0,1-1,...,1-149}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-149}。在真實情況下,記憶體控制器110僅能組合成150個超級區塊,資料儲存裝置100僅能提供96GB(例如(128*(150/200))=96)的儲存容量,至於未組合至超級區塊的剩餘區塊,例如:裸晶#0的平面#0、#1以及#3的區塊#150~#199,裸晶#1的平面#0~#3的區塊#150~#199,則作為預留空間(Over-provisioning),無法成為資料儲存裝置100的儲存容量。
However, in a real situation, the die usually includes a portion of bad blocks. For example, bare die
Blocks #150~#199 of plane #2 of #0 are all bad blocks, as indicated by the symbol "X". Therefore, in a real situation, the memory controller 110 combines the blocks with the same block numbers of the planes #0~#3 in the die #0 and #1 into a super block, as shown in the lower half of FIG. 2 The Super Block Index (Super Block Index) {0,1,...,149} shown in Figure 2, where the block index {0-0,0-1,...,0 shown in the lower left corner of Figure 2 -149}, {1-0,1-1,...,1-149}, {2-0,2-1,...,2-149} and {3-0,3-1,. ...,3-149} can represent the block index {0-0,0-1,...,0-149}, {1-0,1-1,...,1- 149}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3-149}, and the block index shown in the lower right corner of Figure 2 {4-0,4-1,...,4-149}, {5-0,5-1,...,5-149}, {6-0,6-1,...,6 -149} and {7-0,7-1,...,7-149} can represent the block index {0-0,0-1,...,0-149}, { 1-0,1-1,...,1-149}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3- 149}. In a real situation, the
為了克服上述問題,本發明提供一種非對稱型平面管理(Unbalanced Plane Management)方法,其可在資料儲存裝置100進行儲存容量檢測而無法達到容量閾值,例如:100GB,的情況下,開發出不同的儲存容量,使資料儲存裝置100的儲存容量可以超過容量閾值,達到本發明的目的。而本發明非對稱型平面管理方法不局限於將每一平面之一個區塊整合至一個超級區塊中,尤其,可依據真實情況下的需求來彈性地調整超級區塊的組合,或是調整平面的個數以組成超級區塊。舉例來說,當使用本發明非對稱型平面管理方法來管理裸晶#0與#1時,超級區塊可由八個平面中的七個平面的區塊的組合來形成,如第3圖所示,其中,區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-199}可代表裸晶#0的區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,
1-199}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-199},而區塊索引{4-0,4-1,...,4-199}、{5-0,5-1,...,5-199}、{6-0,6-1,...,6-199}與{7-0,7-1,...,7-199}可代表裸晶#1的區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-199}與{3-0,3-1,...,3-199}。於是,可以產生較多的超級區塊,例如:由原本的150個超級區塊增加為200個超級區塊,且,可以增加資料儲存裝置100的儲存容量,例如:資料儲存裝置100的儲存容量從96GB增加為112GB(例如(128*(7/8))=112),以成功地達成本發明的目的。
In order to overcome the above-mentioned problems, the present invention provides an asymmetric plane management (Unbalanced Plane Management) method, which can develop different planar management methods when the storage capacity of the
在另一個真實情況下,如第4圖所示,裸晶#0的平面#2的區塊#150~#199都是壞區塊,裸晶#1的平面#2的區塊#180~#199都是壞區塊,因此,資料儲存裝置100僅能提供96GB的儲存容量。當採用本發明一種非對稱型平面管理方法時,將超級區塊由八個平面中的七個平面的區塊來組合,如第5圖所示,其中,區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-199}可代表裸晶#0的區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-199},而區塊索引{4-0,4-1,...,4-199}、{5-0,5-1,...,5-199}、{6-0,6-1,...,6-179}與{7-0,7-1,...,7-199}可代表裸晶#1的區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-179}與{3-0,3-1,...,3-199}。屬於超級區塊#0~#179的一大部分區塊可由裸晶#0的平面#0、#1與#3以及裸晶#1的平面#0~#3之各自的區塊#0~#179所組成,而屬於超級區塊#180~#199的另一部分區塊可改由裸晶#0與#1之各自的平面#0、#1與#3之各自的區塊#180~#199以及裸晶#0的平面#2的區塊#0~#19(如虛線框所示)所組成,一樣可以組成200個超級區塊,使資料儲存裝置100的儲存容量從96GB增加為112GB,以成功地達成本發明的目的。
In another real situation, as shown in Figure 4, blocks #150~#199 of plane #2 of
第6圖繪示依據本發明一實施例之非對稱型平面管理方法的工作流程,本發明非對稱型平面管理方法可應用於資料儲存裝置100,並由資料儲存裝
置100的記憶體控制器110所執行。另外,於執行本發明非對稱型平面管理方法以後,記憶體控制器110可能會產生多種儲存容量的記錄,其可分別對應於一平面數參數(plane count parameter)諸如一非平衡平面數量(unbalanced plane number)UNBAL_NUM的多個可能的值(例如多個候選值),並且使用者可以依據其需求從上述多種儲存容量的記錄選擇對應於該多個可能的值中的某一可能的值(例如該多個候選值中的某一候選值)之一記錄,例如:選取儲存容量值為最大的記錄,或是選取儲存容量值為次佳但是非平衡平面數量UNBAL_NUM的值較小的記錄,而選取該所選擇的記錄所對應的非平衡平面數量UNBAL_NUM的值,使資料儲存裝置100能透過對應的儲存容量組態提供所需的儲存容量。
Figure 6 shows the workflow of the asymmetric plane management method according to an embodiment of the present invention. The asymmetric plane management method of the present invention can be applied to the
於步驟S10中,記憶體控制器110設定非平衡平面數量UNBAL_NUM,其中,非平衡平面數量UNBAL_NUM小於一最大平面數量。該最大平面數量代表該複數個非揮發性記憶體元件122-1、122-2、...與122-N之各自的平面的數量的總和,尤其,該最大平面數量可等於裸晶數量(Die Count)DIE_COUNT乘以平面數量(Plane Number)PLANE_NUM,以前面所述實施例為例,資料儲存裝置100設置有裸晶#0與#1,則裸晶數量DIE_COUNT等於2。平面數量PLANE_NUM可代表每一裸晶所包含的平面的總數量,裸晶#0與#1分別具有其各自的平面#0~#3,則平面數量PLANE_NUM等於4,因此該最大平面數量等於8。非平衡平面數量UNBAL_NUM的初始值例如等於7,最小值例如等於2。
In step S10 , the
於步驟S12中,記憶體控制器110選取該最大平面數量減去非平衡平面數量UNBAL_NUM的至少一平面,並將選取的平面(諸如該至少一平面)的至少一組區塊(例如其區塊索引)記錄至一區塊省略表(block skip table)諸如對應於該至少一平面之至少一組區塊省略索引(block skip indexes)BLOCKSKIPIDX,其中該區塊省略表可包含該至少一組區塊省略索引
BLOCKSKIPIDX。該至少一組區塊省略索引BLOCKSKIPIDX較佳為一陣列,其可包含一或多個子陣列,而該陣列的該一或多個子陣列的一子陣列數(sub-array count)較佳等於該最大平面數量減去非平衡平面數量UNBAL_NUM的差值,並且該陣列的大小較佳等於該至少一組區塊的總數量。以第2圖上半部以及第4圖為例,最大平面數量等於8,非平衡平面數量UNBAL_NUM等於7,因此,記憶體控制器110將選取1個平面。由於裸晶#0的平面#2的好區塊的總數量最少,因此,記憶體控制器110選取裸晶#0的平面#2,並將裸晶#0的平面#2的區塊#0~#149(例如其區塊索引)記錄至區塊省略索引BLOCKSKIPIDX。假設非平衡平面數量UNBAL_NUM可予以變化,例如,當非平衡平面數量UNBAL_NUM等於6時,因為裸晶#0的平面#2以及裸晶#1的平面#2的好區塊的總數量最少,記憶體控制器110選取裸晶#0的平面#2以及裸晶#1的平面#2,並將裸晶#0的平面#2的區塊#0~#149以及裸晶#1的平面#2的區塊#0~#179(例如其區塊索引)記錄至區塊省略索引BLOCKSKIPIDX。另外,於某些實施例中,記憶體控制器110可選取好區塊的總數量最多的一或多個平面,並將該一或多個平面的區塊(例如其區塊索引)記錄至區塊省略索引BLOCKSKIPIDX,但本發明並不以此為限。
In step S12, the
於步驟S14中,記憶體控制器110依據區塊編號為索引(例如:BLK#=0、BLK#=1...),將未選取的平面的區塊組成超級區塊,尤其,逐一地(one by one)及/或依序地(sequentially),以將這些平面之各自的區塊#0、#1等分別組成超級區塊#0、#1等,其中這些超級區塊分別對應於這些區塊編號。以第2圖上半部以及第4圖為例,未選取的平面可為裸晶#0的平面#0、#1、#3以及裸晶#1的平面#0~#3,記憶體控制器110依據區塊編號為索引,將未選取的平面的區塊(例如其區塊索引)記錄至孤兒區塊表ORPHAN_BLOCK_TABLE,如第3以及5圖所示,其中,孤兒區塊表ORPHAN_BLOCK_TABLE記錄每一超級區塊的區塊編號,例如,超級區塊#0由7個不同平面的區塊#0所組成,超級區塊#1由7個不同
平面的區塊#1所組成,依此類推。此種架構的超級區塊又可稱為7平面超級區塊,或非平衡平面超級區塊。
In step S14, the
於步驟S16中,記憶體控制器110判斷步驟S14中的這些區塊編號是否小於一區塊閾值,以產生一判斷結果,尤其,透過將這些區塊編號所形成的一區塊編號序列中的最後一個區塊編號和該區塊閾值比較,以產生這個判斷結果,其中該最後一個區塊編號是這些區塊編號中的最大值。如果是(例如判斷結果為「真」(True)),則執行步驟S18;如果否(例如判斷結果為「偽」(False)),則執行步驟S20。該區塊閾值等於一預定值,且較佳等於全部可用的(available)區塊編號{BLK#}的最大值。以第2圖上半部以及第4圖為例,區塊閾值等於上述全部可用的區塊編號{BLK#}的最大值,即數值199。以第3圖為例,孤兒區塊表ORPHAN_BLOCK_TABLE可因應區塊編號BLK#的變化順利地從超級區塊#0建立至超級區塊#199,因此,當步驟S16的判斷為否時,這表示針對非平衡平面數量UNBAL_NUM的目前值之檢測已完成,可執行步驟S20,尤其,可另因應步驟S22的某一判斷結果執行步驟S10,以進行針對非平衡平面數量UNBAL_NUM的下一個值之檢測,例如,記憶體控制器110可在步驟S10中將非平衡平面數量UNBAL_NUM的下一個值(尤其,最新值)設定為非平衡平面數量UNBAL_NUM的目前值減1。
In step S16, the
於步驟S18中,記憶體控制器110繼續依據區塊編號為索引,尤其,依據上述全部可用的區塊編號{BLK#}中的剩餘的區塊編號(例如步驟S14中的上述區塊編號之後續區塊編號)為索引,將上述未選取的平面的其它區塊(例如對應於上述後續區塊編號之後續區塊)以及區塊省略索引BLOCKSKIPIDX所記錄的區塊組成其它超級區塊,諸如步驟S14中的上述超級區塊之後續超級區塊。以第4至5圖為例,孤兒區塊表ORPHAN_BLOCK_TABLE的表內容(例如其內的區塊索引所代表的超級區塊)可順利地建立至超級區塊#179,然而,在建
立超級區塊#180時,只剩下6個不同平面的區塊#180,因此,記憶體控制器110選取區塊省略索引BLOCKSKIPIDX所記錄的裸晶#0的平面#2的區塊#0以及6個不同平面的區塊#180來建立超級區塊#180。接著,記憶體控制器110選取區塊省略索引BLOCKSKIPIDX所記錄的裸晶#0的平面#2的區塊#1以及6個不同平面的區塊#181來建立超級區塊#181,依此類推,直到完成超級區塊#199的建立,如第5圖所示。
In step S18, the
於步驟S20中,記憶體控制器110記錄全部超級區塊的總容量以及非平衡平面數量UNBAL_NUM,以產生上述多種儲存容量的記錄中的一最新的記錄,以供進一步設定資料儲存裝置100的儲存容量組態,其中上述全部超級區塊可包含步驟S14中的上述超級區塊,尤其,可另包含步驟S18中的上述其它超級區塊(若步驟S18被執行)。於完成孤兒區塊表ORPHAN_BLOCK_TABLE的建立以後,記憶體控制器110可依據孤兒區塊表ORPHAN_BLOCK_TABLE而計算出超級區塊的總容量,例如:112GB,且記錄超級區塊的總容量以及非平衡平面數量UNBAL_NUM的目前值,例如:數值7。
In step S20, the
於步驟S22中,記憶體控制器110判斷非平衡平面數量UNBAL_NUM是否等於平面閾值。如果否(例如判斷結果為「偽」),則執行步驟S10;如果是(例如判斷結果為「真」),則結束非對稱型平面管理方法的執行。在步驟S10,記憶體控制器110例如將非平衡平面數量UNBAL_NUM的下一個值(尤其,最新值)設定為非平衡平面數量UNBAL_NUM的目前值減1。另外,平面閾值可等於UNBAL_NUM的最小值,例如:數值2。
In step S22 , the
由於上述中可知,本發明至少一實施例之非對稱型平面管理方法能成功地將資料儲存裝置100的儲存容量從96GB增加為112GB,並使資料儲存裝置100具備基於超級區塊的高存取效能,而剩下未利用的區塊,例如:區塊省略索引BLOCKSKIPIDX所記錄的區塊則可作為預留空間(Over-provisioning)使用,
達到本發明的目的。
As can be seen from the above, the asymmetric plane management method of at least one embodiment of the present invention can successfully increase the storage capacity of the
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
S10,S12,S14,S16,S18,S20,S22:步驟 S10, S12, S14, S16, S18, S20, S22: steps
Claims (18)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962813169P | 2019-03-04 | 2019-03-04 | |
US62/813,169 | 2019-03-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202213103A TW202213103A (en) | 2022-04-01 |
TWI781846B true TWI781846B (en) | 2022-10-21 |
Family
ID=73643533
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110100036A TWI752784B (en) | 2019-03-04 | 2019-08-22 | Unbalanced plane management method, associated data storage device and controller thereof |
TW110145772A TWI781846B (en) | 2019-03-04 | 2019-08-22 | Unbalanced plane management method, associated data storage device and controller thereof |
TW108129939A TWI718635B (en) | 2019-03-04 | 2019-08-22 | Unbalanced plane management method, associated data storage device and controller thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110100036A TWI752784B (en) | 2019-03-04 | 2019-08-22 | Unbalanced plane management method, associated data storage device and controller thereof |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108129939A TWI718635B (en) | 2019-03-04 | 2019-08-22 | Unbalanced plane management method, associated data storage device and controller thereof |
Country Status (1)
Country | Link |
---|---|
TW (3) | TWI752784B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022147448A (en) | 2021-03-23 | 2022-10-06 | キオクシア株式会社 | Memory system and data management method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201510722A (en) * | 2009-09-03 | 2015-03-16 | Pioneer Chip Technology Ltd | Page based management of flash storage |
US20180151251A1 (en) * | 2016-11-29 | 2018-05-31 | SK Hynix Inc. | Memory system and operating method thereof |
US20180196749A1 (en) * | 2017-01-12 | 2018-07-12 | SK Hynix Inc. | Memory system and operating method of the same |
TWI643065B (en) * | 2017-12-20 | 2018-12-01 | 慧榮科技股份有限公司 | Data storage device and operating method for dynamically executing garbage collection |
TWI652679B (en) * | 2017-12-08 | 2019-03-01 | 旺宏電子股份有限公司 | Memory controller, memory system and control method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008115720A1 (en) * | 2007-03-21 | 2008-09-25 | Sandisk Corporation | Methods for storing memory operations in a queue |
KR20120084906A (en) * | 2011-01-21 | 2012-07-31 | 에스케이하이닉스 주식회사 | Non-volatile memory system and management method therefor |
US9431113B2 (en) * | 2013-08-07 | 2016-08-30 | Sandisk Technologies Llc | Data storage system with dynamic erase block grouping mechanism and method of operation thereof |
US9263136B1 (en) * | 2013-09-04 | 2016-02-16 | Western Digital Technologies, Inc. | Data retention flags in solid-state drives |
KR102420025B1 (en) * | 2017-06-19 | 2022-07-13 | 에스케이하이닉스 주식회사 | Memory system and operation method for the same |
TWI650763B (en) * | 2018-05-14 | 2019-02-11 | 慧榮科技股份有限公司 | Method, memory device and electronic device and page availability management system for performing page availability management of memory device |
-
2019
- 2019-08-22 TW TW110100036A patent/TWI752784B/en active
- 2019-08-22 TW TW110145772A patent/TWI781846B/en active
- 2019-08-22 TW TW108129939A patent/TWI718635B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201510722A (en) * | 2009-09-03 | 2015-03-16 | Pioneer Chip Technology Ltd | Page based management of flash storage |
US20180151251A1 (en) * | 2016-11-29 | 2018-05-31 | SK Hynix Inc. | Memory system and operating method thereof |
US20180196749A1 (en) * | 2017-01-12 | 2018-07-12 | SK Hynix Inc. | Memory system and operating method of the same |
TWI652679B (en) * | 2017-12-08 | 2019-03-01 | 旺宏電子股份有限公司 | Memory controller, memory system and control method |
TWI643065B (en) * | 2017-12-20 | 2018-12-01 | 慧榮科技股份有限公司 | Data storage device and operating method for dynamically executing garbage collection |
Also Published As
Publication number | Publication date |
---|---|
TW202125264A (en) | 2021-07-01 |
TW202213103A (en) | 2022-04-01 |
TWI718635B (en) | 2021-02-11 |
TW202034172A (en) | 2020-09-16 |
TWI752784B (en) | 2022-01-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI506430B (en) | Method of recording mapping information method, and memory controller and memory storage apparatus using the same | |
US9880742B2 (en) | Valid data merging method, memory controller and memory storage apparatus | |
US8812784B2 (en) | Command executing method, memory controller and memory storage apparatus | |
US9280460B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
US9342371B2 (en) | Boot partitions in memory devices and systems | |
US9268687B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
CN111651371B (en) | Asymmetric plane management method, data storage device and controller thereof | |
US8510502B2 (en) | Data writing method, and memory controller and memory storage apparatus using the same | |
US8296504B2 (en) | Data management method and flash memory storage system and controller using the same | |
US10283196B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
US9965194B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus which performs data arrangement operation according to usage frequency of physical erasing unit of memory storage apparatus | |
TWI698749B (en) | A data storage device and a data processing method | |
US10552254B2 (en) | Partially written superblock treatment | |
US10503433B2 (en) | Memory management method, memory control circuit unit and memory storage device | |
CN111796759B (en) | Computer readable storage medium and method for fragment data reading on multiple planes | |
US9001585B1 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
TWI781846B (en) | Unbalanced plane management method, associated data storage device and controller thereof | |
US9830077B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
TWI453747B (en) | Method for managing a plurality of blocks of a flash memory, and associated memory device and controller thereof | |
US12061792B1 (en) | Method of handling host write commands requesting to write dummy pattern on flash memory and related memory controller and storage system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent |