TWI718635B - Unbalanced plane management method, associated data storage device and controller thereof - Google Patents

Abstract

An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count obtained from subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into super blocks, wherein said super blocks respectively correspond to said block numbers; and recording total capacity of all super blocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all super blocks include said super blocks.

Description

Asymmetric plane management method, data storage device and controller thereof

The present invention relates to flash memory (Flash memory) access, in particular to an asymmetric plane management (Unbalanced Plane Management) method, data storage device and its controller.

Flash memory can be widely used in various portable or non-portable data storage devices (for example: memory cards that comply with SD/MMC, CF, MS, XD or UFS standards; another example: solid state drives; another example ：In an embedded storage device that meets UFS or EMMC specifications. For the commonly used NAND flash memory, there are initially single level cell (SLC), multiple level cell (MLC) and other types of flash memory. Due to the continuous development of memory technology, newer data storage device products can use triple level cell (TLC) flash memory or even quadruple level cell (QLC) flash memory. In order to ensure that the data storage device's access control to the flash memory can comply with relevant specifications, the flash memory controller is usually equipped with some management mechanism to properly manage its internal operations.

According to related technologies, data storage devices with these management mechanisms still have shortcomings. For example, multiple flash memory dies (Die) can be used at the same time to improve access performance. However, the number of good blocks of a certain flash memory die may limit the utilization rate of the respective blocks of the flash memory die. For example, when the number of these good blocks is small, or the distribution of these good blocks is unbalanced, the required storage capacity cannot be obtained. Therefore, a novel method and related architecture are needed to achieve reliable management without side effects or less likely to bring side effects. The data storage device of the mechanism.

One objective of the present invention is to provide an asymmetric plane management method and related data storage device and its controller to solve the above-mentioned problems.

Another object of the present invention is to provide an asymmetric plane management method and related data storage device and its controller, so as to provide a reliable management mechanism to the data storage device without side effects or less likely to cause side effects.

At least one embodiment of the present invention provides an asymmetric plane management method, wherein the asymmetric plane management method is applied to a data storage device including a non-volatile memory (NV memory) ), the non-volatile memory includes a plurality of non-volatile memory elements (NV memory elements), and the plurality of non-volatile memory elements includes a plurality of blocks. The asymmetric plane management method may include: setting an unbalanced plane number (unbalanced plane number), wherein the unbalanced plane number is less than a maximum plane number, and the maximum plane number represents each of the plurality of non-volatile memory devices The sum of the number of planes; select at least one plane from the maximum number of planes minus the number of unbalanced planes, and record at least one group of blocks of the at least one plane in a block skip table; according to the block The number is an index, and the blocks of the unselected planes are formed into super blocks, where the super blocks respectively correspond to the block numbers; and the total capacity of all super blocks and the number of unbalanced planes are recorded to generate a variety of A newest record in the storage capacity records for further setting the storage capacity configuration of the data storage device, wherein the all super blocks include the super blocks.

At least one embodiment of the present invention provides a data storage device, which may include: a non-volatile memory for storing information, wherein the non-volatile memory includes a plurality of non-volatile memory elements, and the plurality of non-volatile memory devices. The volatile memory device includes a plurality of blocks; and a controller, It is coupled to the non-volatile memory for controlling the operation of the data storage device. The controller may include a processing circuit, wherein the processing circuit can control the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller body. For example: the controller sets a number of unbalanced planes, where the number of unbalanced planes is less than a maximum number of planes, and the maximum number of planes represents the sum of the numbers of the respective planes of the plurality of non-volatile memory devices; the controller Select at least one plane from the maximum number of planes minus the number of unbalanced planes, and record at least one group of blocks of the at least one plane in a block omission table; the controller uses the block number as an index, and then the unselected The flat blocks constitute a super block, wherein the super blocks respectively correspond to the block numbers; and the controller records the total capacity of all super blocks and the number of unbalanced planes to generate a record of multiple storage capacities A latest record of the data storage device for further setting the storage capacity configuration of the data storage device, wherein the all super blocks include the super blocks.

At least one embodiment of the present invention provides a controller for a data storage device, wherein the data storage device includes the controller and a non-volatile memory, the non-volatile memory includes a plurality of non-volatile memory elements, and the The plurality of non-volatile memory devices include a plurality of blocks. The controller may include a processing circuit, wherein the processing circuit can control the controller according to a plurality of host commands from a host, so as to allow the host to access the non-volatile memory through the controller. For example: the controller sets a number of unbalanced planes, where the number of unbalanced planes is less than a maximum number of planes, and the maximum number of planes represents the sum of the numbers of the respective planes of the plurality of non-volatile memory devices; the controller Select at least one plane from the maximum number of planes minus the number of unbalanced planes, and record at least one group of blocks of the at least one plane in a block omission table; the controller uses the block number as an index, and then the unselected The flat blocks constitute a super block, wherein the super blocks respectively correspond to the block numbers; and the controller records the total capacity of all super blocks and the number of unbalanced planes to generate a record of multiple storage capacities The latest record of the data storage for further setting of the data storage The storage capacity configuration of the storage device, wherein all the super blocks include the super blocks.

One of the benefits of the present invention is that through a carefully designed management mechanism, the present invention can properly control the operation of the controller, especially, the data storage device can use the unbalanced plane method, for example, used in the super block (Super Block) can change the number of planes instead of using the entire number of planes. Therefore, the present invention can break the limitation on the number of good blocks of NAND flash memory to integrate the largest capacity; or, under specific capacity requirements, effectively integrate sufficient super blocks to achieve Optimize performance. In addition, the implementation according to the embodiments of the present invention does not increase a lot of additional costs. Therefore, the related technical problems can be solved, and the overall cost will not increase too much. Compared with the traditional architecture, the present invention can achieve the optimal performance of the data storage device without side effects or less likely to cause side effects.

50: host

100: Data storage device

110: Memory Controller

112: Microprocessor

112C: Code

112M: Read only memory

114: Control logic circuit

116: buffer memory

118: Transmission interface circuit

120: Non-volatile memory

122, 122-1, 122-2,..., 122-N: Non-volatile memory components

{0-0,0-1,...}, {1-0,1-1,...}, {2-0,2-1,...}, {3-0,3-1 ,...}, {4-0,4-1,...}, {5-0,5-1,...}, {6-0,6-1,...}, {7 -0,7-1,...): block index

S10, S12, S14, S16, S18, S20, S22: steps

ORPHAN_BLOCK_TABLE: Orphan block table

BLOCKSKIPIDX: Block omitted index

FIG. 1 is a schematic diagram of a data storage device and a host device according to an embodiment of the invention.

Figure 2 shows a schematic diagram of a management solution for super blocks.

Figure 3 illustrates a super block management scheme according to an embodiment of the invention.

Figure 4 shows an example of bad block distribution.

Figure 5 shows a super block management scheme according to another embodiment of the present invention.

FIG. 6 shows a workflow of an asymmetric plane management method according to an embodiment of the present invention.

Please refer to FIG. 1, which is a schematic diagram of a data storage device 100 and a host device 50 according to a first embodiment of the present invention. For example: the data storage device 100 may be solid state Hard Disk (Solid State Drive, SSD). In addition, examples of the host 50 may include (but are not limited to): a multifunctional mobile phone, a tablet, and a personal computer such as a desktop computer and a laptop computer. According to this embodiment, the data storage device 100 may include a controller such as a memory controller 110, and may further include a non-volatile (Non-Volatile) memory 120, wherein the controller is used to access the non-volatile memory 120. The volatile memory 120 and the non-volatile memory 120 are used to store information.

The non-volatile memory 120 may include a plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N, where the symbol "N" may represent a positive integer greater than one. For example: the non-volatile memory 120 can be a flash memory, and the non-volatile memory devices 122-1, 122-2, ... and 122-N can be a plurality of flash memories, respectively A chip or a plurality of flash memory die, but the invention is not limited to this. In addition, the data storage device 100 may further include a volatile memory device to cache data. The volatile memory device is preferably a dynamic random access memory (DRAM). The above-mentioned volatile memory device can provide appropriate data temporary storage space to cache data, or only provide a small amount of data temporary storage space to cache a small amount of data. This architecture is also called partial DRAM (Partial DRAM). In addition, volatile memory components are unnecessary components.

The memory controller 110 may include a processing circuit such as a microprocessor 112, a memory such as a read only memory (Read Only Memory, ROM) 112M, a control logic circuit 114, a buffer memory 116, and a transmission interface circuit 118, among which these components Can be coupled to each other through the bus. The buffer memory 116 is preferably a static random access memory (SRAM). For example, if the data storage device 100 is further configured with the above-mentioned DRAM, the memory controller 110 can use the buffer memory 116 such as SRAM as the first level cache and use DRAM as the second level cache. The data storage capacity of the DRAM is preferably greater than the data storage capacity of the buffer memory 116, and the data buffered by the buffer memory 116 can be derived from the DRAM or the non-volatile memory 120.

The read-only memory 112M of this embodiment is used to store the program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the non-volatile memory 120. Please note that the program code 112C must also be stored in the buffer memory 116 or any form of memory. In addition, the control logic circuit 114 may include at least one Error Correction Code (ECC) circuit (not shown) to protect data and/or perform error correction, and the transmission interface circuit 118 may comply with a specific communication standard (such as serial It is listed as Serial Advanced Technology Attachment (SATA) standard, Peripheral Component Interconnect Express (PCIE) standard or Non-Volatile Memory Express (Non-Volatile Memory Express, NVME) standard and can be based on specific communication standards. Communicate with the host 50.

In this embodiment, the host 50 can send a plurality of host commands (Host Command) to the data storage device 100, and the memory controller 110 then accesses the non-volatile memory 120 (such as reading or writing) according to the host command. Input data), wherein the above-mentioned data is preferably user data derived from the host 50. The host command includes a logical address, such as a logical block address (Logical Block Address, LBA). The memory controller 110 can receive host commands and translate the host commands into memory operation commands (operation commands for short), and then use the operation commands to control the non-volatile memory 120 to read, write (Write)/program (Program) A page of a specific physical address in the non-volatile memory 120 (Page).

The memory controller 110 records the mapping relationship between the logical address and the physical address of the data in a logical-to-physical address (L2P) mapping table, where the physical address can be defined by the channel (Channel) Number, Logical Unit Number (LUN), Plane Number, Block Number, Page Number, and Offset. In some embodiments, the implementation of the physical address can be changed. For example, the physical address may include channel number, logical unit number, plane number, block number, page number, and/or offset.

The L2P mapping table can be stored in a system block in the non-volatile memory 120, and can be divided into a plurality of group mapping tables, and each group mapping table records a mapping relationship of a logical address. The system block is preferably an encrypted block and data programming is performed in the SLC mode. The memory controller 110 can be The capacity of the buffer memory 116 is to load part or all of the group mapping tables from the non-volatile memory 120 into the buffer memory 116 for quick reference, but the present invention is not limited to this . When the user data is updated, the memory controller 110 can update the content of the group mapping table according to the latest mapping relationship of the user data. The size of the group mapping table is preferably no greater than the size of a page (Page) of the non-volatile memory device 122-n, such as 16KB (kilobytes; kilobytes), where the symbol "n" can represent the interval [1, N] is any positive integer, but the present invention is not limited to this. For example, the size of the group mapping table can be 4KB or 1KB.

The non-volatile memory device 122-n may include multiple planes, such as planes #0, #1, #2, and #3. Each plane includes multiple blocks, and each block includes multiple pages. In this case, the memory controller 110 may combine each block of the planes #0 to #3 into a large block, and the size of the large block is equal to 4 times the size of a block.

The memory controller 110 can combine multiple channels, for example, two channels CH#0 and CH#1, each of a large block of each non-volatile memory element 122-n can be combined into a super block (Super Block, SB), the size of the super block is equal to 8 times the size of a block, and the two non-volatile memory elements 122-n can be controlled by the same chip enable (CE) signal, However, the present invention is not limited to this. For example, under the setting that the number of channels is equal to 4, such as channels CH#0~CH#3, channels CH#0~CH#3, each of a non-volatile memory device can also be composed of a large block. A super block can also be controlled by a chip enable signal.

Figure 2 shows a schematic diagram of a management solution for super blocks. The non-volatile memory elements 122-1, 122-2, ... and 122-N can be implemented as a plurality of flash memory die, such as die #0 and #1, among which die #0 and #1 It can be used as a non-volatile memory device 122-n in each of the two channels CH#0 and CH#1, and the structure of the super block is described as an example. Die #0 can have 4 planes. Therefore, the block in die #0 can be represented by 4 sets of block indexes, for example, its block index {0-0,0-1,... ,0-199}, {1-0,1-1,...,1-199}, {2-0,2-1,...,2-199} and {3-0,3-1 ,...,3-199}. Similarly, die #1 can also have 4 planes. Therefore, the block in die #1 can also be represented by 4 sets of block indexes, for example, its block index {0-0,0-1,... .,0-199}, {1-0,1-1,...,1-199}, {2-0,2-1,...,2-199} and {3-0,3- 1,...,3-199}.

When forming a super block, die #0~#1 can be placed in channels CH#0 and CH#1, respectively. In this way, the blocks in the super block can be represented by a block index, for example, with a block index 8 groups of block indexes in the format [Die#,PLN#,BLK#] {[0,0,0],[0,0,1],...,[0,0,199]}, {[0,1 ,0],[0,1,1],...,[0,1,199]}, {[0,2,0],[0,2,1],...,[0,2,149]} , {[0,3,0],[0,3,1],...,[0,3,199]}, {[1,4,0],[1,4,1],..., [1,4,199]}, {[1,5,0],[1,5,1],...,[1,5,199]}, {[1,6,0],[1,6,1 ],...,[1,6,199]} and {[1,7,0],[1,7,1],...,[1,7,199]}, and in the block index format [Die# ,PLN#,BLK#], Die#, PLN#, and BLK# represent the die number, plane number, and block number, respectively. Among them, the die number and the plane number are preferably progressive values (such as those with fixed increments). A series of values), sometimes the die number will be replaced by the channel number. In addition, in the above architecture, since the blocks in the super block come from eight planes, such a super block can also be called an eight-plane super block or a balanced plane architecture.

Assuming that under ideal conditions, the respective planes #0~#3 of die #0 and #1 can have the same number of good blocks (Good Block), for example, 200 good blocks, that is, blocks #0~#199 All are good blocks, none of them are bad blocks. Therefore, in an ideal situation, the memory controller 110 can combine the blocks with the same block numbers of the planes #0~#3 in the die #0 and #1 into a super block. Therefore, it can be combined into 200 blocks. Super block. Since all the blocks are good blocks, the memory controller 110 can combine the maximum number of super blocks in this case. Therefore, the data storage device 100 (such as an SSD) can provide an ideal storage capacity. Assuming that the storage capacity of each die is 64 GB (Gigabytes; one billion bytes), the data storage device 100 can provide a storage capacity of 128 GB. Since the blocks in the die are combined into super blocks, the data storage device 100 can provide ideal (better) access performance.

However, in real situations, the die usually includes a part of bad blocks. For example, bare die #0的平面#2's blocks #150~#199 are all bad blocks, as shown by the symbol "X". Therefore, in a real situation, the memory controller 110 combines the blocks with the same block numbers of the planes #0~#3 in die #0 and #1 into a super block, as shown in the lower half of Figure 2 The Super Block Index (Super Block Index) {0,1,...,149} shown in Figure 2, where the block index {0-0,0-1,...,0 shown in the lower left corner of Figure 2 -149}, {1-0,1-1,...,1-149}, {2-0,2-1,...,2-149} and {3-0,3-1,. ..,3-149} can represent the block index of die #0 {0-0,0-1,...,0-149}, {1-0,1-1,...,1- 149}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3-149}, and the block index shown in the lower right corner of Figure 2 {4-0,4-1,...,4-149}, {5-0,5-1,...,5-149}, {6-0,6-1,...,6 -149} and {7-0,7-1,...,7-149} can represent the block index {0-0,0-1,...,0-149}, { 1-0,1-1,...,1-149}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3- 149}. In a real situation, the memory controller 110 can only be combined into 150 super blocks, and the data storage device 100 can only provide a storage capacity of 96GB (for example, (128 * (150/200)) = 96). The remaining blocks of the super block, for example: the plane #0, #1 and #3 of the die #0 block #150~#199, and the plane #0~#3 of the die #1 block #150~ #199 is used as over-provisioning and cannot be the storage capacity of the data storage device 100.

In order to overcome the above-mentioned problems, the present invention provides an asymmetric plane management (Unbalanced Plane Management) method, which can detect the storage capacity of the data storage device 100 but cannot reach the capacity threshold, for example, 100GB. The storage capacity enables the storage capacity of the data storage device 100 to exceed the capacity threshold, achieving the purpose of the present invention. The asymmetric plane management method of the present invention is not limited to integrating one block of each plane into one super block. In particular, the combination of super blocks can be flexibly adjusted or adjusted according to actual needs. The number of planes constitutes a super block. For example, when the asymmetric plane management method of the present invention is used to manage dies #0 and #1, the super block can be formed by a combination of blocks of seven planes out of eight planes, as shown in Figure 3. Shows, where the block index {0-0,0-1,...,0-199}, {1-0,1-1,...,1-199}, {2-0,2- 1,...,2-149} and {3-0,3-1,...,3-199} can represent the block index {0-0,0-1,... ,0-199}, {1-0,1-1,..., 1-199}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3-199}, and the block index {4-0, 4-1,...,4-199}, {5-0,5-1,...,5-199}, {6-0,6-1,...,6-199} and { 7-0,7-1,...,7-199} can represent the block index of die #1 {0-0,0-1,...,0-199}, {1-0,1 -1,...,1-199}, {2-0,2-1,...,2-199} and {3-0,3-1,...,3-199}. Therefore, more super blocks can be generated, for example, the original 150 super blocks are increased to 200 super blocks, and the storage capacity of the data storage device 100 can be increased, for example: the storage capacity of the data storage device 100 Increase from 96GB to 112GB (for example (128 *(7/8))=112) to successfully achieve the purpose of the invention.

In another real situation, as shown in Figure 4, blocks #150~#199 of plane #2 of die #0 are all bad blocks, and block #180~ of plane #2 of die #1. #199 are all bad blocks. Therefore, the data storage device 100 can only provide a storage capacity of 96GB. When the asymmetric plane management method of the present invention is adopted, the super block is combined by blocks of seven of the eight planes, as shown in Figure 5, where the block index is {0-0,0 -1,...,0-199}, {1-0,1-1,...,1-199}, {2-0,2-1,...,2-149} and {3 -0,3-1,...,3-199} can represent the block index of die #0 {0-0,0-1,...,0-199}, {1-0,1- 1,...,1-199}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3-199}, and the block Index {4-0,4-1,...,4-199}, {5-0,5-1,...,5-199}, {6-0,6-1,..., 6-179} and {7-0,7-1,...,7-199} can represent the block index {0-0,0-1,...,0-199} of die #1, {1-0,1-1,...,1-199}, {2-0,2-1,...,2-179} and {3-0,3-1,...,3 -199}. A large part of the blocks belonging to the super block #0~#179 can be divided by the plane #0, #1 and #3 of the die #0 and the plane #0~#3 of the die #1. #179, and the other part of the blocks belonging to the super block #180~#199 can be changed to the respective planes #0, #1 and #3 of the die #0 and #1 #180~ #199 and die #0 of the plane #2 are composed of blocks #0~#19 (as shown by the dashed frame), which can also form 200 super blocks, increasing the storage capacity of the data storage device 100 from 96GB to 112GB, in order to successfully achieve the purpose of the invention.

Figure 6 shows the workflow of the asymmetric plane management method according to an embodiment of the present invention. The asymmetric plane management method of the present invention can be applied to the data storage device 100, and the data storage device The memory controller 110 is set to 100 to execute. In addition, after implementing the asymmetric plane management method of the present invention, the memory controller 110 may generate records of multiple storage capacities, which can respectively correspond to a plane count parameter such as an unbalanced plane count. plane number) multiple possible values of UNBAL_NUM (such as multiple candidate values), and the user can select a certain possible value corresponding to the multiple possible values (such as multiple candidate values) from the above-mentioned multiple storage capacity records according to their needs One of the multiple candidate values) records, for example: select the record with the largest storage capacity value, or select the record with the second best storage capacity value but the number of unbalanced planes UNBAL_NUM is smaller, and The value of the number of unbalanced planes UNBAL_NUM corresponding to the selected record is selected, so that the data storage device 100 can provide the required storage capacity through the corresponding storage capacity configuration.

In step S10, the memory controller 110 sets the number of unbalanced planes UNBAL_NUM, where the number of unbalanced planes UNBAL_NUM is less than a maximum number of planes. The maximum number of planes represents the sum of the numbers of the respective planes of the plurality of non-volatile memory elements 122-1, 122-2, ... and 122-N. In particular, the maximum number of planes may be equal to the number of dies ( Die Count) DIE_COUNT is multiplied by the number of planes (Plane Number) PLANE_NUM. Taking the aforementioned embodiment as an example, the data storage device 100 is provided with dies #0 and #1, and the number of dies DIE_COUNT is equal to 2. The number of planes PLANE_NUM can represent the total number of planes included in each die. Die #0 and #1 have their own planes #0~#3 respectively, and the number of planes PLANE_NUM is equal to 4, so the maximum number of planes is equal to 8. . The initial value of the number of unbalanced planes UNBAL_NUM is equal to 7, for example, and the minimum value is equal to 2, for example.

In step S12, the memory controller 110 selects at least one plane from the maximum number of planes minus the number of unbalanced planes UNBAL_NUM, and sets at least one set of blocks (for example, the blocks of the selected plane, such as the at least one plane) Index) recorded in a block skip table (block skip table) such as at least one set of block skip indexes BLOCKSKIPIDX corresponding to the at least one plane, wherein the block skip table may include the at least one set of blocks Omit index BLOCKSKIPIDX. The at least one set of block omission index BLOCKSKIPIDX is preferably an array, which may include one or more sub-arrays, and a sub-array count of the one or more sub-arrays of the array is preferably equal to the maximum The difference between the number of planes minus the number of unbalanced planes UNBAL_NUM, and the size of the array is preferably equal to the total number of the at least one group of blocks. Taking the upper part of Fig. 2 and Fig. 4 as examples, the maximum number of planes is equal to 8, and the number of unbalanced planes UNBAL_NUM is equal to 7. Therefore, the memory controller 110 will select one plane. Since the total number of good blocks in plane #2 of die #0 is the least, the memory controller 110 selects plane #2 of die #0, and places die #0 in plane #2 of block #0. ~#149 (such as its block index) record to the block omission index BLOCKSKIPIDX. Assuming that the number of unbalanced planes UNBAL_NUM can be changed, for example, when the number of unbalanced planes UNBAL_NUM is equal to 6, because the total number of good blocks of die #0 plane #2 and die #1 plane #2 is the smallest, the memory The bulk controller 110 selects the plane #2 of the die #0 and the plane #2 of the die #1, and sets the blocks #0~#149 of the plane #2 of the die #0 and the plane #2 of the die #1. The block #0~#179 (for example, its block index) is recorded to the block omission index BLOCKSKIPIDX. In addition, in some embodiments, the memory controller 110 may select one or more planes with the largest total number of blocks, and record the blocks (for example, the block index) of the one or more planes in The block omits the index BLOCKSKIPIDX, but the present invention is not limited to this.

In step S14, the memory controller 110 uses the block number as an index (for example: BLK#=0, BLK#=1...), and forms the blocks of the unselected planes into super blocks, especially, one by one (one by one) and/or sequentially (sequentially) to form the respective blocks #0, #1, etc. of these planes into super blocks #0, #1, etc., where these super blocks correspond to These block numbers. Take the upper part of Figure 2 and Figure 4 as an example, the unselected planes can be planes #0, #1, #3 of die #0 and planes #0~#3 of die #1, memory control Based on the block number as the index, the device 110 records the blocks of the unselected plane (such as its block index) to the orphan block table ORPHAN_BLOCK_TABLE, as shown in Figures 3 and 5, wherein the orphan block table ORPHAN_BLOCK_TABLE records each The block number of a super block, for example, super block #0 is composed of 7 different planes of block #0, and super block #1 is composed of 7 different It is composed of flat block #1, and so on. The super block of this structure can also be called a 7-plane super block or an unbalanced plane super block.

In step S16, the memory controller 110 determines whether the block numbers in step S14 are less than a block threshold to generate a determination result, in particular, the block number sequence formed by these block numbers The last block number is compared with the block threshold to generate this judgment result, where the last block number is the maximum of these block numbers. If yes (for example, the judgment result is "True"), then step S18 is executed; if not (for example, the judgment result is "False" (False)), then step S20 is executed. The block threshold is equal to a predetermined value, and preferably equal to the maximum value of all available block numbers {BLK#}. Taking the upper part of Fig. 2 and Fig. 4 as examples, the block threshold is equal to the maximum value of all available block numbers {BLK#}, which is a value of 199. Taking Figure 3 as an example, the orphan block table ORPHAN_BLOCK_TABLE can be successfully established from super block #0 to super block #199 in response to the change of block number BLK#. Therefore, when the judgment of step S16 is negative, this means The detection of the current value of the number of unbalanced planes UNBAL_NUM has been completed, step S20 may be executed. In particular, step S10 may be executed according to a certain judgment result of step S22 to perform the detection of the next value of the number of unbalanced planes UNBAL_NUM. For example, the memory controller 110 may set the next value (especially the latest value) of the number of unbalanced planes UNBAL_NUM in step S10 to the current value of the number of unbalanced planes UNBAL_NUM minus one.

In step S18, the memory controller 110 continues to index according to the block number, in particular, according to the remaining block numbers in all the above-mentioned available block numbers {BLK#} (for example, the number of the above-mentioned block numbers in step S14) The subsequent block number) is an index, and other blocks of the above unselected plane (for example, the subsequent block corresponding to the above subsequent block number) and the block recorded by the block omission index BLOCKSKIPIDX form other super blocks, such as The super block subsequent to the above super block in step S14. Taking Figures 4 to 5 as an example, the table content of the orphan block table ORPHAN_BLOCK_TABLE (for example, the super block represented by the block index in it) can be successfully established to super block #179, however, it is under construction When super block #180 is established, only 6 blocks #180 with different planes are left. Therefore, the memory controller 110 selects blocks to omit block #0 of plane #2 of die #0 and plane #2 recorded by the index BLOCKSKIPIDX. And 6 blocks #180 of different planes to create a super block #180. Then, the memory controller 110 selects the block to omit the block #1 of the plane #2 of the die #0 recorded by the index BLOCKSKIPIDX and the block #181 of 6 different planes to create the super block #181, and so on , Until the establishment of super block #199 is completed, as shown in Figure 5.

In step S20, the memory controller 110 records the total capacity of all super blocks and the number of unbalanced planes UNBAL_NUM to generate the latest record among the above-mentioned multiple storage capacity records for further setting the storage of the data storage device 100 The capacity configuration, wherein all the super blocks mentioned above may include the super blocks mentioned in step S14, and in particular, may further comprise the other super blocks mentioned above in step S18 (if step S18 is executed). After completing the establishment of the orphan block table ORPHAN_BLOCK_TABLE, the memory controller 110 can calculate the total capacity of the super block according to the orphan block table ORPHAN_BLOCK_TABLE, for example: 112GB, and record the total capacity of the super block and the number of unbalanced planes The current value of UNBAL_NUM, for example: the value 7.

In step S22, the memory controller 110 determines whether the number of unbalanced planes UNBAL_NUM is equal to the plane threshold. If not (for example, the judgment result is "false"), step S10 is executed; if yes (for example, the judgment result is "true"), then the execution of the asymmetric plane management method is ended. In step S10, the memory controller 110, for example, sets the next value (especially the latest value) of the number of unbalanced planes UNBAL_NUM to the current value of the number of unbalanced planes UNBAL_NUM minus one. In addition, the plane threshold can be equal to the minimum value of UNBAL_NUM, for example, the value 2.

As can be seen from the above, the asymmetric plane management method of at least one embodiment of the present invention can successfully increase the storage capacity of the data storage device 100 from 96GB to 112GB, and enable the data storage device 100 to have high access based on super blocks. Performance, and the remaining unused blocks, for example: the blocks recorded by the block omission index BLOCKSKIPIDX can be used as over-provisioning, To achieve the purpose of the present invention.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

S10, S12, S14, S16, S18, S20, S22: steps

Claims (18)

An asymmetric plane management method, the asymmetric plane management method is applied to a data storage device, the data storage device includes a non-volatile memory (non-volatile memory, NV memory), the non-volatile memory includes a plurality of A non-volatile memory element (NV memory element), the plurality of non-volatile memory elements include a plurality of blocks (block), the asymmetric plane management method includes: setting an unbalanced plane number (unbalanced plane number) ), wherein the number of unbalanced planes is less than a maximum number of planes, and the maximum number of planes represents the sum of the number of the respective planes of the plurality of non-volatile memory elements; select the maximum number of planes minus at least the number of unbalanced planes A plane, and at least one set of blocks of the at least one plane are recorded in a block skip table (block skip table); according to the block number as an index, the blocks of the unselected plane are formed into a super block. The super blocks respectively correspond to the block numbers; and the total capacity of all super blocks and the number of unbalanced planes are recorded to generate a newest record among the records of multiple storage capacities for further setting of the data storage device The storage capacity configuration, wherein all the super blocks include the super blocks, and the records of the various storage capacities correspond to multiple possible values of the number of unbalanced planes, so as to allow a user to follow the demand from The record selection of the multiple storage capacities corresponds to a record of one of the multiple possible values. According to the asymmetric plane management method described in claim 1, wherein the block omission table includes at least one set of block skip indexes; and the at least one set of block skip indexes is an array, The array includes one or more sub-arrays, and a sub-array count of the one or more sub-arrays of the array is equal to the maximum number of planes minus the non-flat The difference in the number of balance planes, where the size of the array is equal to the total number of the at least one set of blocks. For example, the asymmetric plane management method described in claim 1 further includes: judging whether at least one of the block numbers is less than a block threshold to generate a judgment result, wherein the block threshold Equal to the maximum value of all available block numbers, and the judgment result indicates whether the at least one of the block numbers is less than the block threshold; and the judgment result indicates that the block number is The at least one is smaller than the block threshold, and based on the remaining block numbers in the all available block numbers as an index, other blocks in the unselected plane and the area recorded in the block omission table Blocks make up other super blocks. The asymmetric plane management method described in item 3 of the scope of patent application, wherein the remaining block number includes a subsequent block number of the block number, and the other blocks of the unselected plane include The subsequent block corresponding to the subsequent block number, and the other super block includes the subsequent super block of the super block. According to the asymmetric plane management method described in item 3 of the scope of patent application, the step of determining whether the at least one of the block numbers is less than the block threshold to generate the determination result includes: The last block number in a block number sequence formed by the number is compared with the block threshold to generate the judgment result, wherein the last block number is the maximum value of the block numbers. According to the asymmetric plane management method described in the first item of the scope of patent application, the multiple possible values represent multiple candidate values, and the possible value represents a candidate value among the multiple candidate values. A data storage device includes: a non-volatile memory (NV memory) for storing information, wherein the non-volatile memory includes a plurality of non-volatile memory elements (NV memory elements), And the plurality of non-volatile memory elements include a plurality of blocks; and a controller coupled to the non-volatile memory for controlling the operation of the data storage device, wherein the controller includes: a processing circuit, Used to control the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller, wherein: the controller sets a The number of unbalanced planes (unbalanced plane number), wherein the number of unbalanced planes is less than a maximum plane number, and the maximum plane number represents the sum of the number of the respective planes of the plurality of non-volatile memory elements; the controller selects the At least one plane of the maximum number of planes minus the number of unbalanced planes, and records at least one group of blocks of the at least one plane in a block skip table; the controller uses the block number as an index, and The blocks of the unselected planes constitute a super block, wherein the super blocks respectively correspond to the block numbers; and the controller records the total capacity of all super blocks and the number of unbalanced planes Volume to generate a newest record among the records of multiple storage capacities for further setting the storage capacity configuration of the data storage device, wherein the all super blocks include the super blocks and the multiple storage capacities The records respectively correspond to multiple possible values of the number of unbalanced planes, so as to allow a user to select a record corresponding to a possible value among the multiple possible values from the records of the multiple storage capacities according to requirements. For the data storage device described in claim 7, wherein the block omission table includes at least one set of block omission indexes (bloclk skip indexes); and the at least one set of block omission indexes is an array, and the array includes One or more sub-arrays, and a sub-array count of the one or more sub-arrays of the array is equal to the difference between the maximum number of planes minus the number of unbalanced planes, wherein the size of the array is equal to the at least The total number of blocks in a group. For the data storage device described in item 7 of the scope of patent application, the controller determines whether at least one of the block numbers is less than a block threshold to generate a determination result, wherein the block threshold is equal to all available The maximum value of the (available) block number, and the judgment result indicates whether the at least one of the block numbers is less than the block threshold; and the judgment result indicates that the at least one of the block numbers Is smaller than the block threshold, the controller uses the remaining block numbers in the all available block numbers as an index, and indexes the other blocks of the unselected plane and the area recorded in the block omission table. Blocks make up other super blocks. The data storage device described in claim 9, wherein the remaining block number includes a subsequent block number of the block number, and the other blocks of the unselected plane A subsequent block corresponding to the subsequent block number is included, and the other super block includes the subsequent super block of the super block. The data storage device described in item 9 of the scope of patent application, wherein the controller compares the last block number in a block number sequence formed by the block number with the block threshold to generate the judgment As a result, the last block number is the maximum value among the block numbers. For the data storage device described in item 7 of the scope of patent application, the multiple possible values represent multiple candidate values, and the possible value represents a candidate value among the multiple candidate values. A controller for a data storage device. The data storage device includes the controller and a non-volatile memory (NV memory). The non-volatile memory includes a plurality of non-volatile memory devices (NV memory). element), the plurality of non-volatile memory elements include a plurality of blocks, and the controller includes: a processing circuit for controlling the control according to a plurality of host commands from a host device To allow the host to access the non-volatile memory through the controller, wherein: the controller sets an unbalanced plane number, wherein the unbalanced plane number is less than a maximum plane number, and The maximum number of planes represents the sum of the number of respective planes of the plurality of non-volatile memory elements; the controller selects at least one plane from the maximum number of planes minus the number of non-balanced planes, and sets at least one plane of the at least one plane A group of blocks are recorded in a block skip table; According to the block number as an index, the controller composes the blocks of the unselected plane into super blocks, wherein the super blocks respectively correspond to the block numbers; and the controller records the total capacity of all super blocks And the number of unbalanced planes to generate a newest record among the records of multiple storage capacities for further setting the storage capacity configuration of the data storage device, wherein the all super blocks include the super blocks and all The records of the multiple storage capacities respectively correspond to multiple possible values of the number of unbalanced planes, so as to allow a user to select a possible value corresponding to the multiple possible values from the records of the multiple storage capacities according to requirements One record. For the controller described in claim 13, wherein the block omission table includes at least one set of block skip indexes; and the at least one set of block skip indexes is an array, and the array includes one Or more sub-arrays, and a sub-array count of the one or more sub-arrays of the array is equal to the difference between the maximum number of planes minus the number of unbalanced planes, wherein the size of the array is equal to the at least one The total number of group blocks. The controller described in item 13 of the scope of patent application, wherein the controller determines whether at least one of the block numbers is less than a block threshold to generate a determination result, wherein the block threshold is equal to all available (available) the maximum value of the block number, and the judgment result indicates whether the at least one of the block numbers is less than the block threshold; and the judgment result indicates the at least one of the block numbers Less than the block threshold, the controller uses the remaining block numbers in the all available block numbers as an index, and removes other blocks of the unselected plane and the blocks recorded in the block omission table Form other super blocks. The controller described in the scope of patent application, wherein the remaining block number includes the subsequent block number of the block number, and the other blocks of the unselected plane include corresponding to the The subsequent block of the subsequent block number, and the other super block includes the subsequent super block of the super block. The controller described in item 15 of the scope of patent application, wherein the controller compares the last block number in a block number sequence formed by the block number with the block threshold to generate the judgment result , Where the last block number is the maximum value among the block numbers. For the controller described in item 13 of the scope of patent application, the multiple possible values represent multiple candidate values, and the possible value represents a candidate value among the multiple candidate values.

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