TW200847162A - Methods for storing memory operations in a queue - Google Patents

Abstract

A method for operating a non-volatile memory storage system is provided. In this method, a queue that is configured to store memory operations associated with two or more types of memory operations. Here, memory operations are associated with the maintenance of the non-volatile memory storage system. A memory operation is scheduled for execution in response to an event and the memory operation is stored in the queue.

Description

200847162 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to memory operations and, more particularly, to methods and systems for storing memory in a queue. [Prior Art] • A non-volatile memory storage system can receive, transmit, or issue operations or instructions associated with the operation of a memory. Most memory operations received or issued by the non-volatile memory storage system # are immediately executed 'however, due to • $ same timing limit (eg, initialization timeout, write command timeout limit, other timing restrictions) 'There may not be enough time allocated to fully perform the memory operation. As a result, the execution of the memory gymnastics can be ignored before the next available time slot can be delayed by the memory operation or before the next _ person triggers the suffix operation. The two-cut memory operation is temporarily stored in random access memory (RAM) of the non-volatile memory storage system. However, the RAM is configured to survive only one of every type of delay memory operation. For example, if the non-volume storage system needs a new block and the result triggers an obsolete item, the waste collection operation can be stored in RAM and later used later. Time execution. On the other hand, if the non-volatile memory and the storage system need to re-create two new blocks, the two discarded project collection operations associated with the new ones are not stored in the RAM. In addition, once the power loss ^ ^, the information stored in the RAM is lost, and the memory operation will not be performed until the next time the memory is triggered. This loss of information can result in incorrect access and reduce the reliability of the non-volatile memory storage system. As a result, positive 129496.doc 200847162 continued efforts to improve the storage of memory in non-volatile memory storage systems. SUMMARY OF THE INVENTION Various embodiments of the present invention provide methods and systems for storing memory in a row. It should be understood that the embodiments may be embodied in a multitude of ways, including in the form of a method, circuit, system, or device. Several embodiments of the invention are described below. In consistent practice

'· π μ丨山❸, 脰 is a method of 糸 。. In this method, a column is configured to store memory operations associated with two or more types of memory operations. Here, remember

Body operations are associated with maintenance of a non-volatile memory storage system. Scheduling I's the operation of the memory, in response to a continuation, and the memory operation is stored in the queue. Other embodiments and advantages of the present invention will be apparent from the description and appended claims. [Embodiment] Referring to the drawings, reference numerals are described below. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be understood from the following detailed description, and similar structural elements are similar. The detailed description of the embodiments, or the embodiments, are provided in conjunction with the accompanying drawings, but are not limited to any. The scope of the patent is limited only by the scope of the patent application, and the numerous equivalents are recited in the following description in order to clarify the details for the purpose of example, and may be in the The described embodiments are implemented in all cases in accordance with the patent application 129496.doc 200847162. For the purpose of achieving clarity for the horse, the technical materials known in the technical fields related to the embodiments are not described in detail to avoid unnecessarily obscuring the description.

Embodiments described herein provide methods and/or systems for storing memory operations in a -. The train is stored in a non-volatile memory storage system t and is explained in more detail below. The train is configured to store memory. The 6 memory can be read by the non-volatile memory storage system and scheduled to be executed in poetry. In the case of a non-volatile memory storage system, the priority is also assigned to the memory operation and the priorities are stored in the same queue. 1 is a simplified block diagram of one example of a non-volatile memory storage system in accordance with an embodiment of the present invention. A host system (e.g., a desktop computer, audio player, digital camera, and other computing device) can write data to or read data from the non-volatile memory storage system 102. The non-volatile memory storage system 1〇2 can be embedded within the host or can be movably connected to the host. As shown in FIG. 1, the non-volatile memory storage system 102 includes a memory control 110 in communication with the memory 118. In general, the memory controller 11 controls the operation of the memory port 18. The memory controller 110 includes a bus bar 124 that is interfaced with the system bus 126 via a host interface i 〇4. The memory controller 11 is further interfaced with the memory 11 8 via the 3 memory interface 108. a host interface 1 〇 4, a processor 106 (eg, a microprocessor, a microcontroller, and other processors), a memory interface 108, a random access memory (RAM) 12, an error correction code (ECC) circuit 114, and The read-only memory (R〇M) 16 is connected to h by means of busbars 124 129496.doc 200847162. The ROM 116 can store a storage system firmware including private instructions for controlling the operation of the memory 118. Processor 1 〇 6 is configured to execute program instructions loaded from ROM 116 or from non-volatile memory cell array 122. The storage system firmware can be temporarily loaded into the RAM 112, and in addition, the RAM can be used to buffer information transferred between the host and the memory port 8. Additionally, RAM 112 can be configured to store a bank 131 of memory operations. The ECC circuit 114 can check for errors that pass through the memory controller 110 between the host and the memory 118. If an error is found, the ECC circuit 114 can correct a plurality of error bits, the number depending on the ECC algorithm utilized. Memory 118 can include array logic 12A and non-volatile memory cell array 122. The non-volatile memory cell array ι 22 may comprise various combinations or a combination of non-volatile memory structures and techniques. Examples of non-volatile memory technologies include flash memory (eg, NAND, NOR, single layer cell (SLC/BIN), multi-level cell (MLC), split bit line nor(din〇r), AND, High capacitance coupling ratio (HiCR), asymmetric contactless transistor (AcT) and other flash memory), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) ), read-only memory (ROM), one-time programmable memory (οτρ) and other notation techniques. In addition to the RAM 112, the bank 13 of memory operations can also be stored in the non-volatile memory cell array 122. In addition, the array logic 120 interfaces the memory controller 与0 with the non-volatile cryptographic, body cell array 122 and provides, for example, addressing, data transfer and sensing, and other support to the non-volatile memory cell array. To support the non-volatile memory cell array 122, the array logic 120 can include column decoding 129496.doc 200847162, 仃 decoder, charge pump, word line voltage production. Input/output 缕 抑 , 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝= is a flow chart of a general overview of stored memory gymnastics = according to an embodiment of the invention. Starting at 27〇 = =: Provided in the storage system, the columns can be configured!多种 Operation of a variety of f material structure. Examples of data structures include tables, arrays, and other data structures. Here, it can be stored in the memory operation of the 盥_斗, #α t口茨4丁列~~ or the type of memory operation. In another embodiment, the cartridge stores memory operations associated with memory operations of two or more members. For example, trait 1 can store two obsolete items that operate on two different blocks: set; two: - the waste collection operation is a type or a single type of memory wrestling). In addition, the trainer can store five read-and-clean processing (serub) operations for five different block operations - read clean processing operations as - type ^ single-type memory operations). The hash can be stored in a variety of memories in a non-volatile memory storage system. In the embodiment, the array is stored in the non-volatile memory storage system, the non-volatile memory unit array. In another embodiment, the register is stored in random access memory in the non-volatile memory storage system. In yet another embodiment, the array is stored in both the random access memory and the non-volatile memory cell array within the non-volatile memory storage system. A memory gymnastic is an instruction to direct the non-volatile memory storage system to perform tasks. In one embodiment, memory operations can be associated with maintenance of a non-volatile memory storage system. These memory operations can be referred to as housekeeping 129496.doc 200847162 (house keeping) operations. Housekeeping operations include memory operations that are not transmitted to the host or host request. Thus, for example, the housekeeping operation includes all memory operations other than the erase operation, the write operation, and the read Z packet requested or initiated by the host. Examples of housekeeping operations include 2 sets of discarded items, wear leveling, read cleanup, block clearing, write buffer block compression, program error recovery, write recovery, and other memory operations. . Please note that in the Waste Project Collection =, valid data from one block is copied to another block. After the valid data is sent, the original block is erased to provide the storage capacity. The blocks of the data stored in the memory are periodically discarded (ie, compressed or merged) to reproduce the storage capacity of the memory. Periodically relocating the logic material stored in the non-volatile memory cell array in the wear jade " makes the data migrate throughout the entire physical memory of the non-volatile memory cell array' and all blocks are All-ground wear. It should also be appreciated that when using a non-volatile memory storage system, the threshold level of the memory unit may lose margins' thereby creating soft errors that are not easily (four). The non-volatile memory cell array can be continuously cleaned to maintain the memory cell; ', within the field margin. In the _take cleanup operation, the test memory is 疋: ': fixed, with its margin, and if not, it is overwritten with the appropriate margin. L body single sputum. In the write buffer block clear, the data stored in the write buffer: block is copied to another block. In the write buffer block compression:, compress the valid data stored in the write buffer block. It should also be understood that a write operation may fail when one of the areas of the array of memory cells (such as '-blocks) is lost. In the program error recovery 129496.doc 200847162, the failure will be λ 4W ^ Copy to another valid data stored in this area before staying. Similarly, if the power loss occurs during a write operation to an area of the non-volatile memory cell array, the write resume command is written. Copy the valid data written before the power loss to another location. At 272, 'schedule-memory operates to respond to the event line. One event in the non-volatile memory storage system can trigger one Memory operation. An event may be the satisfaction of one (four) of the two-conditions in the non-volatile memory storage system, or a criterion, or one of the commands for the operation of the memory-memory operation. Examples of the event include the host receiving the trigger—the data of the closed block of the update block, the detection of a stylized failure in the update block, and the detection of the write abort of the write abort recovery in a block. , meet the criteria of the re-new building system block, meet the criteria for homogenization of the product, meet the trigger control block (for example, write buffer block, map block, index block, write The criteria for dust shrinking of buffer block index blocks 'and other control blocks' (for example, the amount of space remaining in the control block), and other events. Events that trigger memory operations and non-volatile memory storage systems Depending on the state, memory operations can be scheduled for immediate execution or scheduled for execution at a later time. For example, if the non-volatile memory storage system is currently writing data, it is non-volatile. The memory storage system can schedule the memory operation triggered by the data to be executed after the data is written. In another example, if the non-volatile memory storage system is not busy, the memory can be scheduled to be received. Operation for immediate execution. 129496.doc 200847162 Body operation for execution, stored in the column at 274. The column can be stored in non-volatile memory: multiple memory in the system In the area For example, as explained in more detail below, 'can be spanned by one or more sections, pages or columns. If the queue is stored in non-wing, Ί = sub-indicated by Ding Kai, 丨王圯In the case of a pure non-volatile memory storage system, the heart is lost and stored in the 2* U body operation. Initializing the non-volatile memory storage system

%, set the non-volatile memory storage system to the initial state. When the non-volatile memory storage system is separated from the host and (4) reconnected to the host: or when the non-volatile memory storage system receives from the host - reset command 'in the case of power cycling, non-volatile Initialization of the memory storage system. Figure 3 is a simplified block diagram of the organization of the memory cell array as a plane. As noted above, the array can be stored in the area of the femoral body within the non-volatile memory storage system. Note that one or more memory cell arrays can be spliced into a single plane or sub-array. In the example of Fig. 3, the 35-memory cell array is divided into four planes 2〇2 to 2〇5. Other numbers of planes (4, 16, or more) may be present in a non-volatile memory storage system. Each plane 2〇2, 2〇3, 2〇4 or 2〇5 can be divided into blocks of memory cells such as blocks 210 to 213 and 220 to 223 located in respective planes 2〇2 to 205. . A block of memory cells is the smallest number of memory cells that can be physically erased together. To increase parallelism, blocks can be manipulated in larger block units, where blocks from each plane 2〇2, 203, 204, or 205 are logically linked together to form a unitary area 129496.doc • 12- 200847162 A cattle case, you can turn the four blocks 21 to 213 logic to form a one-dimensional zone. From the ^ bucket button to the respective J =, the block used to form the metablock can come from its words, and can be white to 2〇5). For example, 220 to 223 logically recorded from each position in the respective planes 202 to 205. The four & blocks can be extended over the non-volatile surface 2〇2 Soap 5 丨 丨 丨 储存 储存All four logic levels in the system are $ to 205, or the non-volatile memory storage system can dynamically form metablocks from one or more of the non-5 planes.

The mountain work and the illusion are stored in one or more blocks. For example; The queue can be stored in a control block (such as a write buffer block). The write buffer block is maintained in a non-volatile memory cell array. The writer buffer block buffers the received data in a non-volatile U-body storage system. The write buffer block acts as a temporary buffer for the data written to the write buffer block to be later copied to another block. A far write buffer block can span multiple logical addresses. For example, the write buffer block can span the entire logical address space. By writing across the entire logical address space, the write buffer block can be stored to be written to the non-sweep. All the logical addresses of the system and all the groups of the logical addresses "that is, all logical groups). In other words, data associated with different logical groups is stored in the write buffer block. Note that a logical group is a group of logical addresses having a size equal to the size of a unitary block. The second instance of the control block is an index block. In general, the index block stores index information for accessing various blocks in the non-volatile memory storage system. The information may, for example, include an effective complex for various types of blocks. 129496.doc -13- 200847162 Information about the location of this location. The third instance of the control block is a mapped block. The mapping block stores the mapping of the blocks in the non-volatile memory storage system and indicates whether the information of each block is erased. For example, a mapped block can store a column address of an erased block. The fourth example of the control block is the boot block. The boot device block stores the current address of the mapped block. In other words, the boot-up block stores the metrics for the mapped block. Therefore, when the mapping block is relocated, the current address of the mapping block stored in the booting block is updated. The bootable boot block can be located in the first available metablock. The fifth example of a control block is a scratch pad block. It should be understood that the scratch pad block is in the form of one of the data update blocks in which the logical segments can be updated in random order and in any amount of repetition. The scratch pad block is created by a write command in which the desired logical segment is not terminated or crossed over a physical page boundary. Since the non-volatile memory storage system may not be able to program a partial page, a section of a page may be temporarily stored in the scratch pad block. The non-volatile memory storage system accumulates the segments of the page in the scratch pad block until all segments of the page are populated with new data from various write commands. The non-volatile memory storage system then copies the entire page (e.g., new data for eight segments) from the high speed temporary storage block to another block (e.g., update block) in a program operation. 4 is a simplified block diagram of a page of a memory cell. Each block (e.g., blocks 210 through 213) can be further divided into pages of memory cells. As a result, the array can cover one or more pages of the memory unit. As shown in Fig. 4, each block 210, 211, 212 or 213 is divided into eight pages p to p7. Alternatively, there may be a page of 16, 32, or 129496.doc -14 - 200847162 in the parent block 210, 211, 212 or 213. To increase the operation of the non-volatile memory storage system and alphaness, pages within two or more blocks can be logically keyed into a metapage. For example, a unitary page may be formed by one page (such as P1) and formed by each of the four blocks 21G to 213. - The metapage can be extended beyond the non-volatile § memory storage system > %i I 〇·, , all the thousands of faces in the dead, or the non-volatile memory storage system can be - or in multiple different planes One or more of the one or more independent blocks dynamically form a metapage. Figure 5 is a simplified block diagram of a section of a memory cell. You can put a page into a v-cut into a 4th-segment section. The result '伫 column can cover one or more segments of the memory unit. The amount of data in each page can be an integer number of one or more sections of data /, the middle section can store 512 bytes of data. Figure 5 shows a page 5CU divided into two sections 502 and 504. Each section is 5〇2 or 50恃 There are information on the size of 512 bytes, 5〇6, and additional information related to this data. The size of the additional item milk can be a triad and can store, for example, the ECC calculated from the data 506 during the stylization, the logical address associated with the data, the number of erased and reprogrammed blocks. Count, control flag, operating power | level, and other information associated with the (d). Figure 6 is a flow diagram of a general overview of memory memory operations and operations associated with memory cell operations in accordance with an embodiment of the present invention. Beginning at 602, a wide list is provided, and the queue is configured to store memory operations and priorities associated with the memory operations. In response to an event, the schedule-memory operation is performed at 6〇4, and the priority is assigned to the memory operation at 6〇6. Some memory operations can be scheduled for execution by other memory operations by assigning - priority 129496.doc -15-200847162 to each memory operation. Different memory operations can be assigned different priorities. For example, the priorities may be two levels of high or low priority. In another example, the priorities may include multiple levels as shown in Table A below. _ Another *J 〇 describes the priority Μ〇〇, ', Ό 2" "05, 3 or erase operation lin or in the background Operation (during the idle period of the host = remember to write the buffer block item. ~— ----- β except from the write buffer --- memory. Clear the note, in the table The operation with low priority memory will be scheduled for execution before the memory operation with ",,,) < "〇6"). '• and a number (for example, a non-volatile memory storage system correctable element ^4 ' (ECC) can be predetermined or calculated based on - or more parameters and there is an error correction error of seven bits. The memory operation. In the absence, if the priority will be assigned to the priority of the error 129496.doc -16· 200847162 can assign the low priority to the memory of the correction error as an example: 'can be based on memory operation The type (eg, wear-and-sequence, obsolete item collection at the read location, and other types of memory operations) to assign priorities to memory operations. In other words, priority can be expressed as priority ==/ (memory Type of operation)

The function whose priority is the type of memory operation. For example, a grinding memory can be assigned or assigned to - low priority. In the other embodiment, the priority can be assigned to the memory operation based on the type of event that triggers the memory compilation. In other words, the priority line can be expressed as priority = / (type of event) where priority is a function of the type of event that triggers the memory operation. A real J assigns a medium priority to a memory operation triggered by a failure in the update block. On the other hand, it is assigned to the high-priority of the memory operation triggered by the write abort recovery. In yet another embodiment, the H level can be based on a combination of the type of a fe operation and the type of event that triggers the memory operation. In other words, the priority can be expressed as priority = / (type of memory operation, type of event) where priority is a function of the type of memory operation and the type of event that triggers the operation of the memory. After the priority is assigned to the memory operation, the memory gymnastics is prioritized and stored in the queue at 608. Here, the queue may include items for memory operations, priorities associated with memory operations, and other information associated with memory operations, such as number of blocks, sector locations, page 129496. Doc -17, 200847162 Location, count, specific sections within a block, and other information. Still look at Figure 6' and then perform the memory operation at 61 。. It should be understood that the memory operation may be performed in full, because (for example) no sufficient time is allocated to perform the memory operation. Therefore, the execution of the memory operation can be delayed. In an embodiment, as shown at 612, the execution process can be stored in a queue. The execution process indicates the amount of memory operations that have been completed. The execution process includes a variety of information related to the progress of the execution of the C memory operation. This information can include the point, status, or stage of execution. For example, the number of replicated regions, pages, and/or segments, at various levels of memory operations when performing phasing to a predetermined level (eg, the first, second, or third level of firmware upgrade) Or stage, and other information. The memory operation can be partially performed according to the execution process stored in the queue. At a later time, even if a power cycle occurs between the execution of the memory segment, the execution of the memory operation can be resumed before completion. ❿

= is a flow chart of a general overview of the operation of the (four) read memory operation in accordance with an embodiment of the present invention. Start at 7〇2 and provide a column. As described above, the priority of the memory operation to be executed and/or the execution process are scheduled in the hash. At 7〇6; = ❹ read memory operation. In the initial cut volatility (4) I know that the non-volatile memory storage system can be read from the list. = The sexual memory system is not busy performing other memory operations, but also from the second! The column reads the non-volatile memory material system. For example, the host allows =: Quantitative time: meaning, - timeout period to perform 'write: For example, the secure digital agreement limits the amount of time to 25 〇 129496.doc 18- 200847162 Time period. The excess amount of time (the difference between the amount of time written into the operation) may be performed by the memory gymnastics stored in the queue, and at 708, the reading is performed from the queue. Your associated priority...take, ritual, alpha oysters can also be read from the 伫 与 与 与 恃 恃 恃 相关 相关 相关 相关 相关 相关 相关 相关 相关 相关 相关 相关 相关 ... ... ... ... .... At 712, then schedule a specific record _

The body is used for the stick. Household ^ Bamboo 疋忑 In a case, it can be scheduled based on priority. It has been carefully designed for execution. Ding Shi insisted on entering and smashing, memory gymnastics, ancient, can be continued since the beginning of the implementation of the earlier. For example, in the example ~, the execution process is configured to define the - execution point. The execution point is a strong IU ^ ν Λ (3) and the end of the execution. It can be opened from this point of execution: the memory operation is performed. In other words, the execution of the operation can be continued from the execution point (4). Partially executed or completely executed memory

The amount of time to enter the operation can be small, that is, the timeout period is used to execute the volatile memory system. . The right side performs the memory shot, and the execution process is stored in the queue so that the waiter can resume the execution of the memory operation at a later time. However, if the memory operation is completely performed, the column can be removed or deleted: the memory operation. #着可排根据 According to the priority level, it is from Xiao Lie - Memory Gymnastics for execution. Although the foregoing embodiments have been described in some detail for the purpose of clarity of understanding, the embodiments are not limited to the details provided. There are many alternative ways of implementing these embodiments. Therefore, the disclosed embodiments are to be considered as illustrative and not limiting, and the embodiments are not limited to the details provided herein %. dOC -19- 200847162 Modified. In the scope of patent application, the macro _, the scope of the patent, and the H and/or operation do not imply any [simplified description], stay-person order. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified block diagram of one example of a non-volatile memory storage system in accordance with one embodiment of the present invention. Figure 2 is a flow diagram of a general overview of the operation of a memory memory operated by a mussel in accordance with one embodiment of the present invention.

Figure 3 is a simplified block diagram of the organization of the memory cell array as a plane. 4 is a simplified block diagram of a page of a memory cell. Figure 5 is a simplified block diagram of a section of a memory cell. two. A general overview of the operation of storing memory and the operations associated with the recording in accordance with an embodiment of the present invention. : Flowchart for a general overview of a self-aligned read memory operation operation in accordance with an embodiment of the present invention. [Major component symbol description] 102 104 106 108 110 112 114 116 Non-volatile memory storage system host interface processor έ memory interface controller random access memory (RAM) error correction code (ECC) circuit only Read Memory (ROM) ^9496.d〇c -20- 200847162

118 Memory 120 Array Logic 122 Non-volatile Memory Cell Array 124 Bus Bar 126 System Bus 130 伫 131 131 Array 202 Plane 203 Plane 204 Plane 205 Plane 210 Block 211 Block 212 Block 213 Block 220 Block 221 Block 222 Block 223 Block 501 Page 502 Section 504 Section 505 Additional Information 506 Data P0 Page 129496.doc -21 - 200847162 P1 Page P2 Page P3 Page P4 Page - P5 Page, P6 Page P7 Page 129496. Doc -22

Claims (1)

200847162 X. The scope of application for patents: 1 · A method for operating a non-volatile recording body, from the u basket storage system, comprising: providing a queue, the queue is configured to store and Two or more types of memory operations are performed by the plurality of memory operations as of the next day. 'The plurality of memory operations and the non-history machine ^ & a maintenance of the non-volatile memory storage system Associated; a schedule-memory operation to cause it to be executed in response to an event; and storing the memory in the queue. 2. The method of claim 1, further comprising taking the memory operation from $ _ 匕 3 from δ 彳 彳 。. 3. The method of claim 1, further comprising: assigning a priority to the memory operation; and storing the priority in the queue. 4. The method of claim 3, wherein the priority is assigned based on one of the types of memory operations. , 5· :: method of claim 3, wherein the priority is assigned based on one of the types of events. 6. The method of claim 1, further comprising: performing the memory operation; and storing an execution process in the queue. 7. The method of claim 6, further comprising: deleting the memory operation from the register if the memory operation is completely performed; and 129496.doc 200847162 Affecting the memory operation by the location The execution process is in the 8th request item! The method of storing the memory in the non-volatile memory 10: the method of item 1, wherein the queue is stored in the control block. The method for operating a non-volatile memory storage system , the package provides a child column, the character string configured to store the memory of the plurality of memory gymnastics associated with two or more operations: memory operation =: memory operation and the non-volatile The memory storage system reads a memory operation from the queue; and schedules the memory operation for execution. 11·If (4) the heart method 'is let the (4) be configured to store and the complex number k a plurality of priorities associated with the body operation. 12. The method of claim u, further comprising reading from the column: a priority associated with the memory operation, wherein the priority is scheduled based on the priority The method of claim 10, wherein the sequence is configured to store a plurality of execution processes associated with the plurality of memory operations. The method further comprising: reading one from the queue The memory operation is associated with an execution process that is configured to define an execution point; and the memory operation is performed from the execution point. 129496.doc 200847162 15: = :°; method 'its_Ning Stored in the non-volatile memory system 2 1G to 'initiate the non-volatile memory storage', ,,,%, read the memory operation from the queue. 17.=:!10 method, Wherein the non-volatile memory storage system is not busy ¥, the memory is read from the queue::::r method, the axis of which is stored in a block. The method, wherein the column is stored in a Write buffer block 20.: The method of requesting 0, wherein the queue is stored in the booting block 2 1 · If the method is as follows, the method 22 is as in the method of claim 1 其中. The queue is stored in a mapping block. A method for operating a non-volatile memory storage system, the package internal operation and the 'column storage providing a queue, the queue configured to store a plurality of the plurality of housekeeping operations The associated plurality of priorities are stored in a cache pad; the exclusive operation is performed to cause it to be executed in response to an event, a priority is assigned to the housekeeping operation; and the housekeeping operation and the priority are stored Level in this queue. 24. The method of claim 23, further comprising: reading the housekeeping operation and the priority from the queue; and 129496.doc 200847162 scheduling the housekeeping operation for execution based on the priority. 25. The method of claim 23, wherein the priority is assigned based on one of the housekeeping operations. The method of claim 23, wherein the priority is assigned based on one of a type of continuation | (4) event. ^ The method of claim 23, wherein the queue is stored in an array of non-volatile memory cells in the non-volatile memory storage system. 28. The method of claim 23, wherein the (four) is stored in one of the non-volatile memory storage systems. 29. A method for operating a non-volatile memory storage system, comprising: ^L providing a queue configured to store a plurality of housekeeping operations and associated with the plurality of housekeeping operations a plurality of priority levels, the queue being stored in a cache block; reading a house operation and a priority associated with the house operation from the queue; and scheduling the house operation based on the priority Used for execution. A non-volatile memory storage system comprising: a non-volatile memory cell array configured to store a list of 'edge' columns configured to be stored with two or more a plurality of memory operations associated with a plurality of types of memory operations associated with maintenance of the non-volatile memory storage system; and a processor associated with the non-volatile memory Cell array communication, the 129496.doc 200847162 processor is configured to schedule a memory operation to cause it to execute in response to an event, and to store the memory in the queue. 3 1 - The non-volatile memory storage system of claim 3, further comprising a random access memory in communication with the processor, the random access memory configured to store the queue. A non-volatile memory storage system as in claim 30, wherein the processor is further configured to read the memory operation from the queue. The non-volatile memory storage system of claim 30, wherein the processing cry is further configured to: assign a priority to the memory operation; and store the priority in the column. 34. The non-volatile memory storage system of claim 33, wherein the priority is assigned based on one of the types of memory operations. 35. The non-volatile memory storage system of claim 33, wherein the priority is assigned based on one of the types of events. Wherein the processor, wherein the processor 36, such as the non-volatile memory storage system of claim 30, is further configured to: perform the memory operation; and store an execution process in the queue. 37. The non-volatile memory storage system of claim 36 is further configured to: if the memory operation is performed entirely, the operation; and the memory is deleted from the queue 129496.doc 200847162 if the memory is partially executed The body operation stores the execution process in the column. 3^ The non-volatile memory storage system of claim 3, wherein the queue is stored in a control block. 39. A non-volatile memory storage system, comprising: a random access memory configured to be a material-care column configured to store complex numbers of two or more types The plurality of memory operations associated with the memory operation, the plurality of memory operations being associated with maintenance of the non-volatile memory storage system; and the processor 'communicating with the random access memory, the processing The device is configured to read a memory operation from the queue and schedule the memory operation for execution. 40. The non-volatile memory storage system of claim 39, further comprising - an array of non-volatile memory cells in communication with the processor, the non-volatile $ memory cell array configured to store the queue. 41. The non-volatile memory storage system of claim 39, wherein the queue is further configured to store a plurality of priorities associated with the plurality of memory operations and wherein the processor is advanced Step configuration to read from the queue: a priority associated with the memory operation, wherein the memory operation is based on the priority schedule for execution. 42. The non-volatile memory storage system of claim 39, wherein the memory operation is read from the array when the non-volatile memory storage system is initialized. The non-volatile memory storage system of claim 39, wherein the memory operation is read from the slave when the non-volatile memory storage system is not busy. 44. The non-volatile memory storage system of claim 39, wherein the queue is further configured to store a plurality of executions associated with the plurality of memory operations, and wherein the processor The configuration reads an execution process associated with the memory operation from the character string. 45. The non-volatile memory storage system of claim 44, wherein the execution process is configured to define an execution point, and wherein the processor is further responsive to perform the memory operation from the execution point. 46. The non-volatile memory storage system of claim 39, wherein the queue is stored in an index block. 47. The non-volatile memory storage system of claim 39, wherein the queue is stored in a write buffer block. 48. The non-volatile memory storage system of claim 39, wherein the queue is stored in a boot-up block. 49. The non-volatile memory storage system of claim 39, wherein the queue is stored in a mapping block. 50. The non-volatile memory storage system of claim 39, wherein the queue is stored in a high speed temporary storage block. 51. A non-volatile memory storage system, comprising: a random access memory configured to store a queue configured to store a plurality of housekeeping operations and the plurality of housekeeping Manipulating a plurality of priority operations associated with the plurality of two or two types of overhead operations of the type 129496.doc 200847162; and a processor communicating with the non-volatile memory unit array The processor is configured to schedule a housekeeping operation to cause it to execute in response to an event, assign a priority to the housekeeping operation, and store the housekeeping operation and the priority in the queue. 52. The non-volatile memory storage system of claim 5, wherein the processor is further configured to: Reading the housekeeping operation and the priority from the queue; and scheduling the housekeeping operation for execution based on the priority. 53. The non-volatile memory storage system of claim 51, wherein the priority is assigned based on one of the types of overhead operations. 54. The non-volatile memory storage system of claim 5, wherein the priority is assigned based on one of the types of events. 55. A non-volatile memory storage system, comprising: a non-volatile memory cell array configured to store a queue configured to store a plurality of house operations and with the plurality = a plurality of priorities associated with the housekeeping operation, the queue being stored in a cache block; and 'a processor communicating with the array of non-volatile memory cells, the processor being configured to associate The read-to-house operation and the priority from the housekeeping operation are prioritized, and the housekeeping operation is scheduled for execution based on the priority. 129496.doc