^380303 九、發明說明： 【發明所屬之技術領域】 本發明大體上係關於記憶體操作，且更特定言之， ° 係關 於儲存記憶體操作於佇列中之方法及系統。 【先前技術】 非揮發性記憶體儲存系統可接收、傳輸或發出與記憶體 之操作相關聯的操作或指令。由非揮發性記憶體儲存系统 接收或發出之多數記憶體操作經立即執行。然而，歸因於 不同定時限制（例如，初始化逾時、寫入命令逾時限制， 及其他定時限制）’可能未分配足夠時間以完全地執行記 憶體操作。結果’在下一可用時槽之前可使記憶體操作： 執行延遲，或在下次觸發記憶體操作之前可忽視記憶體操 作之執行。 、 目則，a己憶體操作臨時儲存於非揮發性記憶體儲存系統 之隨機存取記憶體（RAM)中'然而，RAM經組態以儲存每 類之延遲6己憶體操作中之僅一者。舉例而言，若非揮 發1"生《己隐體儲存系統需要再新一區塊且結果觸發一廢棄項 目收集操作’則該廢棄項目收集操作可儲存於ra财且經 L遲用於在稍’後時間執行。另—方面，若非揮發性記憶體 儲存系、统需要#新兩個區塊，則與該等再新相關聯之兩個 廢棄項目收集操作不儲存於RAM中。此外，一旦功率損失 發生，則儲存於RAM中之資訊丟失，且在下次觸發此記憶 -喿乍之則將不執行§己憶體操作。此資訊損失可導致存取 錯誤且降低非揮發性記憶體儲存系統之可靠性。結果，正 129496.doc 1380303 繼續努力改良記憶體操作於非揮發性記憶體儲存系 儲存。 ，、巩τ之 【發明内容】 本發明之各種實施例提供用於儲存記憶體操作於佇列中 之方法及系統。應瞭解’可以眾多方式來實施該等實施 例’包括以方法、電路、系統或器件之形式。在下文中： 述本發明之若干實施例。 田 在一實施例中，提供-種操作非揮發性記憶體儲存系統 之方法。在此方法中，-仔列經組態以儲存與兩種或兩種 以上類型的記憶體操作相關聯的記憶體操作。此處 體操作與非揮發性記憶體儲存以之維護相關聯。排程二 =憶體操錢其喊於_事件而執行，且該記憶體操作儲 存於該件列令。 結合附圖，借助於實例說明本發明之原理，由以下詳细 描述顯見本發明之其他實施例及優點。 、 【實施方式】 結合附圖’將易於由以下詳 弄描述理解本發明，且相似 參考數字指定相似結構元件。 在下文中連同附圖—起提供斜_ ^ . %杈供對或多個實施例之詳細描 述。洋細描述係結合此等實 貫施例來提供，但其不限於任何 特疋實施例。範_僅香Φ 4主_ 4丨# m “值又申5月專利範圍限制，且涵蓋眾多替 代、修改及等效物。在以下描 迩中陳述眾多特定細節以便 k供洋盡理解。提供此等細節以達成舉例之目的’且可在 無此等特定細節中之一肽哎全 —及全部的情況下根據申請專利範 129496.doc 1380303 圍來實施職述之實施例。為達成清楚之目的，未詳細地 描述在與該等實施例㈣之技術領域中已知的技術材料以 避免不必要地使描述晦澀難懂。 本文所描述之實施例提供儲存記憶體操作於一佇列中之 法及/或系.统肖〇列儲存於非揮發性記憶體健存系統 中，且如下文更詳細地解釋，該作列經組態以儲存記憶體 操作。記憶體操作可由非揮發性記憶體儲存系統讀取且經 排程以用於執行。在—實施例中，非揮發性記憶體儲存系 統亦將優先級指派給記憶體操作且儲存該等優先級於同一 佇列中。</ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Prior Art] A non-volatile memory storage system can receive, transmit or issue operations or instructions associated with the operation of a memory. Most memory operations received or issued by the non-volatile memory storage system are performed immediately. However, due to different timing constraints (e.g., initialization timeout, write command timeout limits, and other timing constraints), there may not be enough time allocated to fully perform the memory operation. The result 'can be manipulated before the next available time slot: execution delay, or the execution of memory gymnastics can be ignored before the next time the memory operation is triggered. , the purpose, a memory operation is temporarily stored in the random access memory (RAM) of the non-volatile memory storage system. 'However, the RAM is configured to store only the delay of each type of memory. One. For example, if the non-volatile 1" raw "hidden storage system needs a new block and the result triggers an abandoned project collection operation" then the waste project collection operation can be stored in Ra Finance and L is used lately. Execution after the time. On the other hand, if the non-volatile memory storage system requires # new two blocks, the two discarded project collection operations associated with the new ones are not stored in the RAM. In addition, once the power loss occurs, the information stored in the RAM is lost, and the memory is triggered next time - then the § memory operation will not be performed. This loss of information can result in access errors and reduce the reliability of the non-volatile memory storage system. As a result, positive 129496.doc 1380303 continues to work to improve memory operations in non-volatile memory storage systems. SUMMARY OF THE INVENTION Various embodiments of the present invention provide methods and systems for storing memory in a queue. It should be understood that the embodiments may be embodied in a multitude of ways, including in the form of a method, circuit, system, or device. In the following: Several embodiments of the invention are described. In one embodiment, a method of operating a non-volatile memory storage system is provided. In this method, the queue is configured to store memory operations associated with two or more types of memory operations. Here, body operations are associated with non-volatile memory storage for maintenance. Schedule 2 = Recall that the gymnastics money is shouted at the _ event and the memory operation is stored in the order. Other embodiments and advantages of the present invention will be apparent from the description and appended claims. The present invention will be readily understood from the following detailed description, and the like reference The simplifications of the pair or embodiments are provided below in conjunction with the accompanying drawings. The detailed description is provided in connection with such actual embodiments, but it is not limited to any particular embodiment. _ _ 香 Φ 4 main _ 4 丨 # m "The value of the patent scope is limited to May, and covers many alternatives, modifications and equivalents. Many specific details are stated in the following description so that they can be understood. These details are for the purpose of exemplification' and may be practiced in the absence of one of the specific details, and in all cases, in accordance with the application of the patent 129496.doc 1380303. OBJECTS, the technical materials known in the technical fields of the embodiments (4) are not described in detail to avoid unnecessarily obscuring the description. The embodiments described herein provide storage memory operations in a queue. The method and/or system is stored in a non-volatile memory storage system and, as explained in more detail below, the configuration is configured to store memory operations. Memory operations may be performed by non-volatile memory The volume storage system reads and is scheduled for execution. In an embodiment, the non-volatile memory storage system also assigns priorities to memory operations and stores the priorities in the same queue.
圖1為根據本發明之一實施例的非揮發性記憶體儲存系 統之一實例的簡化方塊圖。一主機系統（例如，桌上型電 腦、音訊播放機、數位相機及其他計算器件）可將資料寫 入至非揮發性§己憶體儲存系統〗02或自非揮發性記憶體儲 存系統102讀取資料。非揮發性記憶體儲存系統1〇2可嵌入 於該主機内或可移式地連接至該主機。如圖1中所示，非 揮發性記憶體儲存系統102包括與記憶體1丨8通信之記憶體 控制器110。大體上，記憶體控制器丨丨〇控制記憶體丨丨8之 操作。記憶體控制器11 0包括經由主機介面1 〇4與系統匯流 排126介面連接之匯流排124。記憶體控制器11〇進一步經 由a己憶體介面1〇8與記憶體118介面連接。主機介面1〇4、 處理器1 06(例如，微處理器、微控制器及其他處理器）、記 憶體介面108、隨機存取記憶體（rAM)U2、錯誤校正碼 (ECC)電路114及唯讀記憶體（ROM) 1 1 6係借助於匯流排1 24 129496.doc 1380303 來通信。ROM 116可儲存包括用於控制記憶體118之操作 的程式指令的儲存系統韌體。處理器1〇6經組態以執行自 ROM 116或自非揮發性記憶體單元陣列122載入之程式指 令。可將儲存系統韌體臨時地載入於RAM丨丨2中，且另 外，該RAM可用於緩衝在主機與記憶體丨丨8之間傳送的資 料。此外，RAM 112可經組態以儲存記憶體操作之佇列 131。ECC電路114可檢查在主機與記憶體118之間經過記 憶體控制器11 0的錯誤。若發現錯誤，則ECC電路丨丨4可校 正多個錯誤位元，數目視所利用之ECC演算法而定。 記憶體118可包括陣列邏輯12〇及非揮發性記憶體單元陣 列122。非揮發性記憶體單元陣列122可包括非揮發性記憶 體結構與技術之多種組合或一組合。非揮發性記憶體技術 之實例包括快閃記憶體（例如，NAND、NOR、單層式單元 (SLC/BIN)、多層式單元（MLC)、分割位元線n〇r(din〇R)、 and、高電容耦合率（HiCR)、非對稱不接觸電晶體（act) 及其他快閃記憶體）、可擦可程式化唯讀記憶體 (EPROM)、電可擦可程式化唯讀記憶體（EEpR〇M)、唯讀 記憶體（ROM)、一次性可程式化記憶體（〇τρ)及其他記憶 體技術。除RAM 112外，記憶體操作之佇列13〇亦可儲存 於非揮發性記憶體單元陣列122中。 此外，陣列邏輯120使記憶體控制器11〇與非揮發性記憶 體單元陣列122介面連接且可向非揮發性記憶體單元陣列 提供（例如）定址、資料傳送及感測，及其他支援。為支援 非揮發性s己憶體單元陣列122，陣列邏輯i 2〇可包括列解碼 129496.doc 1^80303 盗、行解碼器、電荷泵、字線電壓產生器、頁緩衝器、輸 入/輸出緩衝器 '位址緩衝器及其他電路。 圖^為根據本發明之一實施例的儲存記憶體操作於仔列 之操作的總體概觀之流程圖。開始於27〇處，在非揮發 性冗憶體儲存系統中提供一仵列。該仔列可包括經組態以 健存記憶體操作之多種資料結構。t料結構之實例包括 ^ 陣列及其他資料結構。此處，在—實施例中，該仔列 或多種類型之s己憶體操作相關聯的多個記憶體 操作。在另一實施例中，該仵列可儲存與兩種或兩種以上 類型之记憶體操作相關聯的記憶體操作。舉例而言，該佇 料儲存對兩個不同區塊操作之兩個廢棄項目收集操作 二-廢棄項目收集操作為一類型或單一類型之記憶體操 作)。另夕卜’該佇列可儲存對五個不同區塊操作之五個讀 二淨化處理（serub)操作（―讀取淨化處理操作為—類型或 早類型之記憶體操作）。該仵列可儲存於非揮發性記憶 體儲存系統内之多種記_體中/ 心 夕種圮隐體中。在一實施例中，該佇列儲 t於該非揮發性記憶體储存系統内之非揮發性記憶體單元 °在另一實施例中’該仔列儲存於該非揮發性記憶 體儲存系統内之隨機存取記憶體中。在又一實施例中，該 知列儲存於該非揮發性記憶體儲存系統内之隨機存取記憶 體及非揮發性記憶體單元陣列兩者中。 一,憶體操作為-指導非揮發性記憶體健存系統執行任 令。在一實施例中，記憶體操作可與非揮發性記憶 體儲存系統之維護相關聯。此等記憶體操作可被稱作内務 129496.doc 1380303 (house keeping)操作。内務操作包括不傳輸至主機或不由 主機請求的t己憶體操作。因此，舉例而言，内務操作可包 括除由主機清求或發起之擦除操作、寫入操作及讀取操^ 外的所有記憶體操作。内務操作之實例包括廢棄項目收 集、磨損均勻化（wear leveling)、讀取淨化處理、寫入緩 衝區塊清除、寫入緩衝區塊壓縮、程式錯誤復原、寫入中 止復原及其他記憶體操作。請注意，在廢棄項目收集操作 中，將來自-區塊之有效資料複製至另一區塊。在傳送該 有效資料後，擦除原始區塊以提供儲存容量。對 憶體中之資料的區塊週期性地進行廢棄項目收集（意即D， 壓縮或合併）以再生記憶體之儲存容量。在磨損均勾化 中週期性地重定位儲存於非揮發性記憶體單元陣列中之 邏輯資料，使得資料在非揮發性記憶體單元陣列之整個實 體空間中遷糝，且所有區塊被均一地磨損。亦應瞭解，在 使用非揮發J·生5己憶體儲存系統時，記憶體單元之臨限位準 可月t*才貝失邊限’藉此產生不易於摘測到之軟錯誤。可連續 地淨化處理非揮發性記憶體單元陣列以使記憶體單元維持 於其適限内。在讀取淨化處理操作中，測試記憶體單 兀^判定，否維持其邊限’且若非如此，則以適當邊限重 寫。己It體早7L。在寫入緩衝區塊清除中，將健存於寫入緩 衝區鬼中之貝料複製至另-區塊。在寫入緩衝區塊壓縮 中壓縮儲存於寫入緩衝區塊中之有效資料。亦應瞭解， 在將資料寫入至非揮發性記憶體單元陣列之一區域(例 如，一區坡、& 寫入操作可能失敗。在程式錯誤復原 129496.doc 1380303 中，將在失敗之寫入操作之前儲存於此區域中之有效資料 複氩至另一位置。類似地，若在至非揮發性記憶體單元陣 歹J之區域的寫入操作期間功率損失發生，則在寫入中止 復原中將在功率損失之前寫入的有效資料複製至另—位 置。 在272處’排程一記憶體操作以使其回應於一事件而執 仃。在非揮發性記憶體儲存系統中之一事件可觸發一記恃 體操作。一事件可為非揮發性記憶體儲存系統内的一狀態 之偵測、一條件之滿足’或一準則之滿足。或者，一事件 可為執行一記憶體操作之命令的接收。事件之實例包括自 主機接收觸發一更新區塊之閉合的資料、在一更新區塊中 偵測一程式化失敗、偵測觸發在一區塊中之寫入中止復原 的寫入中止條件、滿足再新擋案系統區塊之準則滿足對 —區塊之磨損均勻化的準則、滿足觸發控制區塊（例如， 寫入緩衝區塊、映射區塊、索引區塊、寫入緩衝區塊索引 區塊，及其他控制區塊）之壓縮的準則（例如，控制區塊中 剩餘之空間量），及其他事件。視觸發記憶體操作之事件 及非揮發性記憶體儲存系統之狀態而定，記憶體操作可經 排程以用於立即執行或經排程以用於在稍後時間執行。舉 例而言，若非揮發性記憶體儲存系統目前正寫入資料，則 非揮發性έ己憶體儲存系統可排程所觸發之記憶體操作以用 於在寫入資料後執行。在另一實例中，若非揮發性記憶體 儲存系統不繁忙，則可排程接收到之記憶體操作以用於立 即執行。 129496.doc 同時，排桎該記憶體操作 憶體操作儲存於仵列卜該^可於執订，在274處將該記 ^ έ* Λ > 丨可儲存於非揮發性記憶體 堵存系統内之多種記憶體 詳細地解釋，m中舉例而言，如下文中更 ^ 跨或夕個區段、頁或區塊來儲存該佇 :卜若該㈣存於非揮發性記憶體單元陣列中，二 :::揮發性記憶體儲存系統之情況下將不丟失儲= J之。己隐體刼作。在初始化非揮發性記憶 二將非揮發性記憶體儲存系統設為一初始狀態。在非： 發性記憶體健存系統與主機分離且接著重新連接至主機 時’或在非揮發性記憶體儲存系統自該主機接收一重設命 ^夺’在功率循環之情況下’可發生非揮發性記憶體儲存 系統之初始化。 圖3為記憶體單元陣列成為平面之組織的簡化方塊圖。 如上所述，該列可儲存於非揮發性記憶體儲存系統内之 夕種《己it體區域中。4注意，可將_或多個記憶體翠元陣 列分成多個平面或子陣列。在圖3之實例中，冑一記憶體 單元陣列分成四個平面202至2〇5。其他數目之平面（諸 如’卜2、4、8、16或更多）可存在於_非揮發性記憶體 儲存系統中。可將每一平面202、2〇3、2〇4或2〇5分成記憶 體單元之區塊，諸如，位於各別平面2〇2至2〇5中之區塊 2 10至2 13及220至223。記憶體單元之一區塊為實體上可一 起擦除之最小數目的記憶體單元。為增加並行性，可在較 大元區塊單元中操作區塊，其中將來自每一平面2〇2、 2〇3、204或205之一區塊邏輯上鏈接在一起以形成—元區 129496.doc 1380303 塊。舉例而言，可將四個區塊210至213邏輯上鏈接在一起 以形成一元區塊。此外，用於形成元區塊之區塊可來自其 各別平面（諸如，平面202至205)内之各個位置。舉例而 言’可將來自各別平面202至205内之各個位置的四個區塊 220至223邏輯上鏈接在一起以形成另一元區塊。一元區塊 可延展越過非揮發性記憶體儲存系統内之所有四個邏輯平 面202至205，或非揮發性記憶體儲存系統可由一或多個不 同平面中之一或多個區塊動態地形成元區塊。 在一實施例中，該佇列儲存於一或多個區塊中。舉例而 言’該佇列可儲存於一控制區塊（諸如，寫入緩衝區塊） 中。該寫入緩衝區塊維持於非揮發性記憶體單元陣列中。 大體上’該寫入緩衝區塊將所接收到之資料緩衝於非揮發 性記憶體儲存系統中。該寫入緩衝區塊充當一臨時緩衝 器’因為寫入至寫入緩衝區塊之資料稍後被複製至另一區 塊。該寫入緩衝區塊可橫跨多個邏輯位址。舉例而言，該 寫入緩衝區塊可橫跨整個邏輯位址空間。藉由橫跨整個邏 輯位址空間，該寫入緩衝區塊可儲存將要寫入至遍及非揮 發性記憶體鍺存系統的所有邏輯位址及邏輯位址之所有群 (意即’所有邏輯群）的資料。換言之，與不同邏輯群相關 聯之資料可儲存於該寫入緩衝區塊中。請注意，一邏輯群 為具有可等於一元區塊之大小的大小的一群邏輯位址。控 制區塊之第一實例為索引區塊。大體上，索引區塊儲存用 於存取非揮發性記憶體儲存系統内之各個區塊的索引資 訊。索引資訊可（例如）包括關於各種類型之區塊之有效複 I29496.doc 1380303 本的位置的資訊。控制區塊之第三實例為映射區塊。映射 區塊儲存非揮發性記憶體儲存系統中之區塊的映射及指示 是否擦除每一區塊的資訊。舉例而言，映射區塊可儲存已 擦除區塊之一列位址。控制區塊之第四實例為開機啟動 (boot)區塊。開機啟動區塊儲存映射區塊之當前位址。換 έ之’開機啟動區塊儲存對映射區塊之指標。因此，在重 定位映射區塊時’更新儲存於開機啟動區塊中之映射區塊 的當前位址。開機啟動區塊可位於第一可用元區塊中。控 制區塊之第五實例為高速暫存區塊。應瞭解，高速暫存區 塊為資料更新區塊之一形式，其中可以隨機次序及以任何 量之重複來更新邏輯區段。高速暫存區塊藉由寫入命令來 建立，其中所欲邏輯區段不端接或越過一實體頁邊界。由 於非揮發性記憶體儲存系統可能不能夠程式化部分頁，所 以一頁之區段可臨時儲存於高速暫存區塊中β非揮發性記 憶體儲存系統將該頁之區段聚積於高速暫存區塊中，直至 該頁之所有區段填充有來自各種寫入命令之新資料為止。 非揮發性記憶體儲存系統接著在一程式操作中將來自高速 暫存區塊之整個頁（例如，八個區段之新資料）複製至另一 區塊（諸如，更新區塊）。 圖4為記憶體單元之頁的簡化方塊圖。可將每一區塊（諸 如，區塊210至2 13)進一步分成記憶體單元之頁。結果， 佇列可覆蓋記憶體單兀之一或多個頁。如圖4所示，將每 一區塊210、211、212或213分成八個頁ρ〇至ρ7β或者，在 每一區塊210、211、212或213内可存在16個、32個，或更 129496.doc 14 1380303 多的記憶體單元之頁。為增加非揮發性記憶體儲存系統之 操作並行性，可將兩個或兩個以上區塊内的頁邏輯上鏈接 成元頁。例如，一元頁可由一頁（諸如，ρι)形成由四個 區塊210至213中之每一者形成。一元頁可延展越過非揮發 ' ^生記憶體儲㈣統内之所有平面’或非揮發性記憶體儲存 . 系統可由一或多個不同平面中之一或多個獨立區塊中之一 或多個頁動態地形成元頁。 圖5為記憶體單元之區段的簡化方塊圖。可將一頁進一 步分成一或多個區段。結果，佇列可覆蓋記憶體單元之一 或多個區段。每一頁中之資料量可為整數個一或多個區段 之為料其申母一區段可儲存512個位元組之資料。圖5展 示分成兩個區段502及504之頁50卜每一區段5〇2或5〇4含 有大小可為512個位元組之資料5〇6及與該資料相關聯之附 加項資料505。附加項資料505之大小可為16個位元組且可 儲存（例如）在程式化期間由資料5〇6計算出之Ecc、與該資 • 汁斗相關聯之邏輯位址、已擦除及重新程式化區塊之次數的 計數、控制旗標、操作電壓位準，及與該資料相關聯之其 他資訊。 • 圖6為根據本發明之一實施例的儲存記憶體操作及與記 •憶、體操作相關聯之優先級於仔列中的操作之總體概觀的流 矛王圖。開始於602處’提供-件列，且該仔列經組態以儲 存記憶體操作及與該等記憶體操作相關聯之優先級。回應 於一事件，排程一記憶體操作以用於在004處執行，且在 6〇6處將一優先級指派給該記憶體操作。藉由將一優先級 129496.doc -15 - 1380303 指派給每一記憶體操作，可排程某些記憶體操作以 其他記憶體操作之前執行。可為不同記憶體 ； ,P知派不同 優先級。舉例而言，該等優先級可為兩級高或低優 在另一實例該等優先級可包括下表八 先級 私岍不之多個級 別。1 is a simplified block diagram of one example of a non-volatile memory storage system in accordance with an embodiment of the present invention. A host system (eg, a desktop computer, audio player, digital camera, and other computing device) can write data to a non-volatile § memory storage system 02 or read from a non-volatile memory storage system 102 Take the information. The non-volatile memory storage system 1〇2 can be embedded within the host or can be movably connected to the host. As shown in FIG. 1, the non-volatile memory storage system 102 includes a memory controller 110 in communication with a memory port 8. In general, the memory controller controls the operation of the memory port 8. The memory controller 110 includes a bus bar 124 that interfaces with the system bus 126 via the host interface 1 〇4. The memory controller 11 is further interfaced with the memory 118 via a memory interface 1〇8. Host interface 1〇4, processor 106 (eg, microprocessor, microcontroller, and other processor), memory interface 108, random access memory (rAM) U2, error correction code (ECC) circuit 114, and Read-only memory (ROM) 1 1 6 communicates by means of busbars 1 24 129496.doc 1380303. The ROM 116 can store a storage system firmware including program instructions for controlling the operation of the memory 118. Processor 〇6 is configured to execute program instructions loaded from ROM 116 or from non-volatile memory cell array 122. The storage system firmware can be temporarily loaded into the RAM 丨丨 2, and in addition, the RAM can be used to buffer information transferred between the host and the memory 丨丨 8. Additionally, RAM 112 can be configured to store a bank 131 of memory operations. The ECC circuit 114 can check for errors in the memory controller 110 between the host and the memory 118. If an error is found, the ECC circuit 丨丨4 can correct a plurality of error bits, depending on the ECC algorithm utilized. Memory 118 can include array logic 12A and non-volatile memory cell array 122. The non-volatile memory cell array 122 can include various combinations or a combination of non-volatile memory structures and techniques. Examples of non-volatile memory technologies include flash memory (eg, NAND, NOR, single layer cell (SLC/BIN), multi-level cell (MLC), split bit line n〇r (din〇R), And, high capacitive coupling ratio (HiCR), asymmetric contactless transistor (act) and other flash memory), erasable programmable read only memory (EPROM), electrically erasable programmable read-only memory (EEpR〇M), read-only memory (ROM), one-time programmable memory (〇τρ) and other memory technologies. In addition to the RAM 112, the bank 13 of memory operations can also be stored in the non-volatile memory cell array 122. In addition, array logic 120 interfaces memory controller 11 to non-volatile memory cell array 122 and provides, for example, addressing, data transfer and sensing, and other support to non-volatile memory cell arrays. To support the non-volatile suffix cell array 122, the array logic i 2 can include column decoding 129496.doc 1^80303 thief, row decoder, charge pump, word line voltage generator, page buffer, input/output Buffer 'address buffer and other circuits. Figure 2 is a flow diagram of a general overview of the operation of a memory memory operating in a small row in accordance with an embodiment of the present invention. Starting at 27, a line is provided in a non-volatile memory storage system. The train can include a variety of data structures configured to operate in a memory. Examples of t-material structures include ^ arrays and other data structures. Here, in the embodiment, the plurality of types of memory operations associated with the plurality of types of s. In another embodiment, the queue can store memory operations associated with two or more types of memory operations. For example, the stock store collects two obsolete items for two different block operations. The second-discarded item collection operation is a type or a single type of memory gymnastics. In addition, the queue can store five read-and-slave (serub) operations on five different block operations (the read clean processing operation is a type or early type of memory operation). The array can be stored in a variety of cells in the non-volatile memory storage system. In one embodiment, the queue stores a non-volatile memory unit in the non-volatile memory storage system. In another embodiment, the queue is stored in the non-volatile memory storage system. Access memory. In yet another embodiment, the array is stored in both the random access memory and the non-volatile memory cell array in the non-volatile memory storage system. First, recall the gymnastics as a guide to the non-volatile memory storage system to execute the order. In one embodiment, memory operations can be associated with maintenance of a non-volatile memory storage system. These memory operations can be referred to as housekeeping 129496.doc 1380303 (house keeping) operations. Housekeeping operations include t-receiving operations that are not transmitted to the host or are not requested by the host. Thus, for example, housekeeping operations may include all memory operations other than erase operations, write operations, and read operations that are requested or initiated by the host. Examples of housekeeping operations include waste collection, wear leveling, read cleanup, write buffer block write, write buffer block compression, program error recovery, write abort recovery, and other memory operations. Please note that in the waste project collection operation, the valid data from the -block is copied to another block. After transmitting the valid data, the original block is erased to provide storage capacity. The blocks of the data in the memory are periodically discarded (ie, D, compressed or merged) to reproduce the storage capacity of the memory. Periodically relocating the logical data stored in the non-volatile memory cell array in the wear and tear, so that the data migrates in the entire physical space of the non-volatile memory cell array, and all the blocks are uniformly abrasion. It should also be understood that when using a non-volatile J. 5 memory system, the threshold of the memory unit can be reduced by a marginal threshold. This produces a soft error that is not easily measurable. The array of non-volatile memory cells can be continuously cleaned to maintain the memory cells within their limits. In the read purge processing operation, the test memory is judged by itself, whether or not its margin is maintained' and if not, it is overwritten with an appropriate margin. It has been 7L early. In the write buffer block clear, the bead material stored in the write buffer ghost is copied to the other block. The valid data stored in the write buffer block is compressed in the write buffer block compression. It should also be understood that writing data to one of the non-volatile memory cell arrays (for example, a zone, & write operation may fail. In the program error recovery 129496.doc 1380303, the failure will be written The valid data stored in this area before the operation is argon to another position. Similarly, if the power loss occurs during the write operation to the area of the non-volatile memory cell array J, the write abort is resumed. The valid data written by the lieutenant before the power loss is copied to the other location. At 272, the 'storage-memory operation is performed to make it respond to an event. One event in the non-volatile memory storage system An event can be triggered. An event can be a detection of a state in a non-volatile memory storage system, a conditional satisfaction or a criterion. Alternatively, an event can be performed to perform a memory operation. The receiving of the command includes an example of receiving data from the host that triggers the closing of an updated block, detecting a stylized failure in an updated block, and detecting that the trigger is written in a block. The write abort condition of the recovery, the criterion for satisfying the renewed system block satisfies the criteria for the wear uniformity of the block, and satisfies the trigger control block (for example, the write buffer block, the mapping block, the index area) The criteria for compression of blocks, write buffer block index blocks, and other control blocks (eg, the amount of space remaining in the control block), and other events. Events that trigger memory operations and non-volatile memory Depending on the state of the volume storage system, the memory operations can be scheduled for immediate execution or scheduled for execution at a later time. For example, if the non-volatile memory storage system is currently writing data, The non-volatile memory storage system can be scheduled to perform memory operations for execution after data is written. In another example, if the non-volatile memory storage system is not busy, scheduled reception At the same time, the memory operation is performed immediately. 129496.doc At the same time, the memory operation memory operation is stored in the memory list. The file can be placed at 274, and the record is ^* Λ > 丨Can be stored For a detailed explanation of the various memories in the non-volatile memory blocking system, for example, in the case of m, the 伫: 跨 跨 跨 跨 跨 跨 跨 跨 跨 跨 跨 跨 跨In the non-volatile memory cell array, the second::: volatile memory storage system will not lose the storage = J. The hidden body works. In the initialization of non-volatile memory two will store non-volatile memory The system is set to an initial state. In the non-issue memory storage system is separated from the host and then reconnected to the host 'or in the non-volatile memory storage system receives a reset from the host' in the power cycle In this case, the initialization of the non-volatile memory storage system can occur. Figure 3 is a simplified block diagram of the organization of the memory cell array into a plane. As described above, the column can be stored in a non-volatile memory storage system. Xi Xia "in the body of the body. 4 Note that _ or multiple memory cell arrays can be divided into multiple planes or sub-arrays. In the example of Fig. 3, the memory cell array is divided into four planes 202 to 2〇5. Other numbers of planes (such as '2, 4, 8, 16 or more') may be present in the _non-volatile memory storage system. Each plane 202, 2〇3, 2〇4 or 2〇5 can be divided into blocks of memory cells, such as blocks 2 10 to 2 13 and 220 located in respective planes 2〇2 to 2〇5. To 223. A block of memory cells is the smallest number of memory cells that can be physically erased together. To increase parallelism, blocks can be manipulated in larger metablock units, where blocks from each plane 2〇2, 2〇3, 204, or 205 are logically linked together to form a meta-region 129496 .doc 1380303 block. For example, four blocks 210 through 213 can be logically linked together to form a unitary block. Moreover, the blocks used to form the metablocks may come from various locations within their respective planes, such as planes 202 through 205. For example, four blocks 220 through 223 from respective locations within respective planes 202 through 205 can be logically linked together to form another metablock. The unary block can extend across all four logical planes 202-205 within the non-volatile memory storage system, or the non-volatile memory storage system can be dynamically formed from one or more of the one or more different planes Metablock. In an embodiment, the queue is stored in one or more blocks. For example, the queue can be stored in a control block (such as a write buffer block). The write buffer block is maintained in a non-volatile memory cell array. In general, the write buffer block buffers the received data in a non-volatile memory storage system. The write buffer block acts as a temporary buffer 'because the data written to the write buffer block is later copied to another block. The write buffer block can span multiple logical addresses. For example, the write buffer block can span the entire logical address space. By spanning the entire logical address space, the write buffer block can store all of the logical addresses and logical addresses that will be written to the non-volatile memory cache system (ie, all logical groups) )data of. In other words, data associated with different logical groups can be stored in the write buffer block. Note that a logical group is a group of logical addresses having a size equal to the size of a unitary block. The first instance of the control block is an index block. In general, the index block stores index information for accessing various blocks within the non-volatile memory storage system. The index information may, for example, include information about the location of the effective complex I29496.doc 1380303 of the various types of blocks. The third instance of the control block is a mapped block. The mapping block stores the mapping of the blocks in the non-volatile memory storage system and indicates whether to erase the information of each block. For example, a mapped block can store a column address of an erased block. The fourth example of the control block is the boot block. The boot device block stores the current address of the mapped block. The 'boot' block is stored in the boot block to store the index of the mapped block. Therefore, the current address of the mapped block stored in the boot-up block is updated when the mapped block is relocated. The bootable boot block can be located in the first available metablock. The fifth example of a control block is a scratch pad block. It should be understood that the scratch pad block is in the form of one of the data update blocks in which the logical segments can be updated in random order and in any amount of repetition. The scratch pad block is created by a write command in which the desired logical segment is not terminated or crossed over a physical page boundary. Since the non-volatile memory storage system may not be able to program part of the page, a section of one page may be temporarily stored in the scratch pad block. The β non-volatile memory storage system accumulates the section of the page on the high speed. In the memory block, until all the sections of the page are filled with new data from various write commands. The non-volatile memory storage system then copies the entire page (e.g., new data for eight segments) from the high speed temporary storage block to another block (e.g., update block) in a program operation. 4 is a simplified block diagram of a page of a memory cell. Each block (e.g., blocks 210 through 2 13) can be further divided into pages of memory cells. As a result, the queue can cover one or more pages of the memory unit. As shown in FIG. 4, each block 210, 211, 212 or 213 is divided into eight pages ρ 到 ρ 7 β or there may be 16 or 32 in each block 210, 211, 212 or 213, or More 129496.doc 14 1380303 pages of more memory cells. To increase the operational parallelism of a non-volatile memory storage system, pages within two or more blocks can be logically linked into a metapage. For example, a unitary page may be formed by one page (such as ρι) formed by each of the four blocks 210 to 213. A unitary page can extend over all non-volatile 'storage memory' (four) all planes or non-volatile memory storage within the system. The system can be one or more of one or more independent blocks in one or more different planes. The pages dynamically form a meta page. Figure 5 is a simplified block diagram of a section of a memory cell. The page can be further divided into one or more segments. As a result, the queue can cover one or more segments of the memory unit. The amount of data in each page can be an integer number of one or more segments. The data of one segment of the mother can store 512 bytes. Figure 5 shows a page 50 divided into two sections 502 and 504. Each section 5〇2 or 5〇4 contains information of a size of 512 bytes. 5〇6 and additional information associated with the data. 505. The additional item information 505 can be 16 bytes in size and can store, for example, the Ecc calculated from the data 5〇6 during the stylization, the logical address associated with the resource bucket, the erased and The count of the number of reprogrammed blocks, the control flag, the operating voltage level, and other information associated with the data. Figure 6 is a flow diagram of a memory memory operation and a general overview of the operations associated with the memory and body operations in the queue, in accordance with an embodiment of the present invention. Beginning at 602' provides a list of items, and the train is configured to store memory operations and priorities associated with the operations of the memories. In response to an event, a schedule-memory operation is performed for execution at 004, and a priority is assigned to the memory operation at 6〇6. By assigning a priority 129496.doc -15 - 1380303 to each memory operation, certain memory operations can be scheduled to be executed before other memory operations. Can be different memory; P know different priorities. For example, the priorities may be two levels of high or low. In another instance, the priorities may include the following table: eight levels of privilege.
'05' 清除寫入緩衝區塊項„ ____ 、—操作或彳執行。 Ό6" • _體操作。 具有優先級”05·，之所有經排 ^—_ 〇月’主·芑，在表Α中，且古ν 記憶體操作將經排程以用^優先級數字（例如’、"）之 嘗)之具有高優先級數字（例如， 己隱體彳呆作之前執行。 可基於一或多個泉 若非揮發性記憶雜《存計算f先級。舉例而言， (_且存在七個位元 ：:!：之錯誤校正碼 正錯誤之記憶體操作： ：：:…優先級指派給校 …、、而，若存在四個位元之錯誤則 129496.doc • 16 * 丄獨303 可先級指派給校正錯誤之記憶體操作。在一實施例 化:基於記憶體操作之類細如，磨損均勻化、讀取 :=、廢棄項目收集及其他類型之記憶體操作)來將 優先則曰派給記憶體操作。換言之，優先級可表示成 優先級=/(記憶體操作之類型） 其中優先級為記憶體操作之類型的函數。舉例而、一磨 損均勻化記憶體操作可指派有或指^成―低優纽。在另'05' Clear write buffer block item „ ____ , — Operation or 彳 Execution. Ό6" • _ Body operation. With priority “05·, all the rows ^__ 〇月' main 芑, in the table Α Medium, and the ancient ν memory operation will be scheduled to use the priority number (such as ', ") to have a high priority number (for example, the implementation of the hidden body before the execution. Can be based on one or If there are multiple non-volatile memory miscellaneous memories, the calculation is f. For example, (_ and there are seven bits::!: the error correction code is wrong in the memory operation: :::... priority is assigned to School..., and, if there are four bit errors, then 129496.doc • 16 * 303 303 can be assigned to the memory operation of the correction error. In an embodiment: based on the memory operation, such as , wear leveling, reading: =, waste item collection and other types of memory operations) to give priority to memory operations. In other words, priority can be expressed as priority = / (type of memory operation) The priority is a function of the type of memory operation. For example, a mill Loss-homogenized memory operations can be assigned or referred to as "low-key". In another
實施例中’可基於觸發記憶體操作之事件的類型來將優 先級指派給記憶體操作。換言之，優先級可表示成 優先級=/(事件之類型） 其中優先級為觸發記憶體操作之事件的類型之函數。一實 例可包括將一中度優先級指派給由更新區塊中之失敗觸發 的記憶體操作。另一方面’可向由寫入中止復原觸發之記 憶體操作m優先級。在又—實施例中優先級可基 於記憶體操作之類型與觸發記憶體操作之事件之類型的組 合。換言之，優先級可表示成 優先級=/(記憶體操作之類型，事件之類型） 其中優先級為記憶體操作之類型及觸發記憶體操作之事件 之類型的函敫。 在將優先級指派給記憶體操作後，在608處將記憶體操 作及優先級儲存於佇列中。此處，該佇列可包括用於記憶 體操作之項、與記憶體操作相關聯之優先級，及與記憶體 操作相關聯之其他資訊，諸如，區塊數目、區段位置、頁 129496.doc 1360303 位置、愈· , 數、一區塊内之特定區段，及其他資訊。 二，看圖6,接著在610處執行記憶體操作。、應瞭解可 :全I:執行記憶體操作，因為(例如)未分配足夠時間以 :。在體:作。因此’可使記憶體操作之執行延 列中。執&例中’如⑴處所示，執行進程可儲存於仔 …進程指示已完成之記憶體操作的量。執行進程 二^己憶體操作之執行的進度有關的多種資訊。此資訊 塊1執行之點、狀態或階段。舉例而言’所複製之區 或區段的數目，在執行可^目至預定級（例如， 窃體升級之筮_、筮 第-或第三級)時記憶體操作之各個級 $ X ’及其他資訊。根據儲存於仔列中之執行進程，可 部分地執行記憶體操作。在稍後時間，即使在記憶體操作 之不同階段的執行之間發生功率循環，亦可在完成之 繼續記憶體操作之執行。 圖7為根據本發明之一實施例的自仵列讀取記憶體操作 之操作之總體概觀的流程圖。開始於7〇2處，提供叶 列。如上所述，經排程以待執行之記憶體操作及其相關聯 之優先級及/或執行進程儲存於該❹心在·處自該 仵列讀取記憶體操作。在初始化非揮發性記憶體儲存系統 時’可自該仔列讀取非揮發性記憶體儲存系統。在非揮於 性記憶體系統不忙於執行其他記憶體操作時，亦可自奸 列讀取非揮發性記憶體儲存系統。舉例而言，主機允許用丁 固定量之時間（意即’-逾時週期）來執行—寫人操作。舉 例而言，安全數位協定將料間量限於250毫秒。執行^ 129496.doc •18- 入操作之時間量可小於該逾時週期。此過剩之時間量（意 即，逾時週期與執行寫入操作之時間量之間的差）可由= 揮發性記憶體系統用於執行儲存於該佇列中之記憶體操 除記憶體操作外’在708處自該佇列讀取與記憶體操作 相關聯之優先級。在710處，亦可自該作列讀取與記憶體 操作相關聯之執行進程。在712處，接著排程一特定言:憶 體操作以用於執行。在一實施例中，可基於優先級來排程 母-記憶體操作以用於執行。視執行進程而定’記憶體操 作之執订可為自較早時間開始之執行的再繼續。舉例而 έ ’在-實施例中，執行進程經組態以定義一執行點。該 執行點為記憶體操作之前—執行結束時。可自該執行點開 始執行記憶體操作。換言之，可自該執行點開始再繼續記 憶體操作之執行。可部分地執行或完全地執行記憶體操 作。若部分地執行記憶體操作，則將執行進程儲存於仔列 中，使得在稱後時間可再繼續記憶體 若已完全地執行記憶體操作，則可自仔列移除:刪：二 體操作。接著可根據優先級排程來自仵列之下—記憶體操 作以用於執行。 、 雖然已為達成理解之清楚的目的而料細地描述前述實 施例，但該等實施例不限於所提供之細節。#在實施該等 實施例之許多替代方式。^ ^ 戈方式目此，所揭不之實施例將被視為 說=性且非限制性的，且該等實施例不限於本文所提供之 細節’而是可在所附申請專利範圍之料及等效物内進行 129496.doc 修改。在申請專利範圍t， 除非令4專利範圍尹明確地規 【:=操作_次序。 圖1為根據本發明之—實施例的非揮發性記憶體儲存系 統之一實例的簡化方塊圖。 圖2為根據本發明之—實施例的儲存記憶體操作於 中之操作的總體概觀之流程圖。 圖3為5己憶體單疋陣列成為平面之組織的簡化方塊圖。 圖4為記憶體單元之頁的簡化方塊圖。 圖5為記憶體單元之區段的簡化方塊圖。 圖6為根據本發明之一實施例的儲存記憶體操作及與記 憶體操作相關聯之優先級於佇列中的操作之總體概觀的流 程圖。 圖7為根據本發明之一實施例的自佇列讀取記憶體操作 之操作之總體概觀的流程圖。 【主要元件符號說明】 102 非揮發性記憶體儲存系統 104 主機介面 106 處理器 108 記憶體介面 110 記憶體控制器 112 隨機存取記憶體（RAM) 114 錯誤校正碼（ECC)電路 116 唯讀記憶體（ROM) 129496.doc .20. 1380303In an embodiment, the priority may be assigned to a memory operation based on the type of event that triggered the memory operation. In other words, the priority can be expressed as a priority = / (type of event) where the priority is a function of the type of event that triggers the memory operation. An example may include assigning a medium priority to a memory operation triggered by a failure in an update block. On the other hand, it is possible to operate the m priority to the memory that is triggered by the write abort recovery. In still another embodiment, the priority may be based on a combination of the type of memory operation and the type of event that triggered the memory operation. In other words, the priority can be expressed as priority = / (type of memory operation, type of event) where priority is the type of memory operation and the type of event that triggers the operation of the memory. After the priority is assigned to the memory operation, the memory gymnastics is prioritized and stored in the queue at 608. Here, the queue may include items for memory operations, priorities associated with memory operations, and other information associated with memory operations, such as number of blocks, sector locations, page 129496. Doc 1360303 Location, number, number, specific section within a block, and other information. Second, look at Figure 6, and then perform a memory operation at 610. It should be understood that: All I: Perform memory operations because, for example, no sufficient time is allocated to :. In the body: doing. Therefore, the execution of the memory operation can be extended. In the & example, as shown at (1), the execution process can be stored in the amount of memory operations that the process indicates to have completed. Execution process A variety of information about the progress of the execution of the operation. This information is the point, state or phase of block 1 execution. For example, the number of regions or segments that are copied may be at various levels of memory operation $ X ' when performing a predetermined level (eg, 窃 _, 筮 first, or third level). And other information. The memory operation can be partially performed according to the execution process stored in the queue. At a later time, even if a power cycle occurs between executions of different stages of the memory operation, the execution of the memory operation can be continued upon completion. Figure 7 is a flow diagram of a general overview of the operation of a self-aligned read memory operation in accordance with one embodiment of the present invention. Start at 7〇2 and provide a leaf column. As described above, the memory operation to be executed by the scheduling and its associated priority and/or execution process are stored at the heart of the memory from which the memory is read. The non-volatile memory storage system can be read from the queue when the non-volatile memory storage system is initialized. When the non-volatile memory system is not busy performing other memory operations, it can also read the non-volatile memory storage system. For example, the host allows a write-to-write operation to be performed for a fixed amount of time (i.e., '-timeout period). For example, a secure digital agreement limits the amount of material to 250 milliseconds. Execution ^ 129496.doc • 18- The amount of time for the incoming operation can be less than the timeout period. The excess amount of time (ie, the difference between the timeout period and the amount of time the write operation is performed) can be used by the volatile memory system to perform memory gymnastics stored in the queue in addition to memory operations. The priority associated with the memory operation is read from the queue at 708. At 710, the execution process associated with the memory operation can also be read from the queue. At 712, a specific statement is then scheduled: the memory operation is performed for execution. In an embodiment, the mother-memory operation can be scheduled for execution based on priority. Depending on the progress of the process, the memory of the gymnastics can be resumed from the beginning of the earlier time. By way of example, in the embodiment, the execution process is configured to define an execution point. This execution point is before the memory operation—at the end of execution. The memory operation can be performed from this execution point. In other words, the execution of the memory operation can be resumed from the point of execution. The memory gymnastics can be performed partially or completely. If the memory operation is partially performed, the execution process is stored in the queue so that the memory can be resumed after the time is called. If the memory operation has been completely performed, it can be removed from the queue: delete: two-body operation . It can then be scheduled for execution based on priority scheduling from below the queue. Although the foregoing embodiments have been described in detail for purposes of clarity of understanding, the embodiments are not limited to the details provided. #Many alternatives to implementing these embodiments. ^^ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The equivalent of 129496.doc is modified. In the scope of patent application t, unless the scope of the patent 4 is clearly defined [: = operation _ order. 1 is a simplified block diagram of one example of a non-volatile memory storage system in accordance with an embodiment of the present invention. 2 is a flow diagram of a general overview of operations in which memory memory operates in accordance with an embodiment of the present invention. Figure 3 is a simplified block diagram of a tissue in which a single-resonance single-arc array is planar. 4 is a simplified block diagram of a page of a memory cell. Figure 5 is a simplified block diagram of a section of a memory cell. 6 is a flow diagram of a general overview of memory memory operations and operations associated with memory cell operations in a queue, in accordance with an embodiment of the present invention. Figure 7 is a flow diagram of a general overview of the operation of a self-aligned read memory operation in accordance with one embodiment of the present invention. [Main component symbol description] 102 Non-volatile memory storage system 104 Host interface 106 Processor 108 Memory interface 110 Memory controller 112 Random access memory (RAM) 114 Error correction code (ECC) circuit 116 Read-only memory Body (ROM) 129496.doc .20. 1380303
118 記憶體 120 P車列邏輯 122 非揮發性記憶體單元陣列 124 匯流排 126 系統匯流排 130 仔列 131 佇列 202 平面 203 平面 204 平面 205 平面 210 區塊 211 區塊 212 區塊 213 區塊 220 區塊 221 區塊 222 區塊 223 區塊 501 頁 502 區段 504 區段 505 附加項資料 506 資料P0頁 -21 - 129496.doc 1380303 PI P2 P3 P4 P5 P6 P7 頁 頁 頁 頁 頁 頁 頁118 Memory 120 P Train Logic 122 Non-volatile Memory Cell Array 124 Bus Bar 126 System Bus 130 Triangulation 131 伫 Column 202 Plane 203 Plane 204 Plane 205 Plane 210 Block 211 Block 212 Block 213 Block 220 Block 221 Block 222 Block 223 Block 501 Page 502 Section 504 Section 505 Additional Information 506 Data P0 Page-21 - 129496.doc 1380303 PI P2 P3 P4 P5 P6 P7 Page Page Page Page Page Page
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