TWI822516B - Method and computer program product and apparatus for executing host write commands - Google Patents

Abstract

The invention is related to a method, a computer program product and an apparatus for executing host write commands. The method, performed by a processing unit, includes: providing a sequential write-command queue, a random write-command queue and a mark queue; receiving a host write command from a host side; and pushing a record into the mark queue, and pushing the host write command into the sequential write-command queue or the random write-command queue according to a length of the first logical address range carried in the host write command when detecting that a first logical address range carried in the host write command conflicts with a second logical address range carried in at least one sequential write command and/or a third logical address range carried in at least one random write command. The record indicates that the conflicted sequential write command(s) and/or the conflicted random write command(s) require to be processed in advance. With the above method, the data write performance would be improved without the occurrence of dirty writes.

Description

Methods and computer program products and devices for executing host write commands

The present invention relates to a storage device, and in particular, to a method, computer program product and device for executing a host write command.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The host side can provide any address to access the NOR flash memory on the address pin and obtain the data stored at that address from the data pin of the NOR flash memory in a timely manner. material. On the contrary, NAND flash memory does not have random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the host needs to write a sequence of Bytes values into the NAND flash memory to define the type of request command (Command) (for example, read, write, discard, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory).

However, in Cache Mode, data to be written sequentially or randomly can be temporarily stored in the random access memory in the flash memory controller for a period of time until the appropriate time is reached and then written to the flash memory module. However, the time and length of writing temporary data to the flash memory module will affect the overall system performance. Therefore, the present invention provides a method, computer program product and device for executing a host write command.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

This specification relates to a method for executing host write commands, which is executed by a processing unit and includes: providing a sequential write command queue, a random write command queue, and a label queue; receiving a host write command from the host; and when detecting It is detected that the first logical address range carried in the host write command conflicts with the second logical address range carried in at least one sequential write command and/or the third logical address range carried in at least one random write command. When the record is pushed to the mark queue, and the host write command is pushed into the sequential write command queue or the random write command queue according to the length of the first logical address interval carried by the host write command. , so that when the conditions are met, based on the content of this record, the second logical address range indicated by the conflicting sequence write command and/or the third logical address interval indicated by the conflicting random write command can be written earlier than the host write command. User data in the logical address range to the flash memory module.

The sequential write command queue stores multiple sequential write commands, and the random write command queue stores multiple random write commands. This record indicates that conflicting sequential write commands and/or conflicting random write commands require more time than the host writes. Information that input commands are processed with priority.

This manual also relates to a computer program product, including program code. When the processing unit executes the program code, the method of executing the host write command as described above is implemented.

This specification also relates to a device for executing host commands, including: a host interface; a random access memory; and a processing unit. The random access memory allocates space for the sequential write command queue, the random write command queue, and the label queue. The processing unit is configured to receive a host write command from the host through the host interface; and when detecting a first logical address range carried in the host write command and at least one second logical bit carried in the sequential write command When the address range and/or the third logical address range carried in at least one random write command conflict, the record is pushed to the mark queue, and the record is pushed according to the length of the first logical address range carried in the host write command. The host write command pushes the sequential write command queue or the random write command queue, so that when the conditions are met, based on the content of the record, the conflicting sequential write command can be written earlier than the host write command. The user information of the logical address range and/or the third logical address range indicated by the conflicting random write command Supplied to the flash memory module.

One of the advantages of the above embodiment is that through the above method, data writing performance can be improved without dirty writing occurring.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

10: Electronic devices

110: Host side

130:Flash controller

131:Host interface

132:Bus

134: Processing unit

135,135#0~135#7: Search engine

136: Random access memory

138: Direct Memory Access Controller

139:Flash memory interface

150:Flash memory module

151:Interface

153#0~153#15: NAND flash memory unit

CH#0~CH#3: Channel

CE#0~CE#3: enable signal

310: Sequentially write command queue

330: Random write command queue

610:Command scheduling module

630: Data writing module

650: Mark queue

S710~S760: Method steps

S810~S850: Method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a random update command queue and a sequential update command queue according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of an initial enqueuing result according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of an intermediate enqueuing result according to an embodiment of the present invention.

FIG. 6 is a block diagram of a firmware conversion layer according to an embodiment of the present invention.

FIG. 7 is a flow chart of a method for processing a host write command according to an embodiment of the present invention.

FIG. 8 is a flow chart of a data writing method of a host write command according to an embodiment of the present invention.

9 to 13 are schematic diagrams of intermediate enqueuing results according to embodiments of the present invention.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate a priority, precedence relationship, or a single element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may also be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, digital video cameras, smart TVs, smart refrigerators, and automotive electronic systems (Automotive Electronics Systems). The host interface (Host Interface) 137 between the host 110 and the flash controller 130 can be a Universal Serial Bus (USB), an advanced technology attachment (ATA), or a serial advanced technology attachment (ATA). Communication protocols such as SATA), peripheral component interconnect express (PCI-E), Universal Flash Storage UFS, and Embedded Multi-Media Card eMMC communicate with each other. The flash interface (Flash Interface) 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other using a double data rate (Double Data Rate DDR) communication protocol, such as Open NAND Flash (Open NAND Flash Interface ONFI), Double Data Rate DDR. rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware instructions, the functions described later are provided. The processing unit 134 receives host commands through the host interface 131, such as a read command (Read Command), a write command (Write Command), and a discard command (Discard command). Command), erase command (Erase Command), etc., generate a host data-update command (Host Data-update Command) according to the type of the host command and the parameters carried therein, schedule and execute these commands. The flash memory controller 130 also includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, is used to configure space as a data buffer (Data Buffer) to store user data (also called host data) read from the host 110 and about to be written to the flash memory module 150. and user data read from the flash memory module 150 and output to the host 110 . The random access memory 136 can also store data needed in the execution process, such as variables, data tables, host-to-flash/H2F table, flash-to-host comparison table (Flash-to-Host /F2H Table), queue, etc. The flash memory interface 139 includes a NAND flash memory controller (NAND Flash Controller NFC), which provides functions required for accessing the flash memory module 150, such as command sequencer (Command Sequencer), low density parity check (Low Density Parity Check LDPC), etc.

The flash memory controller 130 can be configured with a bus architecture (Bus Architecture) 132 for coupling components to each other to transmit data, addresses, control signals, etc. These components include the host interface 131, the processing unit 134, the RAM 136, Direct Memory Access (DMA) controller 138, flash memory interface 139, etc. The DMA controller 138 can migrate data between components through the bus architecture 132 according to the instructions of the processing unit 134, for example, move the data from a specific data buffer (Data Buffer) in the host interface 131 or the flash memory interface 139 to the RAM 136. At a specific address, the data at a specific address in the RAM 136 is moved to a specific data register in the host interface 131 or the flash memory interface 139, etc.

The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (GB) or even several trillion bytes (Terabytes, TB). Used to store large amounts of user data, such as high-resolution images, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array can be configured as single-level cells (Single Level Cells, SLCs) and multi-level cells (Multiple Level Cells, MLCs). (Triple Level Cells, TLCs), Quad-Level Cells QLCs, or any combination of the above. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and reads user data from a specified address (source address) in the flash memory module 150. The flash memory interface 139 uses several electronic signals to coordinate the transmission of data and commands between the flash memory controller 130 and the flash memory module 150, including data lines (Data Line), clock signals (Clock Signal) and control signals (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory units, for example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11. , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in a parallel manner, or write user data to the enabled NAND flash memory unit.

In some embodiments, the flash memory controller 130 can set up a dedicated search engine 135, including digital circuits such as registers, comparators, output logic, etc., for driving the processing unit 134 to determine the logical address range of a host write command. Does it conflict with the logical address range recorded in the sequential write command queue 310 or the random write command queue 330 (or or partially overlap). Since the comparison of logical address ranges requires a large amount of computing time, the processing unit 134 can leave to perform other operations after setting the logical address range of a host write command to the input register of the search engine 135 . After a preset period of time, the processing unit 134 can read the value of the output register of the search engine 135 to determine whether the search is completed, and to determine whether the input logical address range is consistent with the sequential write command queue 310 or the random write command. The logical address ranges recorded in the queue 330 conflict, and the nodes in the sequential write command queue 310 or the random write command queue 330 conflict. In other embodiments, the comparison of multiple logical address intervals can be implemented using a search program code, and when the processing unit 134 loads and executes the search program code, it completes the above-mentioned determination and outputs the search results.

Referring to Figure 3, the RAM 136 configures space for a Sequential-write Command Queue (SCQ) 310, which is used to store sequential host write commands sent by the host end 110 according to the time sequence when they arrive at the flash memory controller 130, for example A host data update command with a logical block address (LBA Length) greater than 1. The RAM 136 also configures space for a Random-write Command Queue (RCQ) 330, which is used to store random host write commands sent by the host end 110 according to the time sequence when they arrive at the flash memory controller 130. For example, the LBA length is equal to 1 host write command. Either the sequential write command queue 310 or the random write command queue 330 may store hundreds or thousands of host write commands. The sequential write command queue 310 and the random write command queue 330 can be cyclic queues (Cyclical Queue), and the basic principle of their operation is to add a host write command from the end position (such as the position indicated by the indicator T) ( may be called enqueuing), and the host write command is moved out from the starting position (such as the position indicated by pointer H) (which may be called dequeuing). In other words, the first command added to the queue will also be the first to be removed and processed, complying with the First-In First-Out (FIFO) principle.

For example, when the processing unit 134 executes the program code of the Firmware Translation Layer (FTL), it completes the enqueuing of the host write command as follows: First, Eight host write commands are received sequentially from the host side 110 through the host interface 131: W0={LBA#0~499,D0}; W1={LBA#1000~1499,D1}; W2={LBA#2000~ 2499,D2}; W3={LBA#3000~3499,D3}; W4={LBA#500,D4}; W5={LBA#1500,D5}; W6={LBA#2500,D6}; W7={ LBA#3500,D7}. The host write command W0 instructs the writing of data D0 at logical addresses LBA#0~499, the host write command W1 instructs the writing of data D1 at logical addresses LBA#1000~1499, and the host write command W2 instructs the writing of logical bits Data D2 at address LBA#2000~2499, host write command W3 instructs to write data D3 at logical address LBA#3000~3499, host write command W4 instructs data D4 at logical address LBA#500 to be written, host write The input command W5 instructs the writing of data D5 at logical address LBA#1500, the host write command W6 instructs the writing of data D6 at logical address LBA#2500, and the host write command W7 instructs the writing of data at logical address LBA#3500. D7. Referring to the schematic diagram of the enqueuing result in Figure 4, FTL then pushes the host write commands W0 to W3 (which can be called sequential write commands) into the sequential write command queue 310 according to the LBA length of the data, and writes the host write commands W4 to W7 (which may be referred to as random write commands) push the random write command queue 330 .

In order to improve the data writing performance of the flash memory module 150, the flash memory controller 130 may use specific policies to process sequential write commands and random write commands. However, this may cause the actual writing order of the data in the host write command to be different from the order issued by the host, thus causing a dirty write (Dirty Write) situation. For example, following the example shown in FIG. 4 , FTL receives the host write command W8={LBA#100,D8} through the host interface 131, instructing to write the data D8 at the logical address LBA#100. The enqueuing result of the host write command W8 is shown in Figure 5. Assume that the flash memory controller 130 adopts the Random-write First principle to remove and process the host write commands in the sequential write command queue 310 and the random write command queue 330: that is, the flash memory controller After the processor 130 first executes the host write commands W4~W8, it then executes the host write commands W0~W3. Because the host write command W0 is executed later than the host write command W8, the logic stored in the flash memory module 150 is The data at edit address LBA#100 is D0, which is not the data D8 expected by the host 110, and a dirty write occurs.

Referring to Figure 6, in order to improve the data writing performance without dirty writing, the embodiment of the present invention proposes to set up an independently executed command scheduling module 610 and a data writing module 630 in the FTL, and in the RAM 136 Configure space to store Mark Queue (Mark Queue) 650.

The command scheduling module 610 includes program code for detecting the logical address range (which may be referred to as the third host write command) of each host write command received from the host 110 through the host interface 131 when executed by the processing unit 134 . a logical address interval) and at least one logical address interval (which may be called a second logical address interval) carried in the sequential write command in the sequential write command queue 310 and/or a random write command queue The logical address range (which may be called the third logical address range) carried in at least one random write command in step 330 conflicts. Once a conflict is found, the command scheduling module 610 pushes a record in the annotation queue 650 to indicate that the conflicting sequential write command and/or the conflicting random write command requires more time than the received host write command. Information that is processed first, and according to the length of the logical address range carried by the host write command, the received host write command is pushed into the sequential write command queue 310 or the random write command queue 330, so that in When certain conditions are met, the logical address range indicated by the conflicting sequence write command and/or the conflicting random write command may be written earlier than the host write command based on the content of this record in the annotation queue 650. The user data in the logical address range is sent to the flash memory module 150 .

The data writing module 630 includes program code for obtaining the conflicting sequential writing command and the previous sequential writing command from the sequential writing command queue 310 according to the content of the record in the annotation queue 650 when executed by the processing unit 134 Enter the logical address interval carried in the command (which may be called the first logical address interval), and/or obtain the conflicting random write command from the random write command queue 330 and the information carried in the previous random write command. a logical address range (which can be called a second logical address range); read the user data of the first logical address range from a specified address (which can be called a first address) of the random access memory 136, and/or from random Access the designated address of the memory 136 (which may be referred to as the second address) to read the user data in the second logical address range; and write the user data in the first logical address range, and/or the second logical address range. The user data in the logical address range is sent to the flash memory module 150 . The data writing module 630 will be triggered when specific conditions are met to complete the actual data writing operation. In addition, in order to make the latency of different host commands as consistent as possible and meet the requirements of the specification, the data writing module 630 can also control the amount of data written to the flash memory module 150 at one time.

The annotation queue 650 can be implemented as a cyclic queue that conforms to the first-in-first-out principle and is used to store multiple records. Each record stores the information that user data associated with all host write commands of a specific node in the sequential write command queue 310 or the random write command queue 330 and its previous nodes needs to be written to the flash memory module 150 first. .

The trigger condition of the data writing module 630 may be: receiving an instruction to enter sleep mode (Sleep Mode), power saving mode (Power Saving Mode) or other similar modes from the host end 110, but has not yet received an instruction from the host end 110. During the instruction to leave sleep mode, power saving mode, or other similar modes; or the number of occupied nodes in the sequential write command queue 310, the random write command queue 330, or the label queue 650 exceeds a specific threshold. The threshold may be set to a specified percentage of the total number of nodes in the sequential write command queue 310, the random write command queue 330, or the label queue 650, for example, may be set to any percentage from 60% to 90%.

Referring to the flow chart of the host write command processing method shown in Figure 7, this method is implemented by the processing unit 134 when loading and executing the command scheduling module 610 to repeatedly receive the host write command from the host end 110, The host write command is pushed into the sequential write command queue 310 or the random write command queue 330 according to the length of the logical address of the data to be written, and the record is pushed into the label queue 650 as appropriate. The details are as follows:

Step S710: Receive a host write command from the host terminal 110 through the host interface 131, including information such as a starting logical address and a length. The starting logical address and length can define a continuous logical address interval. In addition to the host write command, the command scheduling module 610 also receives the write usage indicated by the host write command from the host end 110 through the host interface 131 user data, and drives the DMA controller 138 to store the user data into the specified address in the RAM 136.

Step S720: Determine whether any logical address carried in the host write command conflicts with the logical address recorded in the sequential write command queue 310 or the random write command queue 330. If yes, the process continues to the process of step S730; otherwise, the process continues to the process of step S740. The command scheduling module 610 can drive a dedicated search engine 135, or load and execute search code to complete the determination.

Step S730: Push at least one record to the annotation queue 650. The number of newly queued records is equal to the number of host write commands that conflict with the sequential write command queue 310 and the random write command queue 330 . Each newly added record is associated with a conflicting host write command in the sequential write command queue 310 or the random write command queue 330, and the records are sequentially updated based on the enqueue time of the conflicting host write command. After arriving, they are queued in the annotation queue 650.

Step S740: Determine whether the host write command is a sequential write command based on the length carried in the host write command. For example, if the length is greater than the preset threshold, the host write command is judged to be a sequential write command. The flow continues with the processing of step S750. If the length is equal to or less than the preset threshold, it is determined that the host write command is not a sequential write command (that is, a random write command). The flow continues with the processing of step S760. In some embodiments. The preset threshold can be set to 1.

Step S750: Push the host write command into the sequential write command queue 310. In addition to the sequential write command, the address in the RAM 136 may also be recorded in the enqueuing node for storing the user data to be written by the sequential write command.

Step S760: Push the host write command into the random write command queue 330. In addition to this random write command, the address of the RAM 136 can also be recorded in the enqueuing node for storing the user data to be written by this random write command.

Referring to the flow chart of the data writing method of the host write command shown in FIG. 8 , this method is implemented by the processing unit 134 when loading and executing the data writing module 630 for reference sequence. The host write commands of the write command queue 310 and the random write command queue 330, and the records of the tag queue 650 are used to complete the actual data writing operation. The details are as follows:

Step S810: Determine whether there are any records in the annotation queue 650. If yes, it means that there is already a host write command that needs to be processed with priority, and the process continues with step S820; otherwise, it means that there is no host write command that needs to be processed with priority, and the process continues with step S830.

Step S820: Refer to the content in the annotation queue 650 to obtain the host write command that needs to be processed with priority from the sequential write command queue 310 or the random write command queue 330.

Step S830: Obtain the host write command from the sequential write command queue 310 or the random write command queue 330 according to a specific policy. A specific policy may refer to, for example, sequential write commands first, random write commands first, arrival time first, or other similar scheduling policies.

Step S840: Read the user data corresponding to the obtained host write command from the specified address of the RAM 136 through the DMA controller 138, and drive the flash memory interface 139 to write the user data to the flash memory module 150.

Step S850: Determine whether the flash memory controller 130 still has computing resources to perform subsequent data writing operations. If yes, the process continues to step S810; otherwise, the process ends until the next trigger condition is established. The flash memory controller 130 still has computing resources. For example, the flash memory controller 130 has not received an instruction from the host 110 to instruct the flash memory controller 130 to leave the sleep mode, power saving mode or other similar modes; Operations on higher priority tasks are waiting for execution by the flash memory controller 130 .

The following are more use cases to illustrate the operation of the methods shown in Figures 7 and 8: Continuing the example shown in Figure 4, after receiving the host write command W8 (step S710), the command scheduling module 610 detects The logical address LBA#100 carried in the host write command W8 conflicts with the logical address range LBA#0~499 carried in the host write command W0 in the 0th node of the sequential write command queue 310 ( path "Yes" in step S720), push the record: M0=Q0[0] to the annotation queue 650, where Q0[0] represents the sequential write command queue The 0th node in 310 (step S730), and the host write command W8 is pushed into the random write command queue 330 (step S760). The queue content after execution is shown in Figure 9.

Next, after receiving the host write command W9={LBA#1200~1299,D9} (step S710), the command scheduling module 610 detects the logical address range LBA#1200 carried in the host write command W9. ~1299 conflicts with the logical address interval LBA#1000~1499 carried in the host write command W1 in the first node of the sequential write command queue 310 (the path of "Yes" in step S720), and the record is pushed : M1=Q0[1] to the label queue 650, where Q0[1] represents the 1st node in the sequential write command queue 310 (step S730), and the host write command W8 is pushed into the sequential write command Queue 310 (step S750). The queue content after execution is shown in Figure 10.

Next, after receiving the host write command W10={LBA#2300~2799,D10} (step S710), the command scheduling module 610 detects the logical address range LBA#2300 carried in the host write command W10. ~2799 and the host in the second node of the sequential write command queue 310 write the logical address range LBA#2000~2499 carried in the write command W2 and the host in the second node of the random write command queue 330 The logical address LBA#2500 carried in the write command W6 conflicts (the path of "Yes" in step S720), and the record: M2=Q0[2]+Q1[2] is pushed to the mark queue 650, where Q0[ 2] represents the second node in the sequential write command queue 310, Q1[2] represents the second node in the random write command queue 330 (step S730), and the host write command W10 is pushed into the sequence Write command queue 310 (step S750). The queue content after execution is shown in Figure 11.

Next, assuming that the conditions for triggering the data writing operation are met, the data writing module 630 finds that there is a record in the annotation queue 650 (the "Yes" path in step S810), and writes sequentially according to the preset maximum amount of data to be written. The command queue 310 launches the host write commands W0 and W1, and the data to be written in the host write commands W0 and W1 is the data that needs to be written first as indicated by the top two records M0 and M1 of the queue 650. From The user data D0 and D1 instructed to be written by the host write commands W0 and W1 are sequentially read from the designated location of the RAM 136 (step S820). The data writing module 630 drives the flash memory interface 139 to write sequentially Use data D0 and D1 to the flash memory module 150 (step S840). The queue content after execution is shown in Figure 12.

Next, after receiving the host write command W11={LBA#4000~4499,D11} (step S710), the command scheduling module 610 detects the logical address range LBA#4000 carried in the host write command W11. ~4499 does not conflict with the logical address range or logical address carried in any host write command in the sequential write command queue 310 and the random write command queue 330 (the "No" path in step S720) will The host write command W11 pushes the sequential write command queue 310 (step S750). The queue content after execution is shown in Figure 13.

All or part of the steps in the method of the present invention can be implemented by computer instructions, such as a firmware translation layer (FTL) in a storage device, a driver for a specific hardware, etc. In addition, it can also be implemented in other types of programs. Those with ordinary skill in the art can write the methods of the embodiments of the present invention as computer instructions, which will not be described again for the sake of simplicity. Computer instructions implemented according to the methods of embodiments of the present invention can be stored in appropriate computer-readable media, or placed in a network server accessible through a network (such as the Internet, or other appropriate vehicles).

Computer-readable storage media includes volatile and non-volatile, removable and non-removable media that use any method or technology to store information, such as computer-readable instructions, data structures, program modules, or other material. Computer-readable storage media includes but is not limited to RAM, ROM, EEPROM, flash memory or other memory, CD-ROM, DVD, Blu-ray disk or other optical storage, magnetic card, tape, magnetic disk or other magnetic storage, or other A vehicle that can be used to store information needed and accessed by the command execution system. It should be noted that the computer-readable storage medium can be paper or other appropriate media, which is used to print out the program code so that the program code can be obtained electronically, such as by optically scanning the paper or other media, and then printing the program code when necessary. In this case, it is compiled, interpreted, or otherwise processed by other appropriate methods, and then stored in the computer's memory.

Although the above-described elements are included in Figures 1 to 2, it does not exclude the possibility of In spirit, using more other add-on components has achieved better technical results. In addition, although the flowcharts of Figures 7 to 8 are executed in a specified order, those skilled in the art can modify the order of these steps without violating the spirit of the invention and achieving the same effect. Therefore, The present invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

S710~S760: Method steps

Claims (11)

A method for executing host write commands, executed by a processing unit. The method includes: providing a sequential write command queue, a random write command queue, and a label queue, wherein the sequential write command queue stores a plurality of Sequential write commands, the random write command queue stores a plurality of random write commands; receiving a host write command from the host; when detecting the first logical address range carried in the host write command and When the second logical address interval carried in at least one of the sequential write commands and/or the third logical address interval carried in at least one of the random write commands conflicts, push a record to the annotation queue, and pushing the host write command into the sequential write command queue or the random write command queue according to the length of the first logical address interval carried by the host write command, wherein , the record indicates information that conflicting sequential write commands and/or conflicting random write commands need to be processed prior to the host write command; according to the content of the record in the annotation queue, from all Obtain the second logical address interval carried in the conflicting sequential write command and the previous sequential write command from the sequential write command queue, and/or obtain the second logical address interval from the random write command queue. The third logical address interval carried in the conflicting random write command and the previous random write command; the use of reading the second logical address interval from the second address of the random access memory user data, and/or read user data of the third logical address range from the third address of the random access memory; and write user data of the second logical address range, and/or the user data of the third logical address range to the flash memory module. The method of executing host write commands as described in request item 1 includes: When it is detected that the first logical address range carried in the host write command does not match any of the second logical address range carried in the sequential write command and does not match any of the random writes When the third logical address interval carried in the command conflicts, the host write command is pushed into the sequence according to the length of the first logical address interval carried by the host write command. Write command queue or the random write command queue. The method for executing a host write command as described in request item 1, including: when the length of the first logical address interval carried by the host write command is greater than a threshold, executing the host write command Pushing the sequential write command queue; and when the length of the first logical address interval carried by the host write command is less than or equal to the threshold, pushing the host write command Enter the random write command queue. The method for executing a host write command as described in request item 3, wherein the threshold is set to 1. The method for executing a host write command as described in claim 3 includes: storing the associated user data of the first logical address range carried by the host write command into the random access memory. a first address; and an enqueuing node in the sequential write command queue or the random write command queue records the first address of the random access memory. A computer program product for executing host commands, including program code, wherein when a processing unit executes the program code, the method for executing host write commands described in any one of claims 1 to 5 is implemented. A device for executing host write commands, including: a host interface coupled to the host; a flash memory interface coupled to a flash memory module; a random access memory configured with space for sequential write command queues and random write command queues and a label queue, wherein the sequential write command queue stores a plurality of sequential write commands, and the random write command queue stores a plurality of random write commands; and a processing unit coupled to the random access The memory and the host interface are configured to receive a host write command from the host through the host interface; when detecting the first logical address range carried in the host write command and at least one of the When the second logical address interval carried in the sequential write command and/or the third logical address interval carried in at least one of the random write commands conflicts, push the record to the mark queue, and according to the The length of the first logical address interval carried by the host write command pushes the host write command into the sequential write command queue or the random write command queue, wherein the record Information indicating that conflicting sequential write commands and/or conflicting random write commands need to be processed prior to the host write command; obtaining the conflict from the sequential write command queue based on the content of the record the second logical address interval carried in the sequential write command and the previous sequential write command, and/or obtain the conflicting random write command and the previous random write command from the random write command queue Write the third logical address range carried in the command; read the user data of the second logical address range from the second address of the random access memory, and/or read the user data from the second logical address range. The third address of the random access memory reads the user data of the third logical address range; and drives the flash memory interface to write the user data of the second logical address range, and/or The user data in the third logical address range is transferred to the flash memory module. The device for executing a host write command as described in claim 7, wherein the processing unit is configured to detect that the first logical address range carried in the host write command does not correspond to any of the sequences. When the second logical address interval carried in the write command does not conflict with the third logical address interval carried in any of the random write commands, according to the said host write command carried The length of the first logical address interval pushes the host write command into the sequential write command queue or the random write command queue. The device for executing a host write command as described in claim 7, wherein the processing unit is configured to: when the length of the first logical address interval carried by the host write command is greater than a threshold, The host write command is pushed into the sequential write command queue; and when the length of the first logical address interval carried by the host write command is less than or equal to the threshold, the host write command is The host write command is pushed into the random write command queue. The device for executing a host write command as described in claim 9, wherein the threshold is set to 1. The device for executing a host write command according to claim 9, wherein the processing unit is configured to store the associated user data of the first logical address range carried by the host write command to the the first address of random access memory; and an enqueue node in the sequential write command queue or the random write command queue, recording the first address of the random access memory site.

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