TWI818762B - Method and computer program product and apparatus for scheduling and executing host data-update commands - Google Patents

Abstract

The invention is related to a method, a computer program product and an apparatus for scheduling and executing host data-update commands. The method, performed by a processing unit, includes: generating third host data-update command and labeling the third host data-update command as a first-type of host data-update command according to a type and parameters of a host command for updating data from a host-side; popping out and executing all first host data-update commands of a first queue in response to a third logical address of the third host data-update command being equal to a first logical address in one of the first host data-update commands in the first queue; popping out and executing all first host data-update commands of the first queue and all second host data-update commands of a second queue in response to the third logical address of the third host data-update command being equal to a second logical address in one of the second host data-update commands in the second queue; and pushing the third host data-update command into the first queue. With the aforementioned method, errors of dirty write would be avoided.

Description

Methods and computer program products and devices for scheduling and executing host data update commands

The present invention relates to storage devices, and in particular, to a method, computer program product and device for scheduling and executing host data update commands.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The host side can provide any address to access the NOR flash memory on the address pin and obtain the data stored at that address from the data pin of the NOR flash memory in a timely manner. material. On the contrary, NAND flash memory does not have random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the host needs to write a sequence of Bytes values into the NAND flash memory to define the type of request command (Command) (for example, read, write, discard, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory). However, in order to improve the data update performance of the flash memory module, the execution order of host data update commands may be different from the order of corresponding host commands issued by the host to update data, so dirty writes may occur. The present invention proposes a method, computer program product and device for scheduling and executing host data update commands to avoid dirty writing errors.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

This description relates to a method for scheduling and executing a host data update command, which is executed by a processing unit and includes: generating a third host data update command according to the type and parameters of the host command received from the host for updating data, and marking It is a first type of host data update command; in response to the third logical address in the third host data update command being the same as the first logical address of one of the plurality of first host data update commands in the first queue. situation, launch and execute all the first host data update commands in the first queue; in response to the third logical address being the same as the second logical address of one of the plurality of second host data update commands in the second queue In this case, push out and execute all the first host data update commands in the first queue and all the second host data update commands in the second queue; and push the third host update command into the first queue.

This manual also relates to a computer program product, including program code. When the processing unit executes the program code, the method of scheduling and executing the host data update command as described above is implemented.

This specification also relates to a device for scheduling and executing host data update commands, including: a random access memory configured to configure space for the first queue and the second queue; and a processing unit coupled to the random access memory. The processing unit is configured to generate a third host data update command according to the type and parameters of the host command for updating data received from the host, and mark it as a first type of host data update command; in response to the third host data update command When the third logical address is the same as the first logical address of one of the plurality of first host data update commands in the first queue, launch and execute all the first host data update commands in the first queue. ; In response to the situation that the third logical address is the same as the second logical address of one of the plurality of second host data update commands in the second queue, launch and execute all first host data updates in the first queue command and all second host data update commands in the second queue; and pushing the third host update command into the first queue.

One of the advantages of the above embodiment is that by scheduling and executing the host data update command as described above, it can be avoided that the execution sequence of the host data update command is different from the sequence of the corresponding host command issued by the host for updating data. , and a dirty write error occurs Wrong.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

10: Electronic devices

110: Host side

130:Flash controller

131:Host interface

132:Bus

134: Processing unit

136: Random access memory

138: Direct Memory Access Controller

139:Flash memory interface

150:Flash memory module

151:Interface

153#0~153#15: NAND flash memory unit

CH#0~CH#3: Channel

CE#0~CE#3: enable signal

310: Sequential update command queue

330: Random update command queue

S412~S462: Method steps

S512~S562: Method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a random update command queue and a sequential update command queue according to an embodiment of the present invention.

FIG. 4 is a flow chart of a method for scheduling and executing host data update commands according to an embodiment of the present invention.

FIG. 5 is a flow chart of a method for scheduling and executing host data update commands according to an embodiment of the present invention.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate a priority, precedence relationship, or a single element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may also be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between components may also be similar Interpretation methods, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", etc.

Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, digital video cameras, smart TVs, smart refrigerators, etc. The host interface (Host Interface) 137 between the host 110 and the flash controller 130 can be a Universal Serial Bus (USB), an advanced technology attachment (ATA), or a serial advanced technology attachment (ATA). Communication protocols such as SATA), peripheral component interconnect express (PCI-E), Universal Flash Storage (UFS), and embedded multi-media card (eMMC) communicate with each other. The flash interface (Flash Interface) 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other using a double data rate (Double Data Rate, DDR) communication protocol, such as Open NAND Flash (Open NAND Flash Interface, ONFI), dual Double data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware instructions, the functions described later are provided. The processing unit 134 receives host commands through the host interface 131, such as write command (Write Command), discard command (Discard Command), erase command (Erase Command), etc., and generates a host data update command according to the type of the host command and the parameters carried therein. (Host Data-update Command), schedules and executes these commands. The flash memory controller 130 also includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory. Static Random Access Memory (SRAM) or a combination of the above two is used to configure space as a data buffer to store user data read from the host 110 and about to be written to the flash memory module 150 (also called the host data), and user data read from the flash memory module 150 and about to be output to the host 110 . The random access memory 136 can also store data needed in the execution process, such as variables, data tables, host-to-flash/H2F table, flash-to-host comparison table (Flash-to-Host /F2H Table) etc. The flash memory interface 139 includes a NAND Flash Controller (NFC), which provides functions required to access the flash memory module 150, such as a command sequencer (Command Sequencer) and a low density parity check (LDPC). wait.

The flash memory controller 130 can be configured with a bus architecture (Bus Architecture) 132 for coupling components to each other to transmit data, addresses, control signals, etc. These components include the host interface 131, the processing unit 134, the RAM 136, Direct Memory Access (DMA) controller 138, flash memory interface 139, etc. The DMA controller 138 can migrate data between components through the bus architecture 132 according to the instructions of the processing unit 134, for example, move the data from a specific data buffer (Data Buffer) in the host interface 131 or the flash memory interface 139 to the RAM 136. At a specific address, the data at a specific address in the RAM 136 is moved to a specific data register in the host interface 131 or the flash memory interface 139, etc.

The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (GB) or even several terabytes (TB), for storing a large amount of user data. For example, high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array can be configured as single-level cells (Single Level Cells, SLCs) and multi-level cells (Multiple Level Cells, MLCs). (Triple Level Cells, TLCs), Quad-Level Cells QLCs, or any combination of the above. The processing unit 134 writes user data into the flash memory module 150 through the flash memory interface 139 Specify an address (destination address), and read user data from the specified address (source address) in the flash memory module 150 . The flash memory interface 139 uses several electronic signals to coordinate the transmission of data and commands between the flash memory controller 130 and the flash memory module 150, including data lines (Data Line), clock signals (Clock Signal) and control signals (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory units, for example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11. , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in a parallel manner, or write user data to the enabled NAND flash memory unit.

In order to improve the efficiency of data update, the flash memory controller 130 can separately schedule and execute long and continuous host commands and short and scattered host commands for data update. The flash memory controller 130 generates a host data update command according to the type of the host command and the parameters carried therein, and the host data update command can be expressed as the following data structure: {SN, LA, Len, PA}, where SN represents the sequence number of the host command. , LA represents the starting logical address, Len represents the length of the logical address, and PA represents the starting physical address. The sequence number of the host command may represent the time sequence in which the host command reaches the flash memory controller 130 . The smaller the number, the earlier it reaches the flash memory controller 130 . The logical address may be a logical block address (Logical Block Address, LBA), host page number (Host Page Number), etc. A logical block address can point to 512K bytes of data, and a host page can point to eight Data of continuous logical block addresses (that is, 4K bytes). The physical address may include a channel number, a logical unit number (LUN), a page number, a segment number, or any combination of the above information, allowing the flash memory interface 139 to interpret and perform a series of operations with the flash memory module 150 Signal interaction to complete specific data writing operations. When the physical address is all "0" (that is, the null value NULL), it means that the data update command is generated based on the host discard command or the host erase command. When the physical address can be interpreted by the flash memory interface 139, it means that the data update command is generated according to the host write command. For example, according to the host write command of LBA#100~LBA#115, the host data update command {1,100,16,PA={CH#0,LUN#1,P#0~P#1}} can be generated. The physical address may be assigned by the flash memory controller 130 according to the physical settings of the flash memory module 150 and preset rules. According to the host discard or erase command of LBA#100~LBA#115, the data update command {2,100,16,PA=NULL} can be generated.

Referring to Figure 3, the RAM 136 configures space for a Sequential-update Command Queue (SCQ) 310, which is used to store sequential host data update commands sent by the host 110 according to the time sequence when they arrive at the flash controller 130, such as logical Host data update command with block address length (Logical Block Address, LBA Length) greater than 1. The RAM 136 also configures space for a Random-update Command Queue (RCQ) 330, which is used to store random host data update commands sent by the host 110 according to the time sequence when they arrive at the flash controller 130. For example, the LBA length is equal to 1. Host data update command. Either of the sequential update command queue 310 and the random update command queue 330 can store hundreds or thousands of host data update commands. The sequential update command queue 310 and the random update command queue 330 can be cyclic queues (Cyclical Queue), and the basic principle of their operation is to add a host data update command (which can be called is enqueuing), and the host data update command is moved out from the starting position (such as the position pointed by pointer H) (which can be called dequeuing). In other words, the first command added to the queue will also be the first to be removed and processed, complying with the First-In First-Out (FIFO) principle.

For example, when the processing unit 134 executes the program code of the Firmware Translation Layer (FTL), it completes the generation and enqueuing of the host data update command as follows: First, five commands are received sequentially through the host interface 131 Host write command: W1={LBA#200~215,D1}; W2={LBA#300,D2}: W3={LBA#400~415,D3}: W4={LBA#300~315,D4} :W5={LBA#200,D5}. The host write command W1 instructs the writing of data D1 at logical address LBA#200~215, the host write command W2 instructs the writing of data D2 at logical address LBA#300, and the host write command W3 instructs the writing of logical address LBA The data D3 of #400~415, the host write command W4 instructs to write the data D4 of the logical address LBA#300~315, and the host write command W5 instructs the write of the data D5 of the logical address LBA#200. Then, the host data update commands DU1={1,200,16,PA#1}; DU2={2,300,1,PA#2}; DU3={3,400,16,PA#3 are generated for the host write commands W1 to W5 respectively. }; DU4={4,300,16,PA#4}; DU5={5,200,1,PA#5}. After judging the update type, the host data update commands DU1, DU3, and DU4 (which can be called sequential update commands, Sequential Update Command, SUC) are pushed into the sequential update command queue 310 in sequence, and the host data update commands DU2, DU5 ( A random update command (RUC), which may be called a random update command (RUC), is pushed into the random update command queue 330 .

The host data update command DU2={2,300,1,PA#2} and the host data update command DU4={4,300,16,PA#4} contain the same logical address LBA#300, and DU2 must be executed earlier than DU4 . The host data update command DU1={1,200,16,PA#1} and the host data update command DU5={5,200,1,PA#5} contain the same logical address LBA#200, and DU1 must be executed earlier than DU5 .

In some embodiments, the flash memory controller 130 may adopt a Sequential-update First principle to remove and process the host data update commands in the sequential update command queue 310 and the random update command queue 330 . That is to say, the flash memory controller 130 first executes the host data update commands DU1, DU3, and DU4, and then Execute the host data update commands DU2 and DU5. However, because DU2 is executed later than DU4, the final update result of the logical address LBA#300 is not the result expected by the host end 110 after executing the host data update command DU4, and a dirty write occurs.

In other embodiments, the flash memory controller 130 may adopt a random update (Random-update First) principle to remove and process the host data update commands in the sequential update command queue 310 and the random update command queue 330 . That is to say, the flash memory controller 130 first executes the host data update commands DU2 and DU5, and then executes the host data update commands DU1, DU3, and DU4. However, because DU1 is executed later than DU5, the final update result of the logical address LBA#200 is not the result expected by the host end 110 after executing the host data update command DU5, and a dirty write occurs.

In order to solve the problem of dirty writing caused by the above embodiments, embodiments of the present invention propose a scheduling mechanism for host data update commands. Referring to the method flow chart shown in Figure 4, this method is executed by the processing unit 134 when loading and executing FTL, continuously receiving host commands for data update from the host terminal 110, and generating host commands according to the type of the host command and the parameters carried therein. data update commands, and use the sequential update command queue 310 and the random update command queue 330 to schedule these host data update commands, and use preset rules to execute these host data update commands. The details are as follows:

Step S412: Determine whether a host command for data update is received from the host 110 through the host interface 131, such as a host write, discard, erase command, etc. If yes, the process continues to the process of step S422; otherwise, the process continues to the process of step S414.

Step S414: If there is currently no pending data update host command, wait for a preset period of time.

Step S422: Obtain the content of the host command for data update.

Step S424: Generate a host data update command according to the type of the host command and the parameters carried therein, and mark the host data update command as a sequential update command (SUC) or a random update command (RUC) according to the logical address length carried in the host command. ). The data structure and generation details of the host data update command, and whether it is marked as SUC or For the details of RUC's judgment, please refer to the description in the above paragraph, and will not be repeated for the sake of simplicity.

Step S432: Determine whether the host data update command is SUC and the SCQ 310 is full, or whether the logical address in the host data update command already exists in other host data update commands of the SCQ 310. If yes, the flow continues to the processing of step S434; otherwise, the flow continues to the processing of step S442.

Step S434: Launch and execute all SUCs in SCQ 310 sequentially. For example, for one or more SUCs that write data, the processing unit 134 may read the host data to be written from the buffer of the RAM 136, drive the flash memory interface 139 to write the host data to a specific physical address, and then update Corresponding records in the F2H table and/or H2F table to reflect the data write operations that have been performed. For one or more SUCs that discard data, the processing unit 134 may delete the record of the specific logical address from the temporary storage H2F of the RAM 136 . For one or more SUCs that erase data, the processing unit 134 can drive the flash memory interface 139 to erase the specific physical address, and then update the corresponding record in the H2F table to reflect the data erase operation that has been performed. Step S434 can ensure that the SUC with all or part of the same logical address in SCQ 310 is executed earlier than the execution of the host data update command.

Step S442: Determine whether the host data update command is RUC and the RCQ 330 is full, or whether the logical address in the host data update command already exists in other host data update commands of the RCQ 330. If yes, the flow continues to the processing of step S444; otherwise, the flow continues to the processing of step S452.

Step S444: Launch and execute all RUCs in RCQ 330 in sequence. For example, for one or more RUCs that write data, the processing unit 134 may read the host data to be written from the buffer of the RAM 136, drive the flash memory interface 139 to write the host data to a specific physical address, and then update Corresponding records in the F2H table and/or H2F table to reflect the data write operations that have been performed. In response to one or more RUCs that discard data, the processing unit 134 may delete the record of the specific logical address from the temporary H2F of the RAM 136 . In response to one or more RUCs that erase data, the processing unit 134 can drive the flash memory interface 139 to erase the specific physical address, and then update the corresponding record in the H2F table to reflect the data erase that has been performed. write operation. Step S444 can ensure that the RUC with all or part of the same logical address in RCQ 330 is executed earlier than the execution of the host data update command.

Step S452: Determine whether the host data update command is SUC and the logical address in it already exists in other host data update commands of RCQ 330, or whether the host data update command is RUC and the logical address in it already exists in Among other host data update commands of SCQ 310. If yes, the flow continues to the processing of step S454; otherwise, the flow continues to the processing of step S462.

Step S454: Launch and execute all SUCs in SCQ 310 and all RUCs in RCQ 330 in sequence. For technical details of executing SUC and RUC, please refer to the description of steps S434 and S444, which will not be described again for the sake of simplicity. Step S454 can ensure that the SUC or RUC with all or part of the same logical address in the SCQ 310 or RCQ 330 is executed earlier than the execution of the host data update command.

Step S462: Push the host information update command to the corresponding one of SCQ 310 and RCQ 330. If this host data update command is SUC, SCQ 310 is pushed. If this host profile update command is RUC, RCQ 330 is pushed.

An example is given below to illustrate the execution of the method in Figure 4. Initially, SCQ 310 and RCQ 330 have empty queues.

The processing unit 134 receives the host write command W1={LBA#200~215,D1} at time point t1 (step S422), generates the host data update command DU1={1,200,16,PA#1} according to the content of W1 and Marked as SUC (step S424). Because the three judgments are not consistent, the host data update command DU1={1,200,16,PA#1} is pushed into the SCQ 310. At this time, the SCQ 310 contains {DU1}, and the RCQ 330 is an empty queue (step S462).

The processing unit 134 receives the host write command W2={LBA#300,D2} at time point t2 (step S422), generates the host data update command DU2={2,300,1,PA#2} according to the content of W2 and marks it as RUC (step S424). Because the three judgments are not consistent, the host data update command DU2={2,300,1,PA#2} is pushed into RCQ 330. At this time, SCQ 310 contains {DU1}, and RCQ 330 contains {DU2} (step S462).

The processing unit 134 receives the host write command W3={LBA#400~415,D3} at time point t3 (step S422), generates the host data update command DU3={3,400,16,PA#3} according to the content of W3 and Marked as SUC (step S424). Because the three judgments are not consistent, the host data update command DU3={3,400,16,PA#3} is pushed into SCQ 310. At this time, SCQ 310 contains {DU1, DU3}, and RCQ 330 contains {DU2} (step S462) .

The processing unit 134 receives the host write command W4={LBA#300~315,D4} at time point t4 (step S422), generates the host data update command DU4={4,300,16,PA#4} according to the content of W4 and Marked as SUC (step S424). Because the logical address LBA#300~315 in the host data update command DU4 is partially the same as the logical address LBA#300 in DU2 in the RCQ 330 (the "yes" path in step S452), SCQ 310 is launched and executed in sequence. The host data update commands DU1 and DU3 in RCQ 330, and the host data update command DU2 in RCQ 330 (step S454). Next, the host data update command DU4={4,300,16,PA#4} is pushed into the SCQ 310. At this time, the SCQ 310 contains {DU4} and the RCQ 330 is an empty queue (step S462).

The processing unit 134 receives the host write command W5={LBA#200,D5} at time point t5 (step S422), generates the host data update command DU5={5,200,1,PA#5} according to the content of W5 and marks it as RUC (step S424). Because the three judgments are not consistent, the host data update command DU5={5,200,1,PA#5} is pushed into RCQ 330. At this time, SCQ 310 contains {DU4} and RCQ 330 contains {DU5} (step S462).

In order to solve the problem of dirty writing caused by the above embodiments, embodiments of the present invention propose another scheduling mechanism for host data update commands. Referring to the method flow chart shown in Figure 5, this method is executed by the processing unit 134 when loading and executing FTL, continuously receiving host commands for data update from the host terminal 110, and generating host commands according to the type of the host command and the parameters carried therein. data update commands, and use the sequential update command queue 310 and the random update command queue 330 to schedule these host data update commands, and use preset rules to execute these host data update commands. The detailed description is as follows: The technical contents of steps S512, S514, S522, and S524 are respectively similar to steps S412, S414, S422, and S424 will not be described in detail for the sake of simplicity.

Step S532: Determine whether SCQ 310 is full. If yes, the flow continues to the processing of step S534; otherwise, the flow continues to the processing of step S542.

The technical content of step S534 is similar to step S434, and will not be described again for simplicity.

Step S542: Determine whether RCQ 330 is full. If yes, the flow continues to the processing of step S544; otherwise, the flow continues to the processing of step S552.

The technical content of step S544 is similar to step S444, and will not be described again for simplicity.

Step S552: Determine whether the logical address in the host data update command is the same as the logical address of any SUC or RUC in SCQ 310 and RCQ 330. If yes, the flow continues to the processing of step S554; otherwise, the flow continues to the processing of step S562.

Step S554: Delete the duplicate logical addresses from the corresponding host data update commands in SCQ 310 and RCQ 330.

The technical content of step S562 is similar to step S462, and will not be described again for simplicity.

An example is given below to illustrate the execution of the method in Figure 5. Initially, SCQ 310 and RCQ 330 have empty queues. The processing unit 134 receives the host write commands W1={LBA#200~215,D1}, W2={LBA#300,D2}, and W3={LBA#400~415,D3 at time points t1, t2, and t3 respectively. } (step S522), generate host data update commands DU1={1,200,16,PA#1}, DU2={2,300,1,PA#2}, and DU3={3,400,16 based on the contents of W1, W2, and W3 respectively. ,PA#3}, and marked as SUC, RUC, and SUC respectively (step S524). Because the host data update commands DU1, DU2, and DU3 cannot pass the three judgments, the host data update commands DU1 and DU3 are pushed into the SCQ 310, and the host update command DU2 is pushed into the RCQ 330 (step S562). After the host write command W3 is processed, SCQ 310 contains {DU1, DU3}, and RCQ 330 contains {DU2}.

The processing unit 134 receives the host write command W4={LBA#300~315,D4} at time point t4 (step S522), generates the host data update command DU4={4,300,16,PA#4} according to the content of W4 and Marked as SUC (step S524). Because the logical addresses LBA#300~315 in the host data update command DU4 are the same as the logical addresses in DU2 in RCQ 330 LBA#300 (the "Yes" path in step S552) deletes the duplicate logical address from DU2 in RCQ 330, so that the original host data update command DU2={2,300,1,PA#2} is changed to DU2 '={2,NULL,0,NULL} (step S554). Next, the host data update command DU4={4,300,16,PA#4} is pushed into the SCQ 310. At this time, the SCQ 310 contains {DU1, DU3, DU4}, and the RCQ 330 contains {DU2'} (step S562). It should be noted here that since the logical address of the host data update command DU2’ is NULL, this command will not be executed after it is launched from RCQ 330 in the future.

The processing unit 134 receives the host write command W5={LBA#200,D5} at time point t5 (step S522), generates the host data update command DU5={5,200,1,PA#5} according to the content of W5 and marks it as RUC (step S524). Because the logical address LBA#200 in the host data update command DU5 is partially the same as the logical address LBA#200~215 in DU1 in RCQ 330 (the path of "Yes" in step S552), the duplicate logical address is changed from DU1 in SCQ 310 is deleted, so that the original host data update command DU1={1,200,16,PA#1} is changed to DU1'={1,201,15,PA#1'} (step S554). Next, push the host data update command DU5={5,200,1,PA#5} into RCQ 330. At this time, SCQ 310 contains {DU1', DU3, DU4}, and RCQ 330 contains {DU2', DU5} (step S562 ).

The logical address update operation and the enqueuing operation of the host data update command will be continuously executed until the SCQ 310 or RCQ 330 is full. Once the SCQ 310 is full (the "YES" path in step S532), all host data update commands in the SCQ 310 are sequentially pushed out and executed (step S534). Once the RCQ 330 is full (the "YES" path in step S542), all host data update commands in the RCQ 330 are sequentially pushed out and executed (step S544).

All or part of the steps in the method of the present invention can be implemented by computer instructions, such as a firmware translation layer (FTL) in a storage device, a driver for a specific hardware, etc. In addition, it can also be implemented in other types of programs. Those with ordinary skill in the art can write the methods of the embodiments of the present invention as computer instructions, which will not be described again for the sake of simplicity. Computer instructions implemented according to methods of embodiments of the present invention Can be stored on appropriate computer-readable media, such as DVD, CD-ROM, USB disk, hard drive, or can be placed on a network accessible through a network (such as the Internet, or other appropriate vehicles) server.

Although Figures 1 and 2 contain the components described above, it does not rule out the use of more other additional components to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts of Figures 4 to 5 are executed in a specified order, those skilled in the art can modify the order of these steps while achieving the same effect without violating the spirit of the invention. Therefore, The present invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

S412~S462: Method steps

Claims (15)

A method for scheduling and executing host data update commands, executed by a processing unit. The method includes: providing a first queue and a second queue, wherein the first queue includes a plurality of first host data update commands, Each of the first host data update commands is a first type of host data update command and includes a first logical address, the second queue includes a plurality of second host data update commands, and each of the second The host data update command is a second type of host data update command and includes a second logical address; a third host data update command is generated according to the type and parameters of the host command received from the host for updating data, and the flag is The third host data update command is the first type of host data update command, wherein the third host data update command includes a third logical address; in response to the third logical address being the same as the plurality of In the case of the first logical address of one of the first host data update commands, launch and execute all the first host data update commands in the first queue; in response to the same third logical address In the case of the second logical address of one of the plurality of second host data update commands, launch and execute all of the first host data update commands and the second host data update commands in the first queue. queue all the second host data update commands; and push the third host update command into the first queue. The method for scheduling and executing host data update commands as described in claim 1, wherein the first type of host data update command is a sequential host update command, and the second type of host data update command is a random host Update command. The method of scheduling and executing host data update commands as described in request item 2, wherein, The logical block address length of the sequential host update command is greater than 1, and the logical block address length of the random host update command is equal to 1. The method for scheduling and executing host data update commands as described in claim 1, wherein the first type of host data update command is a random host update command, and the second type of host data update command is a sequential host Update command. The method for scheduling and executing host data update commands as described in claim 4, wherein the logical block address length of the sequential host update command is greater than 1, and the logical block address length of the random host update command is greater than 1. equal to 1. The method of scheduling and executing a host data update command as described in claim 1 includes: in response to the situation that the first queue is full, launching and executing all the first host data in the first queue. Update command. The method of scheduling and executing host data update commands as described in claim 6, wherein the first queue is a sequential update command queue or a random update command queue. A computer program product for scheduling and executing host data update commands, comprising program code, wherein when a processing unit executes the program code, scheduling and executing host data as described in any one of claims 1 to 7 is performed Method for updating commands. A device for scheduling and executing host data update commands, including: a random access memory, configuring space for a first queue and a second queue, wherein the first queue contains a plurality of first host data update commands , each of the first host data update commands is a first type of host data update command and includes a first logical address, the second queue includes a plurality of second host data update commands, and each The second host data update command is a second type of host data update command and includes a second logical address; and a processing unit coupled to the random access memory, configured to receive a request from the host according to the second host data update command. The type and parameters of the host command to update the data, generate a third host data update command, and mark the third host data update command as the first type of host data update command, wherein the third host data update command Comprise a third logical address; in response to the situation that the third logical address is the same as the first logical address of one of the plurality of first host data update commands, launch and execute the first queue all the first host data update commands in; in response to the situation that the third logical address is the same as the second logical address of one of the plurality of second host data update commands, derive and execute all all first host data update commands in the first queue and all second host data update commands in the second queue; and push the third host update command into the first Queue. The device for scheduling and executing host data update commands as described in claim 9, wherein the first type of host data update command is a sequential host update command, and the second type of host data update command is a random host Update command. The device for scheduling and executing host data update commands as described in claim 10, wherein the logical block address length of the sequential host update command is greater than 1, and the logical block address length of the random host update command is greater than 1. equal to 1. The device for scheduling and executing host data update commands as described in claim 9, wherein the first type of host data update command is a random host update command, and the second type of host data update command is a sequential host Update command. The device for scheduling and executing host data update commands as described in claim 12, wherein the logical block address length of the sequential host update command is greater than 1, and the logical block address length of the random host update command is greater than 1. equal to 1. The device for scheduling and executing host data update commands as described in claim 9, wherein the processing unit is used to push out and execute all the commands in the first queue in response to the situation that the first queue is full. The first host data update command. The device for scheduling and executing host data update commands as described in claim 14, wherein the host command is a host write command, a host discard command, or a host erase command.

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