TW202145042A - Method and apparatus for encrypting and decrypting physical address information - Google Patents

Abstract

The invention relates to a method and an apparatus for encrypting and decrypting physical address information. The method is performed by a flash controller to include: receiving a read command requesting for physical block addresses (PBAs) corresponding to a logical block address (LBA) range from a host side; reading the PBAs corresponding to the LBA range from a flash device; arranging the PBAs into entries; encrypting the content of each entry by using an encryption algorithm and an encryption parameter to obtain encrypted entries; and transmitting the encrypted entries to the host side. By encrypting entries including PBA information, it prevents illegal persons from spying on the PBA information with the host side to know internal data management of a device side.

Description

Method and apparatus for encrypting and decrypting physical address information

The present invention relates to a storage device, in particular to a method and device for encrypting and decrypting physical address information.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address for accessing NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of NOR flash memory in time. material. In contrast, NAND flash memory is not random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data in flash for write operations) or a block (the smallest block of data in flash for erase operations).

In order to improve the data writing and reading performance of the flash memory module, the device side performs data writing and reading in parallel with multiple channels. In order to achieve the purpose of parallel processing, a continuous piece of data will be distributed to the flash memory cells connected to multiple channels, and a logical-to-physical (L2P Mapping Table) will be used to record the logical bits of user data. The correspondence between addresses (managed by the host side) and physical addresses (managed by the flash controller). Furthermore, in the new specification, the flash memory controller can organize the correspondence between logical addresses and physical addresses into the format of Host Performance Booster (HPB Entries) and provide it to the host. After that, the host side can take out the required physical address from the HPB project, and carry the physical address in the HPB read command sent to the device side, so that the flash memory controller can directly read and use the physical address from the flash memory module. The user data is returned to the host, without the need to spend time and computing resources to read the logical entity comparison table from the flash memory module and perform logical entity address conversion as before. However, the physical addresses of the HPB project are stored in clear code, so that illegal persons can spy on the physical addresses on the host side to know the internal data management method on the device side, and use improper means to obtain sensitive information (for example, system or management data). Therefore, the present invention proposes a method and apparatus for encrypting and decrypting physical address information for improving data security.

In view of this, how to alleviate or eliminate the above-mentioned deficiencies in related fields is a problem to be solved.

This specification relates to a method for encrypting and decrypting physical address information, which is executed by a flash memory controller, including: receiving a read command from a host, requesting to obtain a plurality of physical block addresses corresponding to a logical block address range ; read the physical block address corresponding to the logical block address interval from the flash memory device; program the physical block address into a plurality of items; encrypt the content of each item using an encryption algorithm and encryption parameters to obtain encrypted project; and transmitting the encrypted project to the host.

The present specification also relates to an apparatus for encrypting and decrypting physical address information, comprising: control logic; a host interface; and a processing unit. The processing unit is used to receive a read command from the host through the host interface, and request to obtain a plurality of physical block addresses corresponding to a logical block address range; read the first table from the flash memory device through the control logic, the first The table contains physical block addresses corresponding to logical block address ranges; program physical block addresses into multiple items; encrypt the content of each item using an encryption algorithm and encryption parameters to obtain encrypted items; and pass The host interface transmits the encrypted item to the host.

Each physical block address indicates where in the logical block address range the user data for that particular logical block address is actually stored in the flash memory device.

One of the advantages of the above embodiment is that by encrypting the item including the physical block address, it can prevent illegal persons from knowing the internal data management mode of the device side by snooping on the physical address on the host side.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

The following description is a preferred implementation manner to complete the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. Reference must be made to the scope of the following claims for the actual inventive content.

It must be understood that the words "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, elements and/or components, but do not exclude the possibility of adding More technical features, values, method steps, job processes, elements, components, or any combination of the above.

The use of words such as "first", "second", "third", etc. in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority order, a preceding relationship between them, or an element Prior to another element, or chronological order in which method steps are performed, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements can also be read in a similar fashion, such as "between" versus "directly interposed," or "adjacent" versus "directly adjoining," and the like.

Refer to Figure 1. The electronic device 10 includes a host device (also referred to as a host side) 110 , a flash memory controller 130 and a flash memory device 150 , and the flash controller 130 and the flash memory device 150 may be collectively referred to as a device side. The electronic device 10 can be implemented in electronic products such as personal computers, notebook computers (Laptop PCs), tablet computers, mobile phones, digital cameras, and digital video cameras. The host device 110 and the host interface (Host Interface) 131 of the flash controller 130 can communicate with each other through a communication protocol such as Universal Flash Storage (UFS). Although the following embodiments describe the function of the Host Performance Booster (HPB) of the UFS specification, those skilled in the art can apply the present invention to similar functions of other specifications, and the present invention is not limited thereby. The control logic 139 of the flash memory controller 130 and the flash memory device 150 can communicate with each other through a Double Data Rate (DDR) protocol, such as Open NAND Flash Interface (ONFI), a double data rate switch (DDR Toggle) or other protocols. The flash controller 130 includes a processing unit 134, which may be implemented using a variety of means, such as using general-purpose hardware (eg, a microcontroller, a central processing unit, a multiprocessor with parallel processing capabilities, a graphics processor, or other computationally capable processors). device) and, when executing software and/or firmware instructions, provide the functionality described later. The processing unit 134 receives HPB commands, such as an HPB read command (HPB READ Command), an HPB read buffer command (HPB READ BUFFER Command), an HPB write buffer command (HPB WRITE BUFFER Command), etc. through the host interface 131 , and Execute these commands. The flash memory controller 130 includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (DRAM), a static random access memory (SRAM) ) or a combination of the two above for configuration space as a data buffer. The random access memory 136 can also store data required in the execution process, such as variables, data tables, and the like. The flash controller 130 includes a Read Only Memory (ROM) 135 for storing program codes that need to be executed when booting. The control logic 139 includes a NAND Flash Controller (NFC), which provides functions required for accessing the flash device 150, such as Command Sequencer (Command Sequencer), Low Density Parity Check (LDPC), etc. .

The flash controller 130 includes a codec (Coder-decoder, Codec) 138, which is a dedicated hardware, including encoding logic for encrypting the original HPB item; and decoding logic for decrypting the encrypted content, for restoring the original HPB item . The following paragraphs will detail the structure, function, and interaction of codec 138 with other components.

A bus architecture (Bus Architecture) 132 can be configured in the flash memory controller 130 for coupling elements to each other to transmit data, addresses, control signals, etc. These elements include a host interface 131, a processing unit 134, a ROM 135, RAM 136, codec 138, control logic 139, etc. In some embodiments, host interface 131, processing unit 134, ROM 135, RAM 136, codec 138, and control logic 139 may be coupled to each other through a single bus. In other embodiments, a high-speed bus may be configured in the flash controller 130 for coupling the processing unit 134, the codec 138, and the RAM 136 to each other, and a low-speed bus may be configured for the processing unit 134, the codec The decoder 138, the host interface 131 and the control logic 139 are coupled to each other. The bus bars contain parallel physical lines that connect more than two components in the flash controller 130 .

The flash memory device 150 provides a large amount of storage space, usually hundreds of gigabytes (Gigabytes, GB), or even several terabytes (Terabytes, TB), for storing large amounts of user data, such as High-resolution pictures, videos, etc. The flash memory device 150 includes a control circuit and a memory array. The memory cells in the memory array may include Single Level Cells (SLCs), Multiple Level Cells (MLCs), Triple Level Cells (Triple Level Cells) Cells, TLCs), Quad-Level Cells (Quad-Level Cells, QLCs), or any combination of the above. The processing unit 134 writes the user data to the designated address (destination address) in the flash memory device 150 through the control logic 139, and reads the user data and L2P comparison from the designated address (source address) in the flash memory device 150 specified section in the table. The control logic 139 uses several electronic signals to coordinate data and command transfer between the flash controller 130 and the flash device 150 , including a data line, a clock signal, and a control signal. Data lines can be used to transmit commands, addresses, read and written data; control signal lines can be used to transmit Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable Can (Command Latch Enable, CLE), write enable (Write Enable, WE) and other control signals.

In other embodiments, referring to FIG. 2 , the electronic device 20 includes a modified flash controller 230 that does not include the codec 138 shown in FIG. 1 . In the flash controller 230, the functions of the codec 138 can be replaced by software or firmware instructions, and when the processing unit 134 loads and executes these instructions, encrypting the original HPB item and decrypting the encrypted content is done for Restore the original HPB project. In other words, Figure 1 contains a solution that uses hardware to encrypt and decrypt, while Figure 2 contains a solution that uses software to encrypt and decrypt.

Referring to FIG. 3 , the interface 151 in the flash memory device 150 may include four I/O channels (hereinafter referred to as channels) CH#0 to CH#3, each of which is connected to four NAND flash memory cells, for example, channel CH #0 connects NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent die. The control logic 139 can issue one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11 , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory cells in parallel, or write user data to the enabled NAND flash memory cells.

Since a continuous piece of data (that is, a piece of data with a continuous logical address) is distributed and stored in the flash memory cells connected to multiple channels, the flash memory controller 130 uses a logical-to-physical (L2P Mapping Table) table. ) records the correspondence between the logical address (managed by the host device 110 ) and the physical address (managed by the flash controller 130 ) of the user data. The L2P comparison table may also be referred to as a host-to-flash comparison table (Host-to-flash, H2F Mapping Table). The H2F comparison table contains multiple records, which store the information of the physical address where the user data of each logical address is actually stored in the order of the logical addresses. However, since the RAM 136 cannot provide enough space to store the entire H2F comparison table for the processing unit 134 to quickly look up the data reading operation in the future, the H2F comparison table can be divided into multiple first tables (Table 1, also known as T1 table) ), and stored in the non-volatile flash memory device 150 , so that in the future data read operations only need to read the corresponding T1 table from the flash memory device 150 to the RAM 136 . Referring to Figure 4, the entire H2F comparison table can be cut into T1 tables 430#0~430#15. The processing unit 134 further maintains a second table (Table 2, also referred to as a T2 table) 410, which includes a plurality of records, and stores the physical address information of the T1 table associated with each logical address segment in the order of logical addresses. For example, the associated T1 table 430#0 of the 0th to 4095th Logical Block Addresses (LBAs) is stored in a specific physical block (the letter "Z") of a specific Logical Unit Number (LUN) " can represent the number of the LUN and the physical block) of the 0th physical page, the associated T1 table 430#1 of the 4096th to 8191st LBAs is stored in the 1st physical page of a specific physical block of a specific LUN, and so on analogy. Although only 16 T1 tables are included in FIG. 4 , those skilled in the art can set more T1 tables according to the capacity of the flash memory device 150 , and the present invention is not limited thereto.

The space required for each T1 table can be 4KB, 8KB, 16KB, etc. Each T1 table stores the physical address information corresponding to each LBA according to the LBA order, and each LBA corresponds to a fixed-size physical storage space, such as 4KB. Referring to FIG. 5, for example, T1 table 430#0 stores physical address information from LBA#0 to LBA#4095 in sequence. The physical address information 530 can be represented by four bytes: the first two bytes 530-0 record the physical block number (Physical Block Number); the last two bytes 530-1 record the physical page number (Physical Page Number) . For example, physical address information 530 corresponding to LBA#2 may point to physical page 510 in physical block 310#1. The byte 530-0 records the number of the physical block 310#1, and the byte 530-1 records the number of the physical page 510.

Referring to FIG. 6 , in the HPB specification, the host 110 configures space in its system memory as the HPB cache 600 for temporarily storing the information of the H2F comparison table maintained by the device. The HPB cache 600 stores a plurality of HPB entries (HPB Entries) received from the device, and each HPB entry records information corresponding to a physical address of an LBA. Next, the host side 110 may issue an HPB read command carrying the HPB item to the device side for obtaining the user data of the designated LBA. The device side can directly drive the control logic 139 to read the user data of the specified LBA from the flash memory device 150 according to the information in the HPB item, without the need to spend time and computing resources reading the H2F comparison table from the flash memory device 150 as before. The user data of the designated LBA can be read from the flash memory device 150 only after the logical physical address translation is performed. The establishment and application of HPB cache 600 can be divided into three stages:

Phase I (HBP initialization): The host side 110 requests the device side (specifically, the flash controller 130 ) to obtain its device capabilities and configure HBP functions, including HPB mode (Mode).

Phase II (L2P cache management): The host 110 allocates space in the system memory as the HPB cache 600 for storing HPB items. The host 110 can send an HPB read buffer command (HPB READ BUFFER Command) to the flash controller 130 at a required time point in the configured mode, so as to load the specified HPB item from the device. Next, the host 110 stores the HPB items in one or more sub-regions (Sub-Regions) in the HPB cache 600 . In the HPB specification, the LBAs of each logical unit (eg, Partition) are divided into multiple HPB regions, and each HPB region can be further subdivided into multiple sub-regions. For example, the HPB cache 600 may include N HPB regions, and each HPB region may include L subregions, wherein the variables "N" and "L" are positive integers for storing HPB entries of an LBA interval. The division example of HPB cache 600 is shown in Table 1: Table 1 HPB subarea #0 HPB area #0 HPB sub-region #1 … HPB District #L-1 … … … … … HPB subarea #0 HPB area #N-1 HPB sub-region #1 … HPB District #L-1 In some embodiments, regions and subregions can be set to have 32MB of space, that is, each region contains only one subregion. In other embodiments, regions may be configured to have 32MB of space, while sub-regions may be configured to have 4MB, 8MB or 16MB of space. That is, each area may contain eight, four or two sub-areas.

Phase III (HPB read command): The host 110 searches the HPB entries in the HPB cache 600 for HPB entries containing physical block addresses (PBAs) of the data to be read from the LBA. Next, the host side 110 sends an HPB read command (HPB READ Command) to the flash memory controller 130 , which includes HPB items in addition to the LBA, TRANSFER LENGTH and other information, for obtaining the specified user data from the device side .

However, in the past, the PBA information was usually included in the HPB project in clear code, so that the unscrupulous person could spy on the PBA information through the host 110 to know the internal data management method of the device, and use improper means to obtain sensitive data (for example, system or management data).

The HPB specification defines two modes for obtaining HPB items: Host Control Mode and Device Control Mode. The host control mode is triggered by the host 110 to determine which HPB subareas need to be stored in the HPB cache 600 ; and the device control mode is triggered by the flash controller 130 to determine which HPB subareas need to be stored in the HPB cache 600 . Those skilled in the art understand that the embodiments of the present invention cover these two or other similar control modes.

Referring to the operation sequence diagram applied in the host control mode as shown in Figure 7, the detailed description is as follows:

Operation 711: The host 110 determines which sub-regions are about to be activated (Activated).

Operation 713: The host 110 sends an HPB read buffer command to the flash controller 130, and requests the flash controller 130 to determine the HPB entry of the subarea. The HPB read buffer command can contain 10 bytes, of which the 0th byte records the operation code (Operation Code) "F9h", the 2nd and 3rd bytes record the information about the HPB area to be activated, and the first byte The 4th and 5th bytes record the information about the subarea to be activated.

Operation 715: The flash controller 130 reads the H2F comparison table of a specific part from the flash memory device 150, and arranges the read comparison information into HPB items. In order to prevent the PBA information in the HPB project from being snooped on by illegal personnel to understand the internal management mode of data storage, the flash controller 130 encrypts the content of the HPB project. The following paragraphs describe the read operation for this step in more detail.

Operation 717 : The flash controller 130 transmits a DATA IN UFS Protocol Information Unit (UPIU) to the host 110 , which contains the encrypted content of the HPB entry that determines the sub-region, instead of clear text.

Operation 719 : The host 110 stores the received encrypted HPB entry into the promoter region in the HPB cache 600 .

Operation 731 : The host 110 determines which regions are about to be deactivated. It should be noted here that in the HPB specification, startup is based on sub-areas, and shutdown is in units of regions. The host 110 can determine the sub-region to be activated and the region to be closed according to the requirements of its algorithm.

Operation 733: The host side 110 sends an HPB write buffer command (HPB WRITE BUFFER command) to the flash memory controller 130, and notifies the flash memory controller 130 of the area determined to be closed. The HPB read buffer command may contain 10 bytes, wherein the 0th byte records the opcode "FAh" and the 2nd and 3rd bytes record the information of the area to be closed.

Operation 735: The flash controller 130 closes the region. For example, after the flash memory controller 130 transmits the HPB item to the host side 110, the flash memory controller 130 can perform an optimization operation on the read process of the subsequent read command from the host side 110 for the activated sub-area, and then After the host 110 is notified of the closed area, the flash controller 130 can terminate the relevant optimization operation corresponding to the closed area.

Operation 751: After executing the host write command, host erase command or background operation (such as garbage collection, wear leveling, read recovery, read refresh, etc.), the flash memory controller 130 updates the content of the H2F comparison table, wherein Contains content corresponding to the promoter region.

Operation 753 : The flash controller 130 transmits a reply UFS protocol information unit (RESPONSE UPIU) to the host 110 , which includes information suggesting that the host 110 update the HPB entry of the sub-region.

Operations 755 and 757: The host side 110 sends the HPB read buffer command to the flash controller 130, and requests the flash controller 130 for the HPB entry of the proposed subarea.

Operation 771: The flash memory controller 130 reads the H2F comparison table of a specific part from the flash memory device 150, and arranges the read comparison information into HPB items. Likewise, the flash controller 130 also encrypts the contents of the HPB entry. The following paragraphs describe the read operation for this step in more detail.

Operation 773: The flash controller 130 transmits the data input UPIU to the host side 110, which contains the encrypted content of the HPB entry of the update subarea instead of clear text.

Operation 775 : the host 110 overwrites the content in the promoter region of the HPB cache 600 with the received encrypted HPB entry.

Referring to the operation sequence diagram applied in the device control mode as shown in Figure 8, the detailed description is as follows:

Operation 811: The flash controller 130 decides which sub-regions are about to be powered on and/or which regions are about to be powered off.

Operation 813: The flash controller 130 transmits a reply UPIU to the host side 110, wherein the host side 110 is advised to activate the above-mentioned sub-area and/or close the above-mentioned area.

Operation 815: If necessary, the host 110 discards the HPB entries of those HPB regions that are no longer valid from the system memory.

Operation 831 : If necessary, the host side 110 sends an HPB read buffer command to the flash controller 130 to request the flash controller 130 for the HPB item of the proposed subarea.

Operation 833: The flash controller 130 reads the H2F comparison table of a specific part from the flash memory device 150, and arranges the read comparison information into HPB items. Likewise, the flash controller 130 also encrypts the contents of the HPB entry. The following paragraphs describe the read operation for this step in more detail.

Operation 835: The flash controller 130 transmits the data input UPIU to the host 110, which contains the encrypted content of the HPB entry corresponding to the above-mentioned sub-area, instead of clear text.

Operation 837 : The host 110 stores the received encrypted HPB entry into the promoter region in the HPB cache 600 .

For the technical details of the read operation 715, 771 or 833, please refer to the flowchart of the HPB item generation method shown in FIG. 9. This method is implemented by the processing unit 134 when the relevant software or firmware code is loaded and executed, and further described as follows:

Step S910 : Receive the above-mentioned HPB read buffer command from the host terminal 110 through the host interface 131 , which includes the information of the subarea to be activated. The HPB read buffer command requests the flash controller 130 to read a PBA of an LBA interval.

Step S920 : Read the specific T1 table and T2 table corresponding to the promoter region from the flash memory device 150 through the control logic 139 .

Step S930: Arrange HPB items according to the contents of the T1 table and the T2 table. Those skilled in the art understand that the length (eg, 8 bytes) of each HPB entry of the HPB specification may be larger than the length (eg, 4 bytes) of the physical address information associated with each LBA recorded in the T1 table. Therefore, in some embodiments, in addition to the physical address information of each LBA (that is, the PBA information of the LBA recorded in the T1 table), the processing unit 134 may add dummy values (Dummy Values) to the remaining space of the HPB entry. to fill the HPB project. In other embodiments, in addition to the physical address information of each LBA, the processing unit 134 adds other information to the remaining space of the HPB item according to different system requirements, so as to speed up future HPB read operations.

In some embodiments, the processing unit 134 may populate each octet of HPB entries with corresponding PBA information of the 4-byte T1 table and corresponding PBA information of the 4-byte T2 table. The PBA information of the T1 table indicates the information associated with where in the flash memory device 150 a particular LBA is actually stored, and the PBA information of the T2 table indicates the information of where in the flash memory device 150 this T1 table is actually stored. The PBA information of the T2 table can be checked by the device in the future whether the HPB entry is invalid. If the PBA information of the T2 table included in the HPB entry obtained from the HPB read command in the future does not match the address of the corresponding T1 table actually stored in the flash memory device 150, the processing unit 134 determines that the HPB entry is invalid. Examples of HPB projects are shown in Table 2: Table 2 HPB item number PBA information of T2 table (4 bytes) PBA information for T1 table (4 bytes) 0 0x00004030 0x0000A000 1 0x00004030 0x0000A001 2 0x00004030 0x0000A002 3 0x00004030 0x0000A003 4 0x00004030 0x0000A004 5 0x00004030 0x0000A005 6 0x00004030 0x0000B009 7 0x00004030 0x0000A007 8 0x00004030 0x0000A008 9 0x00004030 0x0000A009 10 0x00004030 0x0000A00A 11 0x00004030 0x0000B00A 12 0x00004030 0x0000A00C … … …

In other embodiments, the processing unit 134 may fill in the corresponding PBA information of the 28-bit T1 table, the corresponding PBA information of the 24-bit T2 table, and the 12-bit continuous Length (Continuous Length). The continuation length indicates how many LBAs following the LBA are consecutively stored in the physical addresses of the flash memory device 150 . Therefore, one HPB entry can express information for multiple consecutive PBAs in the T1 table. Examples of HPB projects are shown in Table 3: Table 3 HPB item number Consecutive length (12 bits) PBA information for T2 form (24 bits) PBA information for T1 form (28 bits) 0 0x5 0x004030 0x000A000 1 0x4 0x004030 0x000A001 2 0x3 0x004030 0x000A002 3 0x2 0x004030 0x000A003 4 0x1 0x004030 0x000A004 5 0x0 0x004030 0x000A005 6 0x0 0x004030 0x000B009 7 0x3 0x004030 0x000A007 8 0x2 0x004030 0x000A008 9 0x1 0x004030 0x000A009 10 0x0 0x004030 0x000A00A 11 0x0 0x004030 0x000B00A 12 0x3 0x004030 0x000A00C 13 0x2 0x004030 0x000A00D 14 0x1 0x004030 0x000A00E 15 0x0 0x004030 0x000A00F … … … … Assuming that the 0th HPB entry in Table 3 is associated with the LBA "0x001000": the 0th HPB entry indicates that the user data of five LBAs after the LBA "0x001000" are physical bits continuously stored in the flash memory device 150 site. Specifically, the data of LBA "0x001000" to LBA "0x001005" are stored in PBA "0x00A000" to PBA "0x00A005" in the flash memory device 150, respectively. In the future, the processing unit 134 can read the user data of the six LBAs "0x001000" to "0x001005" according to the information carried in the 0th HPB entry. If the HPB read command indicates that the LBA to be read is "0x001000" and the transfer length is less than or equal to "6", the processing unit 134 does not need to read the corresponding part of the H2F comparison table from the flash memory device 150.

In still other embodiments, the processing unit 134 may fill in the corresponding PBA information of the 28-bit T1 table, the corresponding PBA information of the 24-bit T2 table, and the corresponding PBA information of the 12-bit T2 table in each 8-byte HPB entry. Continuous Bit Table. The contiguous bit table is used to represent the PBA continuity of multiple subsequent LBAs (eg, 12 subsequent LBAs) of this LBA. For example, 12 bits respectively correspond to 12 subsequent LBAs. Examples of HPB projects are shown in Table 4: Table 4 HPB item number Consecutive bit table (12 bits) PBA information for T2 form (24 bits) PBA information for T1 form (28 bits) 0 0xBDF (101111011111) 0x004030 0x000A000 1 0xDEF (110111101111) 0x004030 0x000A001 2 0xEF7 (111011110111) 0x004030 0x000A002 3 0xF7B (111101111011) 0x004030 0x000A003 4 … 0x004030 0x000A004 … … … … Assuming that the 0th HPB entry in Table 4 is associated with the LBA "0x001000": The contiguous bit table of the 0th HPB entry indicates the PBA continuity of LBAs "0x001001" to "0x00100C". Ideally, the data of LBA "0x001001" to "0x00100C" should be stored in PBA "0x000A001" to "0x000A00C" of flash device 150, respectively. When the value of each bit is "0", it means that the data of the corresponding LBA is not stored in the ideal PBA, and when the value of each bit is "1", it means that the data of the corresponding LBA is stored in the ideal PBA. Therefore, according to the 0th HPB entry, the processing unit 134 can predict PBAs with consecutive bits of "1" in the future and read LBA data from the PBA of the flash device 150, but ignore PBAs with consecutive bits of "0". For example, if the host device 110 sends an HPB read command, the parameter carries the 0th HPB entry and the transmission length is "9", which is used to request the user data of LBA "0x001000" to "0x001008". The processing unit 134 obtains the consecutive bit table in the 0th HPB entry of the HPB read command, and predicts the data of LBA "0x001000" to "0x001005" and LBA "0x001007" to "0x001008" after decoding the consecutive bit table The PBA actually stored in the flash device 150 does not need to load the H2F lookup table from the flash device 150 . In cases where there are only a few breakpoints, the number of times the specific PBA information of the T1 table is loaded from the flash device 150 can be reduced.

Step S940 : Store the original HPB entry in the RAM 136 . Referring to FIG. 10, the RAM 136 may allocate space to the original project area 1010, which may be a space of contiguous memory addresses. The processing unit 134 may sequentially store the original HPB entries to the original entry area 1010 in the RAM 136 according to the order of the LBAs.

Step S950 : Encrypt the HPB item and store the encrypted HPB item in the RAM 136 . Referring to FIG. 10, RAM 136 may allocate space for encrypted entry area 1020, which may be a space of contiguous memory addresses. In the architecture shown in FIG. 1, the processing unit 134 can set the registers in the codec 138 to drive the codec 138, and read the content of the HPB entry as described above from the original entry area 1010 of the RAM 136, according to the setting The parameters encrypt the HPB entry, and store the encrypted HPB entry in the encrypted entry area 1020 in the RAM 136 . After the codec 138 finishes encrypting the HPB item, it sends an interrupt (Interrupt) to the processing unit 134 to notify the encryption completion message, so that the processing unit 134 can continue to process the encrypted HPB item. Alternatively, in the architecture shown in FIG. 2 , the processing unit 134 can load and execute the code of the encryption module to complete the above-mentioned operations.

Examples of available encryption algorithms are as follows: In some embodiments, processing unit 134 or codec 138 cyclically shifts the contents of the HPB entry left or right by n bits, where n represents any integer from 1-63. In other embodiments, the processing unit 134 or the codec 138 adds a preset key value to the content of the HPB item. In other embodiments, the processing unit 134 or the codec 138 performs an exclusive OR (XOR) operation on the content of the HPB item and a preset key value. In still other embodiments, the processing unit 134 or the codec 138 performs randomization according to preset rules. For example, the preset rule may be the i-th bit and the 63-i-th bit swap of the HPB item, i from "0" to "31".

In order to strengthen the data security, the HPB items of a sub-area can be divided into several groups according to the LBA, and use different encryption algorithms and corresponding encryption parameters to encrypt the HPB items of different groups. An example of the HPB item grouping rule is as follows: In some embodiments, the LBA associated with the HPB item may be first divided by a value, and the HPB items are grouped according to their Quotients. Suppose this value is set to "100": the first group contains HPB items of LBA#0~99, the second group contains HPB items of LBA#100~199, and so on. In other embodiments, the LBA associated with the HPB items may be first divided by a value, and the HPB items are grouped according to the remaining numbers (Remainders). Suppose this value is set to "100": the first group contains HPB items such as LBA#0, LBA#100, LBA#200, etc., and the second group contains HPB items such as LBA#1, LBA#101, LBA#201, etc. And so on.

In some embodiments, different groups of HPB items may use the same encryption algorithm but bring in different encryption parameters. For example, the content of each HPB item of the first group is rotated 1 bit to the left, the content of each HPB item of the second group is rotated 2 bits to the right, and the content of each HPB item of the third group Rotate 3 bits to the left, and so on. Alternatively, the content of each HPB item of the first group is added with the first value or XORed with the first value, and the content of each HPB item of the second group is added with the second value or XORed with the second value, The content of each HPB item of the third group is added to or XORed with the third value, and so on. Or, the content of each HPB item of the first group is shuffled according to the first rule, the content of each HPB item of the second group is shuffled according to the second rule, and the content of each HPB item of the third group is shuffled according to the second rule. The third rule goes out of order, and so on.

In other embodiments, different groups of HPB items may use different encryption algorithms and bring appropriate encryption parameters. For example, the content of each HPB item of the first group is rotated by n bits to the left, the content of each HPB item of the second group is XORed with the preset value, and the content of each HPB item of the third group is added On a specific value, the content of each HPB item of the fourth group is shuffled according to the preset rules, and so on.

In some embodiments, the processing unit 134 may store a Group-and-encryption Mapping Table in the RAM 136, including a plurality of configuration records. Each configuration record stores information indicating which encryption algorithm and corresponding encryption parameters are used by a particular group of HPB items. In other embodiments, the information similar to the group encryption lookup table can also be embedded in the program logic executed by the processing unit 134, and the present invention is not limited thereby.

Step S960: Read the encrypted HPB entry from the encrypted entry area 1020 in the RAM 136, and transmit the data input UPIU to the host 110, which contains the encrypted HPB entry. When the content of the HPB item is encrypted, the unscrupulous person cannot understand the content of the HPB item through the host 110 and know the internal data management method of the device side accordingly, which can prevent the unscrupulous person from using improper means to obtain sensitive information. Although the HPB items are encrypted, the host 110 can still obtain the desired user data from the device as long as the encrypted HPB items are carried in the HPB read command in the future.

Referring to the operation sequence diagram of HPB data reading as shown in Figure 11, the detailed description is as follows:

Operation 1110 : the host 110 obtains the HPB entry corresponding to the LBA to be read from the HPB cache 600 . It should be noted that the contents of these HPB items are already encrypted.

Operation 1120: The host 110 sends an HPB read command to the flash controller 130, and requests the flash controller 130 for the user data of the specified LBA, which includes the LBA, the transfer length and the HPB item.

Operation 1130: The flash controller 130 decrypts the content of the HPB entry, and reads the requested user data from the flash device 150 according to the PBA information of the T1 table of the HPB entry (plus the run length or run bit table if necessary).

Operation 1140: The flash controller 130 transmits the data input UPIU to the host 110, which includes the requested user data.

Operation 1150: The host 110 processes the user data according to the needs of the operating system, drivers, applications, and the like.

For the technical details of the reading operation 1130, please refer to the flowchart of the data reading method shown in FIG. 12. This method is implemented by the processing unit 134 when the relevant software or firmware code is loaded and executed, and the further description is as follows:

Step S1210: Receive an HPB read command from the host 110 through the host interface 131, which includes information such as LBA, transmission length and HPB item. Referring to FIG. 10, the RAM 136 may allocate space to the receiving item area 1030, which may be a space of a continuous memory address for storing the received HPB items.

Step S1220: If the original HPB item has implemented group encryption, the group to which it belongs is obtained according to the LBA in the HPB read command. For the technical details of obtaining the group to which the LBA belongs, reference may be made to the description of step S950, which will not be repeated for brevity. If the original HPB project did not implement cluster encryption, this step can be ignored.

Step S1230: Decrypt the HPB item using the corresponding decryption algorithm and decryption parameters. The decryption algorithm and decryption parameters described above are the reverse process (Reverse Process) of the encryption algorithm and encryption parameters used to encrypt the original HPB item, and are used to restore the original HPB item. For example, if the encryption algorithm rotates the original HPB item to the left by 2 bits, the decryption algorithm rotates the encrypted HPB item to the right by 2 bits. If the encryption algorithm adds a certain value to the original HPB item, the decryption algorithm will encrypt the HPB item minus the certain value. If the encryption algorithm XORed the original HPB entry with a specific value, the decryption algorithm XORed the encrypted HPB entry one more time. If the encryption algorithm uses the preset rules to shuffle the original HPB items, the decryption algorithm uses the preset rules to unshuffle the original HPB items. In some embodiments, if the original HPB item implements group encryption, the processing unit 134 looks up the group encryption lookup table in the RAM 136 to obtain the encryption algorithm and encryption parameters of the group to which the LBA belongs, and then uses the corresponding decryption algorithm and decryption parameters are decrypted.

Referring to FIG. 10, RAM 136 may allocate space for decryption item area 1040, which may be a space of contiguous memory addresses. In the architecture shown in FIG. 1, the processing unit 134 can set the registers in the codec 138 to drive the codec 138, and read the content of the HPB entry as described above from the receive entry area 1030 of the RAM 136, according to the setting The parameter decrypts the HPB entry and stores the decrypted HPB entry in the decrypted entry area 1040 in the RAM 136 . After the codec 138 finishes decrypting the HPB item, it sends an interrupt to the processing unit 134 to notify the decryption completion message, so that the processing unit 134 can continue to process the decrypted HPB item. Alternatively, in the architecture shown in FIG. 2 , the processing unit 134 can load and execute the code of the decryption module to complete the above-mentioned operations.

Step S1240: Determine whether the HPB item is valid. If so, the flow continues to the process of step S1250; otherwise, the process continues to the process of step S1270. This step can be ignored if the original HPB item does not contain T2 form information. The processing unit 134 can determine whether the PBA information of the T2 table included in the decrypted HPB entry matches the address of the corresponding T1 table actually stored in the flash memory device 150 , and if it matches, it means that the HPB entry is valid.

Step S1250 : Read the user data of the requesting LBA from the PBA of the flash memory device 150 through the control logic 139 according to the PBA information of the T1 table of the decrypted HPB entry.

Step S1260: Send one or more data input UPIUs to the host 110 through the host interface 131, including the read user data.

Step S1270: Send a reply UPIU to the host 110 through the host interface 131, indicating that the reading fails. In other embodiments, the reply UPIU may include information suggesting that the host 110 update the HPB entry of the corresponding subregion, so that the host 110 can start the sending operations 755 and 757 as described above.

All or part of the steps in the method of the present invention can be implemented by computer instructions, such as a firmware translation layer (Firmware Translation Layer, FTL) in a storage device, a driver for a specific hardware, and the like. In addition, it can also be implemented in other types of programs. Those skilled in the art can compose the methods of the embodiments of the present invention into computer instructions, which will not be described for brevity. Computer instructions for implementing methods according to embodiments of the present invention may be stored in a suitable computer-readable medium, such as DVD, CD-ROM, USB disk, hard disk, or may be other suitable vehicles) to access the web server.

Although the above-described elements are included in FIGS. 1 to 3 , it is not excluded that more other additional elements can be used to achieve better technical effects without departing from the spirit of the invention. In addition, although the flowcharts of Fig. 9 and Fig. 12 are executed in the specified order, those skilled in the art can modify the order of these steps under the premise of achieving the same effect without violating the spirit of the invention. Therefore, The present invention is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the scope of the appended claims is to be construed in the broadest manner so as to encompass all obvious modifications and similar arrangements.

10,20: Electronic Devices 110: Host side 130,230: Flash Controller 131:Host Interface 132: Busbar 134: Processing unit 135: read-only memory 136: Random Access Memory 138: Codec 139: Control Logic 150: Flash device 151: Interface 153#0~153#15: NAND flash memory unit CH#0~CH#3: Channel CE#0~CE#3: Enable signal 310#1: Solid Block 410:T2 table 430#0~430#15: T1 table 510: Entity page 530: Physical address information 530-0: Entity block number 530-1: Entity page number 600:HPB cache 711~775, 811~837, 1110~1150: Operation S910~S960, S1210~S1270: method steps 1010~1040: Memory space

1 and 2 are system architecture diagrams of an electronic device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a flash memory device according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the association between the T1 table and the T2 table according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of an association between a T1 table and an entity page according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of establishment and application of a Host Performance Booster (HPB) cache according to an embodiment of the present invention.

FIG. 7 is an operation sequence diagram of an application in a host control mode according to an embodiment of the present invention.

FIG. 8 is an operation sequence diagram of an application in a device control mode according to an embodiment of the present invention.

FIG. 9 is a flowchart of a method for generating an HPB item according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of a memory space configuration according to an embodiment of the present invention.

FIG. 11 is an operation sequence diagram of reading HPB data according to an embodiment of the present invention.

FIG. 12 is a flowchart of a data reading method according to an embodiment of the present invention.

S910~S960: method steps

Claims (13)

A method of encrypting and decrypting physical address information, executed by a flash memory controller, includes: A first read command is received from a host, requesting to obtain a plurality of first physical block addresses corresponding to a logical block address range, wherein each of the first physical block addresses indicates the logic where the user data of a first logical block address in the block address interval is actually stored in a flash memory device; read the first physical block address corresponding to the logical block address interval from the flash memory device; Arranging the above-mentioned first physical block address into a plurality of items; encrypting the content of each of the above items using an encryption algorithm and an encryption parameter to obtain an encrypted item; and Send the above-mentioned encrypted project to the above-mentioned host terminal, so that the above-mentioned host terminal can send a second read command carrying the above-mentioned encrypted project to the above-mentioned flash memory controller, requesting to read a second physical block bit in the above-mentioned encrypted project A user profile for the address. The method for encrypting and decrypting entity address information as described in claim 1, comprising: Receive the above-mentioned second read command from the above-mentioned host side; Use a decryption algorithm and a decryption parameter to decrypt the encrypted item in the second read command to obtain a decrypted item, wherein the decryption algorithm and the decryption parameter are the reverse procedure of the encryption algorithm and the encryption parameter. ; Obtain the above-mentioned second physical block address from the above-mentioned decrypted project; read the user data from the second physical block address of the flash memory device; and Send the above-mentioned user data to the above-mentioned host. The method for encrypting and decrypting entity address information as described in claim 1, comprising: dividing the above-mentioned items into a plurality of groups according to the above-mentioned first logical block addresses; and The above items in the above groups are encrypted using a plurality of encryption algorithms and corresponding encryption parameters, respectively. The method for encrypting and decrypting entity address information as described in claim 3, comprising: Record the information that the above items of each group are encrypted using a specific encryption algorithm and specific encryption parameters. The method for encrypting and decrypting entity address information as described in claim 3, comprising: Receive the above-mentioned second read command from the above-mentioned host side; obtaining information about which group a second logical block address carried in the second read command belongs to; Decrypt the above-mentioned encrypted item in the above-mentioned second read command using a decryption algorithm belonging to the above-mentioned group and a decryption parameter to obtain a decrypted item, wherein the above-mentioned decryption algorithm and the above-mentioned decryption parameter are the above-mentioned encryption algorithm and the above-mentioned encryption Reverse procedure of parameters; Obtain the above-mentioned second physical block address from the above-mentioned decrypted project; read the user data from the second physical block address of the flash memory device; and Send the above-mentioned user data to the above-mentioned host. A device for encrypting and decrypting physical address information, comprising: a control logic, coupled to a flash memory device; a host interface, coupled to a host; and a processing unit, coupled to the control logic and the host interface, for receiving a first read command from the host through the host interface, requesting to obtain a plurality of first physical areas corresponding to a logical block address range block address, wherein each of the first physical block addresses indicates where the user data of a first logical block address in the logical block address interval is actually stored in the flash memory device; The control logic reads a first table from the flash memory device, the first table includes the first physical block addresses corresponding to the logical block address ranges; and arranges the first physical block addresses into a plurality of project; use an encryption algorithm and an encryption parameter to encrypt the content of each above-mentioned project to obtain an encrypted project; and transmit the above-mentioned encrypted project to the above-mentioned host terminal through the above-mentioned host interface, so that the above-mentioned host terminal can send the encrypted A second read command of the item is given to the processing unit to request to read a user data of a second physical block address in the encrypted item. The device for encrypting and decrypting physical address information according to claim 6, wherein the processing unit receives the second read command from the host through the host interface; decrypts the second read command using a decryption algorithm and a decryption parameter Read the above-mentioned encrypted items in the command to obtain a decrypted item, wherein the above-mentioned decryption algorithm and the above-mentioned decryption parameters are the reverse procedures of the above-mentioned encryption algorithm and the above-mentioned encryption parameters; Obtain the above-mentioned second physical block from the above-mentioned decrypted project address; read the user data from the second physical block address of the flash memory device through the control logic; and transmit the user data to the host through the host interface. The device for encrypting and decrypting physical address information as claimed in claim 6, wherein the processing unit divides the items into a plurality of groups according to the first logical block address; and uses a plurality of encryption algorithms and corresponding encryption algorithms respectively. The parameters encrypt the above items in the above groups. The apparatus for encrypting and decrypting physical address information as claimed in claim 8, wherein the processing unit records the information that the items of each group are encrypted using a specific encryption algorithm and a specific encryption parameter. The device for encrypting and decrypting physical address information according to claim 8, wherein the processing unit receives the second read command from the host through the host interface; obtains a first read command carried in the second read command Information about which group the two logical block addresses belong to; use a decryption algorithm and a decryption parameter belonging to the group to decrypt the encrypted item in the second read command to obtain a decrypted item, wherein the decryption algorithm And above-mentioned decryption parameter is the reverse procedure of above-mentioned encryption algorithm and above-mentioned encryption parameter; Obtain above-mentioned second physical block address from above-mentioned deciphered project; Read above-mentioned second physical block address from above-mentioned flash memory device through above-mentioned control logic Obtaining the above-mentioned user data; and transmitting the above-mentioned user data to the above-mentioned host through the above-mentioned host interface. The device for encrypting and decrypting physical address information according to claim 8, wherein the processing unit receives the second read command from the host through the host interface; obtains a first read command carried in the second read command Information about which group the two logical block addresses belong to; use a decryption algorithm and a decryption parameter belonging to the group to decrypt the encrypted item in the second read command to obtain a decrypted item, wherein the decryption algorithm And above-mentioned decryption parameter is the reverse program of above-mentioned encryption algorithm and above-mentioned encryption parameter; Obtain a physical block address of above-mentioned first table from the above-mentioned after-decryption project; Judge above-mentioned decryption according to the above-mentioned physical block address of above-mentioned first table Whether the latter item is valid; when the decrypted item is valid, read the user data from the second physical block address of the flash memory device through the control logic, and transmit the user data to the host through the host interface end. The device for encrypting and decrypting physical address information according to claim 11, wherein when the decrypted item is invalid, the processing unit transmits a read failure message to the host through the host interface. The device for encrypting and decrypting physical address information according to claim 11, wherein when the decrypted item is invalid, the processing unit recommends the host to update the logical block address in a cache through the host interface The above-mentioned first physical block address of the interval.

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