CN113704145B - Method and device for encrypting and decrypting physical address information - Google Patents

Abstract

The invention relates to a method and a device for encrypting and decrypting physical address information, wherein the method for encrypting and decrypting the physical address information is executed by a flash memory controller and comprises the following steps: receiving a read command from a host, requesting to read a plurality of physical block addresses corresponding to a section of logical block address interval; reading a physical block address corresponding to the logical block address range from the flash memory device; arranging the physical block address into a plurality of items; encrypting the content of each item using an encryption algorithm and encryption parameters to obtain an encrypted item; and transmitting the encrypted item to the host side. The invention can prevent illegal personnel from knowing the internal data management mode of the device end by snooping the physical address through the host end by encrypting the project containing the physical block address.

Description

Method and device for encrypting and decrypting physical address information

Technical Field

The present invention relates to a storage device, and more particularly, to a method and apparatus for encrypting and decrypting physical address information.

Background

Flash memory is generally classified into NOR flash memory and NAND flash memory. The NOR flash memory is a random access device, and a central processing unit (Host) can provide any address accessing the NOR flash memory on an address pin, and timely obtain data stored on the address from a data pin of the NOR flash memory. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory, like NOR flash memory, cannot access any random addresses, but instead the cpu needs to write serial byte values into the NAND flash memory for defining the type of Command (Command) (e.g., read, write, erase, etc.), and the address used on the Command. The address may point to one page (the smallest block of data for a write operation in flash) or one block (the smallest block of data for an erase operation in flash).

In order to improve the data writing and reading performance of the flash memory module, the device side performs data writing and reading in parallel through a plurality of channels. In order to achieve the purpose of parallel processing, a continuous segment of data is stored in a distributed manner in a flash memory unit connected to a plurality of channels, and a Logical-to-physical (L2P Mapping Table) is used to record the correspondence between the Logical address (managed by the host) and the physical address (managed by the flash memory controller) of the user data. Still further, in the new specification, the flash memory controller can sort the correspondence between logical addresses and physical addresses into the format of the host performance enhancer items (Host Performance Booster, HPB Entries) and provide them to the host side. Then, the host side can fetch the required physical address from the HPB entry and carry the physical address in the HPB read command sent to the device side, so that the flash memory controller can directly read the user data from the physical address of the flash memory module and reply to the host side, without the time and operation resources being required to read the logical-physical comparison table from the flash memory module and perform logical-physical address conversion as before. However, the physical addresses of the HPB items are stored in a clear form, so that an illegitimate person can know the internal data management manner of the device side by snooping the physical addresses at the host side, and use an illegal means to acquire sensitive data (e.g., system or management data). Therefore, the invention provides a method and a device for encrypting and decrypting physical address information, which are used for improving data security.

Disclosure of Invention

In view of this, how to alleviate or eliminate the above-mentioned drawbacks of the related art is a real problem to be solved.

The invention relates to a method for encrypting and decrypting physical address information, which is executed by a flash memory controller and comprises the following steps: receiving a read command from a host end, requesting to acquire a plurality of physical block addresses corresponding to a section of logical block address interval; reading a physical block address corresponding to the logical block address range from the flash memory device; arranging the physical block address into a plurality of items; encrypting the content of each item using an encryption algorithm and encryption parameters to obtain an encrypted item; and transmitting the encrypted item to the host side.

The invention also relates to a device for encrypting and decrypting physical address information, comprising: control logic; a host interface; and a processing unit. The processing unit is used for receiving a read command from a host end through a host interface and requesting to acquire a plurality of physical block addresses corresponding to a section of logical block address interval; reading a first table from the flash memory device by the control logic, the first table including a plurality of first physical block addresses corresponding to the logical block address intervals; the first physical block address is organized into a plurality of items; encrypting the content of each item using an encryption algorithm and encryption parameters to obtain an encrypted item; and transmitting the encrypted item to the host side through the host interface.

Each first physical block address indicates where user data for a particular logical block address in the logical block address interval is actually stored in the flash memory device.

One of the advantages of the above embodiment is that by encrypting the item containing the physical block address, an illegal person can be prevented from knowing the internal data management mode of the device by the host side snooping the physical address.

Other advantages of the present invention will be explained in more detail in connection with the following description and accompanying drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application.

Fig. 1 and fig. 2 are system architecture diagrams of an electronic device according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a flash memory device according to an embodiment of the invention.

FIG. 4 is a diagram illustrating the association between the T1 table and the T2 table according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating the association between a T1 table and a physical page according to an embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating the creation and utilization of a host performance enhancer (Host Performance Booster, HPB) cache in accordance with an embodiment of the invention.

FIG. 7 is a sequence diagram illustrating an operation of the host control mode according to an embodiment of the present invention.

Fig. 8 is a sequence diagram illustrating an operation of the device control mode according to an embodiment of the present invention.

FIG. 9 is a flowchart of a method for generating HPB items in accordance with an embodiment of the invention.

FIG. 10 is a diagram illustrating a memory space configuration according to an embodiment of the invention.

FIG. 11 is a sequence diagram illustrating an HPB data read operation in accordance with an embodiment of the invention.

FIG. 12 is a flow chart of a method for reading data according to an embodiment of the invention.

Wherein the symbols in the drawings are briefly described as follows:

10. 20: an electronic device; 110: a host end; 130. 230: a flash memory controller; 131: a host interface; 132: a bus; 134: a processing unit; 135: a read-only memory; 136: a random access memory; 138: a codec; 139: control logic; 150: a flash memory device; 151: an interface; 153#0 to 153#15: a NAND flash memory cell; ch#0 to ch#3: a channel; ce#0 to ce#3: a start signal; 310#1: a physical block; 410: t2 table; 430#0 to 430#15: t1 table; 510: a physical page; 530: physical address information; 530-0: a physical block number; 530-1: physical page numbering; 600: HPB buffering; 711 to 775, 811 to 837, 1110 to 1150: operating; s910 to S960, S1210 to S1270: the method comprises the steps of; 1010-1040: a memory space.

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, like reference numerals designate identical or similar components or process flows.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, values, method steps, operation processes, components, and/or groups, but do not preclude the addition of further features, values, method steps, operation processes, components, groups, or groups of the above.

In the present invention, terms such as "first," "second," "third," and the like are used for modifying elements of the claims, and are not intended to denote a prior order, a first order, or a sequence of steps of a method, for example, for distinguishing between elements having the same name.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between components may also be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

Reference is made to fig. 1. The electronic Device 10 includes a host Device (also referred to as a host Side) 110, a flash controller 130, and a flash Device 150, and the flash controller 130 and the flash Device 150 may be collectively referred to as a Device Side (Device Side). The electronic device 10 may be implemented in an electronic product such as a personal computer, a notebook computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, and the like. The Host device 110 and a Host Interface (Host Interface) 131 of the flash controller 130 may communicate with each other in a communication protocol such as universal flash memory storage (Universal Flash Storage, UFS). While the following embodiments describe the functionality of the host performance enhancer (Host Performance Booster, HPB) of the UFS specification, the present invention is not so limited as those skilled in the art may apply the present invention to similar functionality of other specifications. The control logic 139 of the flash controller 130 and the flash device 150 may communicate with each other in a Double Data Rate (DDR) communication protocol, such as an open NAND flash interface (Open NAND Flash Interface, ONFI), a Double Data Rate switch (DDR Toggle), or other communication protocol. The flash controller 130 includes a processing unit 134 that may be implemented in a variety of ways, such as using general-purpose hardware (e.g., a micro-control unit, a central processing unit, a multiprocessor having parallel processing capabilities, a graphics processor, or other processor having arithmetic capabilities), and provides the functionality described below when executing software and/or firmware instructions. The processing unit 134 receives HPB commands, such as an HPB READ Command (HPB READ Command), an HPB READ buffer Command (HPB READ BUFFER Command), an HPB write buffer Command (HPB WRITE BUFFER Command), and the like, through the host interface 131, and executes these commands. The flash controller 130 includes random access memory (Random Access Memory, RAM) 136, which may be implemented as dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), or a combination of both, for configuring space as a data buffer. The RAM 136 may also store data, such as variables, tables of data, etc., that are needed during execution. The flash controller 130 includes a Read Only Memory (ROM) 135 for storing program codes that need to be executed when the device is turned on. Control logic 139 includes a NAND flash controller (NAND Flash Controller, NFC) that provides the functions required when accessing flash device 150, such as command serializer (Command Sequencer), low density parity check (Low Density Parity Check, LDPC), etc.

Flash controller 130 includes a Codec 138, which is a special purpose hardware that includes encoding logic for encrypting the original HPB item; and decode logic to decrypt the encrypted content for restoring the original HPB item. The following paragraphs detail the structure, function, and interaction of the codec 138 with other components.

A Bus Architecture (Bus Architecture) 132 may be configured in the flash memory controller 130 for coupling components including a host interface 131, a processing unit 134, a RAM 136, a codec 138, control logic 139, etc., to each other for transferring data, addresses, control signals, etc. In some embodiments, host interface 131, processing unit 134, RAM 136, codec 138, and control logic 139 may be coupled to one another by a single bus. In other embodiments, a high-speed bus may be configured in flash controller 130 for coupling processing unit 134, codec 138 and RAM 136 to each other, and a low-speed bus may be configured for coupling processing unit 134, codec 138, host interface 131 and control logic 139 to each other. The bus includes parallel physical lines that connect two or more components in the flash controller 130.

Flash memory device 150 provides a large amount of storage space, typically hundreds of Gigabytes (GB), even a few megabytes (TB), for storing large amounts of user data, such as high resolution pictures, movies, and the like. The flash memory device 150 includes a control circuit and a memory array, wherein the memory Cells in the memory array may include single-layer Cells (Single Level Cells, SLCs), multi-layer Cells (Multiple Level Cells, MLCs), triple-layer Cells (Triple Level Cells, TLCs), quad-layer Cells (QLCs), or any combination thereof. The processing unit 134 writes the user data to a specified address (destination address) in the flash memory device 150 through the control logic 139, and reads the user data and a specified portion in the L2P lookup table from the specified address (source address) in the flash memory device 150. The Control logic 139 coordinates Data and command transfers between the flash controller 130 and the flash device 150 using a plurality of electronic signals, including Data lines (Data lines), clock signals (Clock signals), and Control signals (Control signals). The data line can be used for transmitting commands, addresses, read-out and written data; the control signal lines may be used to transmit control signals such as Chip Enable (CE), address fetch Enable (Address Latch Enable, ALE), command fetch Enable (Command Latch Enable, CLE), write Enable (WE), and the like.

In other embodiments, referring to FIG. 2, the electronic device 20 includes a modified flash controller 230 that does not include the codec 138 of FIG. 1. In flash controller 230, the functions of codec 138 may be replaced with software or firmware instructions and, when loaded and executed by processing unit 134, perform encrypting the original HPB items and decrypting the encrypted content for restoring the original HPB items. In other words, fig. 1 contains a solution using hardware for encryption and decryption, while fig. 2 contains a solution using software for encryption and decryption.

Referring to fig. 3, the interface 151 in the flash memory device 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) ch#0 to ch#3, each of which connects four NAND flash memory units, for example, the channel ch#0 connects the NAND flash memory units 153#0, 153#4, 153#8, and 153#12. Each NAND flash memory cell may be packaged as a separate chip (die). The control logic 139 may initiate the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the initiation signals ce#0 to ce#3 through the interface 151, and then read user data from the initiated NAND flash memory units or write user data to the initiated NAND flash memory units in a parallel manner.

Since a continuous piece of data (i.e., a continuous piece of data of Logical addresses) is stored in the flash memory unit to which the plurality of channels are connected in a distributed manner, the flash memory controller 130 records the correspondence between the Logical address (managed by the host device 110) and the physical address (managed by the flash memory controller 130) of the user data using a Logical-to-physical (L2P Mapping Table). The L2P lookup Table may also be referred to as a Host flash lookup Table (H2F Mapping Table). The H2F comparison table contains a plurality of records, and information of which physical address the user data of each logical address is actually stored in is stored according to the sequence of the logical addresses. However, since the RAM 136 cannot provide enough space to store the entire H2F lookup Table for the processing unit 134 to quickly look up in the future during the data read operation, the H2F lookup Table may be cut into a plurality of first tables (Table 1, which may also be referred to as T1 tables) and stored in the nonvolatile flash memory device 150, so that only the corresponding T1 Table is read from the flash memory device 150 to the RAM 136 in the future during the data read operation. Referring to FIG. 4, the entire H2F look-up table may be cut into T1 tables 430#0-430#15. The processing unit 134 also maintains a second Table (Table 2, also referred to as a T2 Table) 410 containing a plurality of records storing physical address information of the T1 Table associated with each logical address segment in the order of logical addresses. For example, the associated T1 table 430#0 of logical block addresses (Logical Block Addresses, LBAs) 0 through 4095 is stored in the 0 th physical page in a particular physical block of a particular logical unit number (Logical Unit Number, LUN) (the letter "Z" may represent the number of LUNs and physical blocks), the associated T1 table 430#1 of LBAs 4096 through 8191 is stored in the 1 st physical page in a particular physical block of a particular LUN, and so on. Although fig. 4 only includes 16T 1 tables, those skilled in the art may set more T1 tables according to the capacity of the flash memory device 150, and the present invention is not limited thereto.

The space required for each T1 table may be 4KB, 8KB, 16KB, etc. Each T1 table stores physical address information corresponding to each LBA in order of LBAs, and each LBA corresponds to a fixed-size physical storage space, for example, 4KB. Referring to fig. 5, for example, the T1 table 430#0 sequentially stores physical address information from lba#0 to lba#4095. The physical address information 530 may be represented in four bytes: the first two bytes 530-0 record the physical block number (Physical Block Number); the last two bytes 530-1 record the physical page number (Physical Page Number). For example, the physical address information 530 corresponding to LBA#2 may point to physical page 510 in physical block 310#1. Byte 530-0 records the number of physical block 310#1 and byte 530-1 records the number of physical page 510.

Referring to fig. 6, in the HPB specification, the host 110 configures space in its System Memory (System Memory) as an HPB cache 600 for temporarily storing information of an H2F lookup table maintained by the device. HPB cache 600 stores a plurality of HPB Entries (HPB Entries) received from the device side, each HPB entry recording information corresponding to a physical address of an LBA. Then, the host 110 may issue an HPB read command carrying the HPB entry to the device for obtaining the user data of the specified LBA. The device side can directly drive the control logic 139 to read the user data of the specified LBA from the flash memory device 150 according to the information in the HPB entry, without taking time and computing resources to read the H2F lookup table from the flash memory device 150 and performing logical-to-physical address conversion as before to read the user data of the specified LBA from the flash memory device 150. For the establishment and use of HPB cache 600, three phases may be distinguished:

Stage I (HBP initialization): the host 110 requests the device (specifically, the flash controller 130) to acquire its device capabilities and configures HBP functions, including HPB Mode (Mode) and the like.

Stage II (L2P cache management): host side 110 configures space in system memory as HPB cache 600 for storing HPB items. The host side 110 may send an HPB read buffer command (HPB READ BUFFER Command) to the flash controller 130 at a desired point in time in the configured mode for loading the specified HPB item from the device side. Next, host side 110 stores these HPB entries in one or more Sub-Regions (Sub-Regions) in HPB cache 600. In the HPB specification, LBAs for each logical unit (e.g., sector, partition) are divided into multiple HPB parts, and each HPB part may be further subdivided into multiple sub-regions. For example, HPB cache 600 may include N HPB portions, and each HPB portion may include L sub-regions, where variables "N" and "L" are positive integers, for storing HPB entries for a segment of LBA intervals. An example of the partitioning of HPB cache 600 is shown in Table 1:

TABLE 1

In some embodiments, the parts and sub-regions may be set to have a space of 32MB, that is, each part contains only one sub-region. In other embodiments, the partition may be set to have a space of 32MB, and the sub-region may be set to have a space of 4MB, 8MB, or 16 MB. That is, each part may contain eight, four or two sub-regions.

Stage III (HPB read command): the host 110 searches the HPB entry of the HPB cache 600 for the HPB entry including the physical block address (Physical Block Addresses, PBAs) of the data of the LBA to be read. Next, the host 110 sends an HPB READ Command (HPB READ Command) to the flash controller 130, which includes HPB entries in addition to LBA, transfer length (TRANSFER LENGTH), etc., for obtaining specified user data from the device.

However, conventionally, the information of the PBA is included in the HPB entry in a clear manner, so that an illegal person can know the internal data management manner of the device side by snooping the information of the PBA through the host side 110, and can acquire sensitive data (e.g., system or management data) by using an illegal means.

The HPB specification defines two modes of fetching HPB items: a host control mode (Host Control Mode) and a device control mode (Device Control Mode). The host control mode is triggered by the host side 110 to determine which HPB subregions need to be stored in the HPB cache 600; the device control mode is triggered by the flash controller 130 to determine which HPB sub-regions need to be stored in the HPB cache 600. Those skilled in the art will appreciate that embodiments of the present invention contemplate these two or other similar modes of control.

Referring to the operation sequence diagram applied in the host control mode as shown in fig. 7, the following is described in detail:

operation 711: the host 110 decides which sub-regions are about to be started (Activated).

Operation 713: the host side 110 sends an HPB read buffer command to the flash controller 130 requesting the flash controller 130 for the HPB entry of the determinant region. The HPB read buffer command may comprise 10 bytes, with the 0 th byte record opcode (Operation Code) "F9h", the 2 nd and 3 rd bytes record information about to start the HPB local, and the 4 th and 5 th bytes record information about to start the sub-area.

Operation 715: the flash controller 130 reads a specific portion of the H2F lookup table from the flash memory device 150 and organizes the read lookup information into HPB entries. To avoid PBA information in the HPB item being snooped by unauthorized personnel to learn the internal management of the data store, flash controller 130 encrypts the contents of the HPB item. The following paragraphs describe the read operation of this step in more detail.

Operation 717: the flash controller 130 transmits a data input UFS protocol information unit (DATA IN UFS Protocol Information Unit, UPIU) to the host 110, which contains the encrypted content of the HPB entry of the determinant area, instead of the plaintext.

Operation 719: host side 110 stores the received encrypted HPB item into a promoter region in HPB cache 600.

Operation 731: the host 110 determines which parts are about to be shut down (Deactivated). It should be noted that in the HPB specification, the start-up is in the sub-region unit and the shutdown is in the local unit, and the host 110 may determine the sub-region to be started and the local to be shut down according to the algorithm requirement.

Operation 733: the host 110 sends an HPB write buffer command (HPB WRITE BUFFER Command) to the flash controller 130, informing the flash controller 130 of the local shutdown decision. The HPB read buffer command may comprise 10 bytes, with byte 0 recording the opcode "FAh" and byte 2 and byte 3 recording the information about the impending shutdown portion.

Operation 735: the flash controller 130 turns off the part. For example, after the HPB entry is transferred to the host 110 by the flash controller 130, the flash controller 130 may perform the optimization operation on the read flow of the subsequent read command of the host 110 for the started sub-region, and after receiving the notification of the shutdown region local of the host 110, the flash controller 130 may terminate the related optimization operation corresponding to the shutdown region.

Operation 751: after performing the host write command, the host erase command, or the background operation (e.g., garbage collection, wear leveling, read collection, read refresh, etc.), the flash memory controller 130 updates the contents of the H2F lookup table, including the contents corresponding to the promoter region.

Operation 753: the flash controller 130 transmits a reply UFS protocol information unit (RESPONSE UPIU) to the host 110, which includes information that suggests the host 110 to update the HPB entry of the subzone.

Operations 755 and 757: the host side 110 sends an HPB read buffer command to the flash controller 130 requesting the flash controller 130 for the HPB entry of the suggested subregion.

Operation 771: the flash controller 130 reads a specific portion of the H2F lookup table from the flash memory device 150 and organizes the read lookup information into HPB entries. Similarly, the flash controller 130 also encrypts the content of the HPB item. The following paragraphs describe the read operation of this step in more detail.

Operation 773: the flash controller 130 transmits a data input UPIU to the host 110, which contains the encrypted content of the HPB entry of the update sub-area, instead of the plaintext.

Operation 775: host side 110 overwrites the received encrypted HPB item with the contents of the initiator area of HPB cache 600.

Referring to the operation sequence diagram applied in the device control mode as shown in fig. 8, the following is described in detail:

operation 811: the flash controller 130 decides which sub-regions are about to start and/or which parts are about to shut down.

Operation 813: the flash controller 130 transmits a reply UPIU to the host 110, wherein the host 110 is recommended to start the sub-area and/or shut down the part.

Operation 815: if necessary, host side 110 discards HPB entries from the system memory that are no longer valid HPB local.

Operation 831: if necessary, host side 110 sends an HPB read buffer command to flash controller 130 requesting the HPB entry of the suggested subregion from flash controller 130.

Operation 833: the flash controller 130 reads a specific portion of the H2F lookup table from the flash memory device 150 and organizes the read lookup information into HPB entries. Similarly, the flash controller 130 also encrypts the content of the HPB item. The following paragraphs describe the read operation of this step in more detail.

Operation 835: the flash controller 130 transmits a data input UPIU to the host 110, which contains encrypted content of the HPB entry corresponding to the sub-region, instead of a plain code.

Operation 837: host side 110 stores the received encrypted HPB item into a promoter region in HPB cache 600.

For technical details regarding the read operations 715, 771, or 833, reference is made to a flowchart of an HPB item generating method shown in fig. 9, which is implemented by the processing unit 134 when loading and executing relevant software or firmware program code, and further described below:

step S910: the HPB read buffer command as described above, including information of the upcoming promoter region, is received from the host side 110 via the host interface 131. The HPB read buffer command requests the flash controller 130 to read the PBA for a segment of the LBA interval.

Step S920: the specific T1 table and T2 table corresponding to the promoter regions are read from flash memory device 150 by control logic 139.

Step S930: HPB entries are organized according to the contents of the T1 and T2 tables. Those skilled in the art will appreciate that the length (e.g., 8 bytes) of each HPB entry of the HPB specification may be greater than the length (e.g., 4 bytes) of the physical address information associated with each LBA recorded in the T1 table. Thus, in some embodiments, in addition to the physical address information of each LBA (i.e., the PBA information of this LBA recorded in the T1 table), processing unit 134 may add a Dummy value (Dummy Values) to the remaining space of the HPB entry to fill the HPB entry. In other embodiments, in addition to the physical address information for each LBA, processing unit 134 adds other information in the remaining space of the HPB project depending on the different system requirements for speeding up future HPB read operations.

In some embodiments, processing unit 134 may populate each 8-byte HPB entry with the corresponding PBA information of the 4-byte T1 table and the corresponding PBA information of the 4-byte T2 table. The PBA information of the T1 table indicates information associated with where the particular LBA is actually present in the flash memory device 150, while the PBA information of the T2 table indicates information of where this T1 table is actually present in the flash memory device 150. The PBA information of the T2 table may be checked by the device side in the future whether this HPB entry is invalid. If the PBA information of the T2 table contained in the HPB entry obtained from the HPB read command in the future does not match the address where the corresponding T1 table is actually stored in the flash memory device 150, the processing unit 134 determines that the HPB entry is invalid. Examples of HPB items are shown in table 2:

TABLE 2

In other embodiments, processing unit 134 may populate each 8-byte HPB entry with the corresponding PBA information of the 28-bit T1 table, the corresponding PBA information of the 24-bit T2 table, and the 12-bit contiguous length (Continuous Length). The continuous length indicates how many LBAs of data following this LBA are physical addresses that are stored continuously in flash memory device 150. Therefore, one HPB entry can express information of multiple consecutive PBAs in the T1 table. Examples of HPB items are shown in table 3:

TABLE 3 Table 3

Suppose the 0 th HPB entry in Table 3 is associated with LBA "0x001000": the 0 th HPB entry indicates that user data having five LBAs after LBA "0x001000" is a physical address continuously stored in the flash memory device 150. In detail, the data of LBA "0x001000" to LBA "0x001005" are stored in PBA "0x00a000" to PBA "0x00a005" in the flash memory device 150, respectively. The processing unit 134 is able to read user data of six LBAs "0x001000" to "0x001005" from the information carried in the 0 th HPB entry in the future. If the HPB read command indicates that the LBA to be read is "0x001000" and the transfer length is less than or equal to "6", the processing unit 134 does not need to read the corresponding portion of the H2F lookup table from the flash memory device 150.

In other embodiments, processing unit 134 may populate each 8-byte HPB entry with corresponding PBA information for a 28-bit T1 table, corresponding PBA information for a 24-bit T2 table, and a 12-bit sequential bit table (Continuous Bit Table). The continuous bit table is used to represent the PBA continuity for multiple subsequent LBAs (e.g., 12 subsequent LBAs) for this LBA. For example, 12 bits correspond to 12 subsequent LBAs, respectively. Examples of HPB items are shown in table 4:

TABLE 4 Table 4

Suppose the 0 th HPB entry in Table 4 is associated with LBA "0x001000": the consecutive bit table of the 0 th HPB entry indicates the PBA continuity of LBAs "0x001001" through "0x 00100C". Ideally, the data of LBAs "0x001001" to "0x00100C" should be stored in PBAs "0x000A001" to "0x000A00C" of flash memory device 150, respectively. The data representing the corresponding LBA is not stored in the ideal PBA when the value of each bit is "0", and the data representing the corresponding LBA is stored in the ideal PBA when the value of each bit is "1". Therefore, according to the 0 th HPB entry, the processing unit 134 is able to predict the PBA with the consecutive bit of "1" and read the data of the LBA from the PBA of the flash memory device 150 in the future, but ignore the PBA with the consecutive bit of "0". For example, if the host device 110 sends an HPB read command with a parameter carrying the 0 th HPB entry and a transfer length of "9" for requesting user data for LBAs "0x001000" through "0x 001008". The processing unit 134 obtains the consecutive bit table in the 0 th HPB entry of the HPB read command, and predicts that the data of LBAs "0x001000" to "0x001005" and LBAs "0x001007" to "0x001008" are actually stored in the PBA of the flash memory device 150 after decoding the consecutive bit table, without loading the H2F lookup table from the flash memory device 150. In the case of only a few breakpoints, the number of times specific PBA information of the T1 table is loaded from the flash memory device 150 can be reduced.

Step S940: the original HPB items are stored to RAM 136. Referring to FIG. 10, RAM 136 may allocate space to original project area 1010, which may be a space of consecutive memory addresses. The processing unit 134 may sequentially store the original HPB entries into the original entry region 1010 in the RAM 136 according to the order of LBAs.

Step S950: the HPB item is encrypted and the encrypted HPB item is stored in RAM 136. Referring to FIG. 10, RAM 136 may allocate space to encryption entry area 1020, which may be a space of consecutive memory addresses. In the architecture shown in FIG. 1, the processing unit 134 may set registers in the codec 138 to drive the codec 138, read the content of the HPB item as described above from the original item area 1010 of the RAM 136, encrypt the HPB item according to the set parameters, and store the encrypted HPB item in the encrypted item area 1020 in the RAM 136. After the encryption of the HPB item is performed by the codec 138, an Interrupt (Interrupt) is issued to the processing unit 134 to notify the processing unit 134 of the completion of the encryption, so that the processing unit 134 can continue to process the encrypted HPB item. Alternatively, in an architecture such as that shown in FIG. 2, the processing unit 134 may load and execute the program code of the encryption module to perform the operations described above.

Examples of encryption algorithms that can be used are as follows: in some embodiments, processing unit 134 or codec 138 cyclically shifts the content of the HPB item left or right by n bits, n representing any integer from 1 to 63. In other embodiments, processing unit 134 or codec 138 adds the content of the HPB item to the default key value. In other embodiments, processing unit 134 OR codec 138 performs Exclusive OR (XOR) operations on the contents of the HPB item and the default key value. In other embodiments, the processing unit 134 or the codec 138 is out of order (random) with a default rule. For example, the default rule may be the i-th bit and the 63-i-th bit of the HPB entry, i from "0" to "31".

To further enhance data security, the HPB entries of a sub-region may be divided into multiple groups according to LBAs, and the HPB entries of the different groups may be encrypted using different encryption algorithms and corresponding encryption parameters, respectively. The HPB project grouping rules are exemplified as follows: in some embodiments, the LBAs associated with HPB items may be divided by a value and the HPB items clustered according to their quotient (quantum). Assume that this value is set to "100": the first group contains HPB entries for LBAs # 0-99, the second group contains HPB entries for LBAs # 100-199, and so on. In other embodiments, the LBA associated with an HPB item may be divided by a value and the HPB items clustered according to their remainder (Remainders). Assume that this value is set to "100": the first group contains HPB entries for LBA#0, LBA#100, LBA#200, etc., the second group contains HPB entries for LBA#1, LBA#101, LBA#201, etc., and so on.

In some embodiments, different groups of HPB items may use the same encryption algorithm but brought into different encryption parameters, respectively. For example, the contents of each HPB project of the first group are cyclically shifted 1 bit to the left, the contents of each HPB project of the second group are cyclically shifted 2 bits to the right, the contents of each HPB project of the third group are cyclically shifted 3 bits to the left, and so on. Alternatively, the contents of each HPB item of the first group is added to or XOR ' ed with the first value, the contents of each HPB item of the second group is added to or XOR ' ed with the second value, the contents of each HPB item of the third group is added to or XOR ' ed with the third value, and so on. Still alternatively, the contents of each HPB item of the first group are out of order by a first rule, the contents of each HPB item of the second group are out of order by a second rule, the contents of each HPB item of the third group are out of order by a third rule, and so on.

In other embodiments, different groups of HPB items may each use different encryption algorithms and bring in appropriate encryption parameters. For example, the contents of each HPB item of the first group are cyclically shifted to the left by n bits, the contents of each HPB item of the second group are XOR' ed with a default value, the contents of each HPB item of the third group are plus a particular value, the contents of each HPB item of the fourth group are out of order by a default rule, and so on.

In some embodiments, processing unit 134 may store a Group-and-encryption Mapping Table (Group-encryption-lookup table) in RAM 136, containing a plurality of configuration records. Each configuration record stores information indicating which encryption algorithm and corresponding encryption parameters are used for a particular group of HPB items. In other embodiments, information like the group encryption look-up table may also be embedded in the program logic executed by the processing unit 134, and the invention is not so limited.

Step S960: the encrypted HPB item is read from the encrypted item area 1020 in the RAM 136 and the data input UPIU is transferred to the host side 110, which contains the encrypted HPB item. When the content of the HPB item is encrypted, an illegal person cannot understand the content of the HPB item through the host side 110 and accordingly knows the internal data management manner of the device side, so that the illegal person can be prevented from using an illegal means to acquire the sensitive data. Although the HPB items are encrypted, the host side 110 may still obtain the desired user data from the device side as long as the encrypted HPB items are carried in HPB read commands in the future.

Referring to the operation sequence diagram of the HPB data reading as shown in fig. 11, the following is explained in detail:

Operation 1110: the host side 110 obtains the HPB entry corresponding to the LBA to be read from the HPB cache 600. It should be noted that the contents of these HPB items are already encrypted.

Operation 1120: the host 110 sends an HPB read command to the flash controller 130, requesting user data specifying the LBA, including the LBA, the transfer length, and the HPB entry, from the flash controller 130.

Operation 1130: flash controller 130 decrypts the contents of the HPB project and reads the requested user data from flash device 150 based on the PBA information of the T1 table of the HPB project (plus a continuous length or continuous bit table, if desired).

Operation 1140: the flash controller 130 transmits a data input UPIU to the host 110, which contains the requested user data.

Operation 1150: the host side 110 processes the user data according to the needs of the operating system, drivers, applications, etc.

For technical details regarding the read operation 1130, reference is made to the flowchart of the data read method shown in fig. 12, which is implemented by the processing unit 134 when loading and executing the relevant software or firmware program code, as further described below:

step S1210: an HPB read command is received from the host side 110 via the host interface 131, which includes information such as LBA, transfer length, and HPB entry. Referring to FIG. 10, RAM 136 may allocate space to a received items area 1030, which may be a space of consecutive memory addresses, for storing received HPB items.

Step S1220: if the original HPB item has the group encryption implemented, the group to which the HPB item belongs is obtained according to the LBA in the HPB read command. The details of the LBA group can be referred to in step S950, and are not repeated for brevity. This step can be omitted if the original HPB item did not implement cluster encryption.

Step S1230: the HPB item is decrypted using the corresponding decryption algorithm and decryption parameters. The decryption algorithm and decryption parameters described above are the Reverse procedures (Reverse processes) of the encryption algorithm and encryption parameters used to originally encrypt the HPB item, and are used to recover the original HPB item. For example, if the encryption algorithm left-shifts the original HPB project cycle by 2 bits, the decryption algorithm right-shifts the encrypted HPB project cycle by 2 bits. If the encryption algorithm adds a specific value to the original HPB item, the decryption algorithm subtracts the specific value from the encrypted HPB item. If the encryption algorithm xored the original HPB entry with a particular value, the decryption algorithm xored the encrypted HPB entry once more. If the encryption algorithm uses default rules to shuffle the original HPB items, the decryption algorithm uses default rules to de-shuffle the original HPB items. In some embodiments, if the original HPB entry is subject to group encryption, processing unit 134 looks up the group encryption look-up table in RAM 136 to obtain the encryption algorithm and encryption parameters for the group to which the LBA belongs, and then decrypts using the corresponding decryption algorithm and decryption parameters.

Referring to fig. 10, ram 136 may allocate space to decryption item area 1040, which may be a space of consecutive memory addresses. In the architecture shown in FIG. 1, the processing unit 134 may set registers in the codec 138 to drive the codec 138, read the content of the HPB item as described above from the received item area 1030 of the RAM 136, decrypt the HPB item according to the set parameters, and store the decrypted HPB item in the decrypted item area 1040 in the RAM 136. After the codec 138 has performed decryption of the HPB entry, an interrupt is issued to the processing unit 134 to notify the processing unit 134 of the decryption completion so that the processing unit 134 can continue processing the decrypted HPB entry. Alternatively, in an architecture such as that shown in FIG. 2, processing unit 134 may load and execute the program code of the decryption module to perform the operations described above.

Step S1240: it is determined whether the HPB item is valid. If so, the flow continues with the process of step S1250; otherwise, the process of step S1270 is continued. This step may be omitted if the original HPB entry does not contain information from the T2 table. The processing unit 134 may determine whether the PBA information of the T2 table included in the decrypted HPB entry matches the address of the corresponding T1 table actually stored in the flash memory device 150, and if so, it indicates that the HPB entry is valid.

Step S1250: user data requesting LBAs is read from the PBA of flash memory device 150 by control logic 139 based on the PBA information of the T1 table of the decrypted HPB entry.

Step S1260: one or more data inputs UPIU are transmitted to the host side 110 via the host interface 131, which contains the read user data.

Step S1270: the reply UPIU is transmitted to the host side 110 through the host interface 131, indicating that the read failed. In other embodiments, the reply UPIU may contain information that suggests the host side 110 to update the HPB entry for the corresponding subregion, enabling the host side 110 to begin the send operations 755 and 757 as described above.

All or part of the steps in the method described in the present invention may be implemented by a computer program, for example, a driver of specific hardware, or a software program. In addition, other types of programs as shown above may also be implemented. Those skilled in the art will appreciate that the methodologies of the embodiments of the present invention are capable of being written as program code and that these are not described in the interest of brevity. A computer program implemented according to a method of an embodiment of the invention may be stored on a suitable computer readable storage medium, such as a DVD, CD-ROM, U-disk, hard disk, or may be located on a network server accessible via a network, such as the internet, or other suitable medium.

Although the components described above are included in fig. 1-3, it is not excluded that many more additional components may be used to achieve a better technical result without violating the spirit of the invention. In addition, although the flowcharts of fig. 9 and 12 are executed in the order specified, the order among these steps may be modified by those skilled in the art without departing from the spirit of the invention, and therefore, the present invention is not limited to using only the order described above. Furthermore, one skilled in the art may integrate several steps into one step or perform more steps in addition to these steps, sequentially or in parallel, and the invention should not be limited thereby.

The above description is only of the preferred embodiments of the present invention, but not limited thereto, and any person skilled in the art can make further modifications and variations without departing from the spirit and scope of the present invention, and the scope of the present invention is defined by the claims of the present application.

Claims (7)

1. A method of encrypting and decrypting physical address information, performed by a flash memory controller, comprising:

Receiving a first read command from a host end, requesting to acquire a plurality of first physical block addresses corresponding to a section of logical block address interval, wherein each first physical block address indicates where first user data of the first logical block address in the logical block address interval is actually stored in a flash memory device;

reading the first physical block address corresponding to the logical block address range from the flash memory device;

the first physical block address is compiled and arranged into a plurality of items;

dividing the plurality of items into a plurality of groups according to the first logic block address;

encrypting the items in the group using the same encryption algorithm and a plurality of encryption parameters, respectively, or using a plurality of encryption algorithms and respective encryption parameters of the plurality of encryption algorithms, respectively, to obtain encrypted items;

transmitting the encrypted item to the host side;

receiving a second read command carrying the encrypted item from the host for requesting the flash memory controller to read second user data;

obtaining information of which group the second logic block address carried in the second read command belongs to;

decrypting the encrypted item in the second read command using a decryption algorithm and a decryption parameter belonging to the group to obtain a decrypted item, wherein the decryption algorithm and the decryption parameter are inverse programs of the encryption algorithm and the encryption parameter belonging to the group;

Obtaining a second physical block address from the decrypted item;

reading the second user data from the second physical block address of the flash memory device; and

and transmitting the second user data to the host side.

2. The method of encrypting and decrypting physical address information as recited in claim 1, comprising:

information is recorded that the items of each of the clusters are encrypted using a particular encryption algorithm and a particular encryption parameter.

3. An apparatus for encrypting and decrypting physical address information, comprising:

control logic coupled to the flash memory device;

a host interface coupled to the host end; and

a processing unit, coupled to the control logic and the host interface, for receiving a first read command from the host side through the host interface, requesting to obtain a plurality of first physical block addresses corresponding to a segment of logical block address intervals, wherein each of the first physical block addresses indicates where first user data of a first logical block address in the logical block address intervals is actually stored in the flash memory device; reading, by the control logic, a first table from the flash memory device, the first table including the first physical block address corresponding to the logical block address interval; the first physical block address is compiled and arranged into a plurality of items; dividing the plurality of items into a plurality of groups according to the first logic block address; encrypting the items in the group using the same encryption algorithm and a plurality of encryption parameters, respectively, or using a plurality of encryption algorithms and respective encryption parameters of the plurality of encryption algorithms, respectively, to obtain encrypted items; transmitting the encrypted item to the host end through the host interface, so that the host end can send a second read command carrying the encrypted item to the processing unit; receiving a second read command carrying the encrypted item from the host computer through the host computer interface to request the processing unit to read second user data; obtaining information of which group the second logic block address carried in the second read command belongs to; decrypting the encrypted item in the second read command using a decryption algorithm and a decryption parameter belonging to the group to obtain a decrypted item, wherein the decryption algorithm and the decryption parameter are inverse programs of the encryption algorithm and the encryption parameter belonging to the group; obtaining a second physical block address from the decrypted item; reading the second user data from the second physical block address of the flash memory device; and transmitting the second user data to the host side.

4. A device for encrypting and decrypting physical address information as claimed in claim 3, wherein the processing unit records information of the items of each of the groups encrypted using a specific encryption algorithm and specific encryption parameters.

5. The apparatus for encrypting and decrypting physical address information as recited in claim 3, wherein the processing unit judges whether the decrypted item is valid or not based on the physical block address of the first table; and when the decrypted item is valid, reading the second user data from the second physical block address of the flash memory device through the control logic, and transmitting the second user data to the host through the host interface.

6. The apparatus for encrypting and decrypting physical address information as recited in claim 5, wherein the processing unit transmits information of a read failure to the host side through the host interface when the decrypted item is invalid.

7. The apparatus for encrypting and decrypting physical address information as recited in claim 5, wherein the processing unit suggests the first physical block address of the logical block address range in the host-side update buffer through the host interface when the decrypted item is invalid.