TWI804359B - Method and apparatus for decoding low-density parity-check (ldpc) code - Google Patents

Abstract

The invention is related to a method and an apparatus for decoding low-density parity-check (LDPC) code. The method includes: when detecting a codeword is stored in a static random access memory (SRAM), making an LDPC decoder to enter a first-stage state, in which a check-node calculation circuit calculates a first syndrome corresponding to the codeword; when the first syndrome indicates that the codeword obtained in the first-stage state is incorrect, making the LDPC decoder to enter a second-stage state, in which a variable-node calculation circuit generates variable nodes using a bit flipping algorithm, and the check-node calculation circuit calculates a second syndrome corresponding to the variable nodes; and when the second syndrome indicates that the variable nodes obtained in the second-stage state is incorrect, making the LDPC decoder to repeatedly enter a third-stage state until the decoding is successful, or the iteration number of times of the third-stage state has exceeded a threshold. With the above three-stage configuration for the LDPC decoder, general mechanism would be provided to coordinate with operations performed by the check-node calculation circuit and the variable-node calculation circuit.

Description

Decoding method and device for low-density parity-check codes

The invention relates to a storage device, in particular to a decoding method and device for a low-density parity check code.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address for accessing NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of NOR flash memory in time. material. In contrast, NAND flash memory is not random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the CPU needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory). Reducing the consumption of computing resources in the process of reading data from the flash memory module has always been an important issue affecting the overall performance of the flash memory controller. Therefore, the present invention proposes a decoding method and device for low-density parity-check codes, which are used to reduce the consumption of computing resources.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem to be solved.

This specification relates to a decoding method of a low-density parity-check code performed by a low-density parity-check decoder. The method includes the following steps: when it is detected that the codeword is stored in the static random access memory, the Low-Density Parity-Check (LDPC) decoder enters the first stage state, and in the second stage In the first-stage state, the check node calculation circuit performs a modular square multiplication method on the code word and the parity check matrix to calculate the first syndrome. When the first syndrome indicates that the codeword obtained in the first stage state is incorrect, the LDPC decoder enters the second stage state, and in the second stage state, the change node calculation circuit is based on the codeword, corresponding to the codeword A plurality of first soft bits and the first syndrome perform a bit flip algorithm to generate a plurality of changed nodes, and calculate a plurality of second soft bits of the changed nodes; The check matrix performs a modular square multiplication method to calculate the second syndrome. When the second syndrome indicates that the changed node generated in the second-stage state is incorrect, the LDPC decoder repeatedly enters the third-stage state until decoding succeeds or the number of iterations of the third-stage state exceeds a threshold. In each iteration of the third stage state, the changed node calculation circuit executes a bit flipping algorithm according to the changed node, the second soft bit corresponding to the changed node and the second syndrome to generate a plurality of new changed nodes, And calculating a plurality of new second soft bits of the new changed node; the check node calculation circuit performs a modular square multiplication method on the new changed node and the parity check matrix to calculate a new second syndrome.

The specification further relates to a decoding device of a low-density parity-check code, comprising: a change node calculation circuit coupled to the static random access memory; and a check node calculation circuit coupled to the change node calculation circuit. The decoding apparatus of the LDPC code implements the decoding method of the low-density parity-check code as described above.

Codewords include user data and LDPC codes. Each hard bit in the codeword corresponds to at least one first soft bit, which is used to indicate the degree of confidence of this hard bit, and each change node corresponds to at least one second soft bit, which is used to indicate the confidence of this change node degree.

As one of the advantages of the above embodiments, through the three-stage configuration of the LDPC decoder as described above, a general mechanism can be provided to integrate the operation of the check node calculation circuit and the change node calculation circuit.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

The following description is a preferred implementation mode of the invention, and its purpose is to describe the basic spirit of the invention, but not to limit the invention. For the actual content of the invention, reference must be made to the scope of the claims that follow.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, components and/or components, but do not exclude the possibility of adding More technical characteristics, numerical values, method steps, operation processes, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a priority order, a pre-relationship, or an element An element preceding another element, or a chronological order in performing method steps, is only used to distinguish elements with the same name.

It must be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements may be interpreted in a similar fashion, eg, "between" versus "directly between," or "adjacent" versus "directly adjacent," and so forth.

Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110 , a flash memory controller 130 and a flash memory module 150 , and the flash memory controller 130 and the flash memory module 150 may be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, notebook computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. Between the host terminal 110 and the host interface (Host Interface) 131 of the flash memory controller 130, a universal serial bus (Universal Serial Bus, USB), advanced technology attachment (advanced technology attachment, ATA), serial advanced technology attachment (serial advanced technology) can be used. attachment, SATA), peripheral component interconnect express (PCI-E), universal flash memory storage (Universal Flash Storage, UFS), embedded multimedia card (Embedded Multi-Media Card, eMMC) and other communication protocols communicate. The flash memory interface (Flash Interface) 139 of the NAND flash controller (NAND Flash Controller, NFC) 137 and the flash memory module 150 can communicate with each other through the double data rate (Double Data Rate, DDR) communication protocol, for example, open NAND flash (Open NAND Flash Interface, ONFI), Double Data Rate Switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in various ways, such as using general-purpose hardware (for example, a single processor, multiple processors with parallel processing capabilities, graphics processing units, or other processors with computing capabilities), and The functions described later are provided when the software and/or firmware instructions are executed. The processing unit 134 receives host commands through the host interface 131, such as read commands (Read Command), write commands (Write Command), discard commands (Discard Command), erase commands (Erase Command), etc., schedule and execute these commands . The flash controller 130 further includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, used to configure the space as a data buffer, store user data (also called host data) that is read from the host end 110 and will be written into the flash memory module 150, and read from the flash memory module 150. The group 150 reads and outputs user data to the host 110 . The random access memory 136 can also store data needed during execution, such as variables, data tables, host-to-flash address mapping table (H2F table for short), flash memory and host address Comparison table (Flash-to-Host Address Mapping Table, F2H table for short), etc. The NAND flash memory controller 137 provides functions required for accessing the flash memory module 150 , such as a command sequencer (Command Sequencer), Low-Density Parity-Check (Low-Density Parity-Check, LDPC) and so on.

The shared bus architecture (Shared Bus Architecture) can be configured in the flash memory controller 130, which is used to couple components to each other to transmit data, addresses, control signals, etc. These components include a host interface 131, a processing unit 134, and a RAM 136 , NAND flash memory controller 137 and the like. A bus comprises parallel physical wires connecting two or more components in flash memory controller 130 . A shared bus is a shared transmission medium. At any one time, only two devices can use these lines to communicate with each other and transfer data. Data and control signals can travel bidirectionally along the data and control lines respectively between components, but on the other hand, address signals can only travel unidirectionally along the address lines. For example, when the processing unit 134 wants to read data at a specific address of the RAM 136 , the processing unit 134 transmits the address to the RAM 136 on the address line. Then, the data at this address will be returned to the processing unit 134 on the data line. In order to complete the data reading operation, the control signal will be transmitted using the control line.

The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (Gigabytes, GB), or even several terabytes (Terabytes, TB), for storing a large amount of user data, Such as high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array, and the memory cells in the memory array can be configured as single-level cells (Single Level Cells, SLCs), multi-level cells (Multiple Level Cells, MLCs) three-level cells (Triple Level Cells, TLCs), four-layer units (Quad-Level Cells, QLCs), or any combination of the above. The processing unit 134 can write user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and read user data from a specified address (source address) in the flash memory module 150 . The flash memory interface 139 uses several electronic signals to coordinate data and command transmission between the flash memory controller 130 and the flash memory module 150 , including a data line (Data Line), a clock signal (Clock Signal) and a control signal (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to FIG. 2, the interface 151 in the flash memory module 150 may include four input and output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each of which is connected to four NAND flash memory units, for example, the channel CH#0 is connected to NAND flash memory units 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory unit can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11 , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in parallel, or write user data to the enabled NAND flash memory unit. Those skilled in the art can change the design of the flash memory module 150 according to the requirements of the system, configure more or fewer channels in the flash memory module 150, and/or connect each channel to more or fewer NAND flash memory units , the present invention is not limited thereby.

所屬技術領域人員知道可使用習知的奇偶校檢矩陣和高效演算法來產生LDPC碼，例如二階段編碼（2-stage Encoding）等。 The NAND flash memory controller 137 may include a low-density parity-check encoder (LDPC Encoder), which is used to generate a low-density parity-check code (LDPC Code) according to user data, which is a linear error correction code (Linear Error Correcting Code). For example, the generation of LDPC codes can be expressed by the following formula: MSG _1xn ⊙ PCM _{nx (n+m)} = CW _1x(n+m) Among them, MSG _1xn represents a matrix with 1 column and n rows of user data, and PCM _{nx (n+m)} represents n columns, (n+m) row parity check matrix (Parity Check Matrix), CW _1x(n+m) represents 1 column of the last generated codeword (Codeword), (n+m) Row matrix, ⊙ stands for Modulo 2 Multiplication. The parity check matrix can contain a Quasi-Cyclic (QC) structure, and the value of the first n bits in CW _1x(n+m) is equal to the value of MSG _1xn , and in CW _1x(n+m) The value of the last m bits is called LDPC code. Examples are as follows:

Those skilled in the art know that LDPC codes can be generated using known parity check matrices and efficient algorithms, such as 2-stage encoding.

The NAND flash memory controller 137 may include an LDPC decoder (LDPC Decoder) 138 for verifying the codeword (Codeword, including user data and LDPC code) read from the flash memory module 150 through the flash memory interface 139 and judging the codeword contains error bits. Once an error bit is found in the codeword, the LDPC decoder 138 attempts to recover the correct codeword and obtain user information from the codeword. If the correct codeword cannot be returned after a predetermined number of attempts, the LDPC decoder 138 determines that the codeword is an irreparable error codeword (Uncorrectable Codeword). For LDPC decoding, refer to the example (n=3, k=6) LDPC code shown in FIG. 3 . Blocks 33#0 to 33#5 represent variable nodes (Variable Nodes), and blocks 31#0 to 31#2 represent check nodes (Check Nodes). The bits in the change nodes 33#0 to 33#5 form a codeword, which is composed of user data and LDPC codes, and the bits must satisfy the Graphical Constrains. In detail, all wires connected to a change node have the same value, and the sum of all wires connected to a check node must divide by two with a remainder of 0 (that is, they add up to an even number, or has an even number of odd values). Check nodes 31#0 to 31#2 may also be called syndromes (Syndrome).

The NAND flash memory controller 137 also includes a static random access memory (Static Random Access Memory, SRAM) 140 for storing data required in the decoding process. The flash memory interface 139 can store codewords (also referred to as hard bits) read from the flash memory module 150 and designated addresses of the soft bits in the SRAM 140 . Each hard bit can correspond to at least one soft bit, and the corresponding soft bit is used to indicate the confidence level of the hard bit (Likelihood of Belief). In order to correct the erroneous bits in the codeword, the SRAM 140 also needs to configure space to store the updated change nodes and their corresponding soft bits during the decoding process. Similarly, each change node may correspond to at least one soft bit, and the corresponding soft bit is used to indicate the degree of confidence of the change node. However, SRAM 140 is a precious resource that requires proper planning and use to improve its utilization (Utilization).

The LDPC decoder (LDPC Decoder) 138 includes two important circuits: a check-node calculation circuit (Check-node Calculation Circuit) and a variable-node calculation circuit (Variable-node Calculation Circuit). The check node calculation circuit executes the modular square multiplication method on the code word or the change node, and the parity check matrix to calculate the syndrome. The change node calculation circuit executes the known bit flipping algorithm (Bit Flipping Algorithm) according to the soft bits corresponding to the codeword or change node, and the syndrome to generate a new change node, and uses the known formula to calculate The soft bits of the new change node. However, the operation of the check node calculation circuit and the change node calculation circuit are interdependent, and the result produced by one circuit will be the input of the other circuit. Therefore, a general mechanism is needed to integrate the check node calculation circuit and the change node. Calculate the operation of the circuit.

In order to integrate the operations of the check node calculation circuit and the change node calculation circuit, the embodiment of the present invention proposes a three-stage LDPC decoding. The LDPC decoder 138 may enter one of the three phases according to circumstances, so that the check node calculation circuit and the change node calculation circuit therein complete the operation of entering the phase accordingly. In detail, when it is detected that the codeword is stored in the SRAM 140, the LDPC decoder 138 enters the first stage state. In the first stage state, the check node calculation circuit performs a modular square multiplication method on the code word and the preset parity check matrix to calculate the first syndrome, wherein the code word includes user data and low-density parity check multiple bits of the code. When the first syndrome indicates that the codeword obtained in the first-stage state is incorrect, the LDPC decoder 138 enters the second-stage state. In the second stage state, the change node calculation circuit performs a bit flipping algorithm to generate a plurality of change nodes according to the codeword, the plurality of first soft bits corresponding to the codeword, and the first syndrome, and calculates the change node Multiple second soft bits of . The check node calculation circuit performs a modular square multiplication method on the changed nodes and the preset parity check matrix to calculate the second syndrome. Each hard bit in the codeword corresponds to at least one first soft bit, which is used to indicate the degree of confidence of the hard bit. Each change node corresponds to at least one second soft bit, which is used to indicate the degree of confidence of the change node. When the second syndrome indicates that the changed node generated in the second-stage state is incorrect, the LDPC decoder 138 repeatedly enters the third-stage state until decoding succeeds or the number of iterations of the third-stage state exceeds a threshold. In each iteration of the third stage state, the changed node calculation circuit executes a bit flipping algorithm according to the changed node, the second soft bit corresponding to the changed node and the second syndrome to generate a plurality of new changed nodes, And calculate a plurality of new second soft bits of the new changed node. The check node calculation circuit performs a modular square multiplication method on the new changed node and the parity check matrix to calculate a new second syndrome.

In some embodiments, the LDPC decoder 138 may include a finite state machine, which is used to keep the LDPC decoder 138 in the first stage state when the codeword is stored in the SRAM 140; When the syndrome points out that the acquired code word in the first phase state is incorrect, the LDPC decoder 138 is in the second phase state; When the generated change node is incorrect, let the LDPC decoder 138 be in the third-stage state; and control the number of iterations to enter the third-stage state to not exceed the threshold.

由於計算後的校驗子為全”0”，碼字中不包含錯誤位元。如果計算後的校驗子不為全”0”，則碼字中包含錯誤位元。校驗節點計算電路418可輸出硬位元或者變化節點，以及計算出的校驗子至變化節點計算電路416。在一些實施例中，校驗節點計算電路418可依據相應於硬位元或者變化節點的軟位元計算校驗子的可靠度（Reliability of Syndrome），並且將校驗子及其可靠度一併傳送到變化節點計算電路416。 In some embodiments, the flash memory interface 139 may include a soft-bit calculation circuit (Soft-bit Calculation Circuit), which is used to calculate each hard bit in the code word when the code word is read from the flash memory module 150 soft bits. In view of this arrangement, refer to the block diagram of the NAND flash memory controller 137 shown in FIG. 4 . Four areas 431 , 433 , 435 and 437 can be configured in the SRAM 430 for storing hard bits, soft bits corresponding to hard bits, change nodes, and soft bits corresponding to change nodes, respectively. The flash memory interface 139 writes the hard bits read from the flash memory module 150 into the area 431 , and writes the calculated soft bits into the area 433 . The LDPC decoder 410 includes a finite state machine (Finite State Machine, FSM) 412 , multiplexers 413 , 414 , a change node calculation circuit 416 and a check node calculation circuit 418 . The check node calculation circuit 418 is used to calculate the syndrome according to the hard bits stored in the area 431 or the changed nodes stored in the area 435 and the parity check matrix. Syndrome generation can be expressed by the following formula: PCM _{nx (n+m)} ⊙ CW _{( n+m )x 1} = SYD _mx1 Among them, PCM _{nx (n+m)} represents the parity of n columns and (n+m) rows Check matrix, MSG _(n+m)x1 represents the (n+m) column and 1-row matrix of the codeword, SYD _mx1 represents the m-column and 1-row matrix of the syndrome, and ⊙ represents the modulo 2 multiplication. Examples are as follows:

Since the calculated syndrome is all "0", the code word does not contain error bits. If the calculated syndrome is not all "0", the codeword contains error bits. The check node calculation circuit 418 can output hard bits or change nodes, and the calculated syndrome to the change node calculation circuit 416 . In some embodiments, the check node calculation circuit 418 can calculate the reliability of the syndrome (Reliability of Syndrome) according to the soft bit corresponding to the hard bit or the change node, and combine the syndrome and its reliability sent to the change node calculation circuit 416.

The changed node calculation circuit 416 is used for judging whether the codeword needs to be corrected according to the syndrome input from the check node calculation circuit 418 . If not needed (that is, the syndrome is all “0”), the changed node calculation circuit 416 sends a successful decoding message to the finite state machine 412 . If necessary (that is, the syndrome is not all "0"), the change node calculation circuit 416 sends a message of decoding failure to the finite state machine 412, and according to the syndrome, hard bits or change nodes, corresponding to the hard bit The soft bit of the element or change node executes the known bit flipping algorithm, which is used to change the state of one or more hard bits or change nodes that may be wrong in the codeword (that is, change "0b0" to "0b1", or change "0b1" to "0b0"). The changed node calculation circuit 416 stores the updated changed node in the area 435 of the SRAM 430 . Next, the changed node calculation circuit 416 calculates the soft bits corresponding to the updated changed nodes according to the updated changed nodes using a known formula, and stores the calculated soft bits in the area 437 of the SRAM 430 . The soft bit may be a log-likelihood ratio (Log-likelihood Ratio, LLR), a quantization value of the log-likelihood ratio (Quantization of LLR), and the like.

The finite state machine 412 uses three stages to manage the entire process of LDPC decoding. In each stage, appropriate control signals are output to the multiplexers 413, 414 and the change node calculation circuit 416, which are used to drive these components to jointly complete the LDPC decoding. FIG. 5 shows example state transitions of the finite state machine 412 . The output terminal of the multiplexer 413 is coupled to the change node calculation circuit 416 , and the two input terminals of the multiplexer 413 are respectively coupled to regions 431 and 435 in the SRAM 430 . The output terminal of the multiplexer 414 is coupled to the change node calculation circuit 416 , and the two input terminals of the multiplexer 414 are respectively coupled to regions 433 and 437 in the SRAM 430 .

After the flash memory interface 139 stores the hard bits and soft bits into the areas 431 and 433 respectively, the finite state machine 412 enters the first stage state 531 from the waiting state 510 . The first phase may be referred to as the hard bit initialization phase. In the first stage, the finite state machine 412 sends a control signal to the multiplexer 413 to couple the region 431 to the change node calculation circuit 416 , and then drives the change node calculation circuit 416 to perform the first stage operation. Referring to the data flow schematic diagram of the first stage shown in FIG. 6, the change node calculation circuit 416 reads the hard bits (indicated by the symbol "sgn") from the area 431 through the multiplexer 413, and transmits the hard bits to the checksum Node calculation circuit 418 . The check node calculation circuit 418 calculates a syndrome according to the obtained hard bits and the preset parity check matrix, and transmits the hard bits and the syndrome to the change node calculation circuit 416 . When the syndrome is all “0”, the change node calculation circuit 416 sends a decoding success message to the finite state machine 412 , so that the finite state machine 412 enters the decoding success state 551 . When the syndrome is not all “0”, the change node calculation circuit 416 stores the hard bits in the area 435 , and sends a decoding failure message to the finite state machine 412 , so that the finite state machine 412 enters the second stage state 532 . Since the hard bits have been successfully stored in the area 435, the area 431 is no longer needed for the code word currently being processed. Therefore, the area 431 can be released to store the next code word read from the flash memory module 150, so that The decoding of this codeword and the next codeword can be performed in parallel to improve the efficiency of data reading.

The second phase, which may be referred to as the soft bit initialization and decoding phase, consists of the first iteration of decoding. In the second stage, the finite state machine 412 sends a control signal to the multiplexer 413 to connect the area 435 to the change node calculation circuit 416, and sends a control signal to the multiplexer 414 to couple the area 433 to the change node calculation circuit 416 , and then, the driving change node calculation circuit 416 executes the operation of the second stage. Referring to the data flow schematic diagram of the second stage shown in FIG. 7, the change node calculation circuit 416 reads the hard bit (indicated by the symbol "sgn") from the area 435 through the multiplexer 413, and reads the hard bit from the area 433 through the multiplexer 414. Take the soft bit (represented by the symbol "mag"), and execute the known bit flip algorithm based on the syndrome, hard bit sgn and soft bit mag calculated in the first stage to update the hard bit sgn becomes the changed node sgn', and the corresponding soft bit mag' is calculated according to the updated changed node sgn' using a known formula. Next, the changed node calculation circuit 416 transmits the changed node sgn' and the corresponding soft bit mag' to the check node calculation circuit 418. The check node calculation circuit 418 calculates the syndrome according to the obtained changed node sgn' and the preset parity check matrix, and transmits the changed node sgn', the corresponding soft bit mag' and the syndrome to the changed node calculation circuit 416. When the syndrome is all “0”, the change node calculation circuit 416 sends a decoding success message to the finite state machine 412 , so that the finite state machine 412 enters the decoding success state 551 . When the syndrome is not all "0", the change node calculation circuit 416 stores the change node sgn' in the area 435, stores the corresponding soft bit mag' in the area 437, and sends a decoding failure message to the finite state machine 412 , so that the finite state machine 412 enters the third stage state 533 . Since the initial soft bits have been updated and successfully stored in area 437, area 433 is no longer needed for the codeword currently being processed. Therefore, area 433 can be released to allow flash memory interface 139 to store the corresponding codeword for the next codeword. The soft bits, so that the decoding of this codeword and the next codeword can be parallelized, and the efficiency of data reading is improved.

The third stage may include a second or subsequent number of decoding iterations. This stage will be executed repeatedly until the decoding is successful, or the decoding fails after more than the preset number of iterations. At the beginning of entering the third stage, the finite state machine 412 sends a control signal to the multiplexer 414 to connect the area 437 to the change node calculation circuit 416, and then drives the change node calculation circuit 416 to execute the third stage operation. Referring to the data flow schematic diagram of the third stage shown in FIG. 8, the change node calculation circuit 416 reads the change node (indicated by the symbol "sgn'") from the area 435 through the multiplexer 413, and reads the change node from the area 437 through the multiplexer 414. Take the corresponding soft bit (indicated by the symbol "mag'"), according to the syndrome, change node sgn' and soft bit mag calculated in the previous decoding iteration (which can exist in the second or third stage) ', execute the known bit flipping algorithm to update the changed node sgn' to become the changed node sgn", and use the known formula to calculate the corresponding soft bit mag" according to the updated changed node sgn". Then , the changed node calculation circuit 416 transmits the changed node sgn" and the corresponding soft bit mag" to the check node calculation circuit 418. The check node calculation circuit 418 calculates the checkpoint according to the obtained changed node sgn" and the preset parity check matrix Syndrome, and the changed node sgn", the corresponding soft bit mag" and the syndrome are transmitted to the changed node calculation circuit 416. When the syndrome is all “0”, the change node calculation circuit 416 sends a decoding success message to the finite state machine 412 , so that the finite state machine 412 enters the decoding success state 551 . When the syndrome is not all "0", the change node calculation circuit 416 stores the change node sgn" in the area 435, stores the corresponding soft bit mag" in the area 437, and sends a decoding failure message to the finite state machine 412 , so that the finite state machine 412 remains in the third stage state 533 , or enters the decoding error state 553 .

When the finite state machine 412 is in the third stage state 533 and obtains the decoding failure message from the changed node calculation circuit 416 , the finite state machine 412 will determine whether the number of iterations executed in the third stage exceeds a preset threshold. If so, finite state machine 412 enters decode error state 553 . Otherwise, the finite state machine 412 remains in the third-stage state 533 , and the driving change node calculation circuit 416 performs the third-stage operation.

In the successful decoding state 551 , the finite state machine 412 obtains the user data in the codeword, stores the user data in a designated location in the RAM 136 , and returns a successful decoding message to the processing unit 134 .

In the decoding error state 553 , the finite state machine 412 replies a decoding failure message to the processing unit 134 , so that the processing unit 134 can determine that a UECC page appears.

In other embodiments, the flash memory interface 139 does not include soft bit calculation circuits. According to this configuration, the NAND flash memory controller 137 shown in FIG. 4 can be changed to the block diagram shown in FIG. 9 . Compared with the SRAM 430, the SRAM 930 reduces the area 433 for storing the soft bits corresponding to the hard bits. Compared with the LDPC decoder 410 , the LDPC decoder 910 reduces the number of multiplexers 414 . The finite state machine 912 can use the example state transition shown in FIG. 5 to control the entire LDPC decoding process. Among the three stages mentioned above, only the second stage has made some changes, and the rest of the technical details are similar.

The schematic diagram of the data flow in the first stage shown in FIG. 10 is similar to that in FIG. 6 . Therefore, the technical details of the first stage can be derived from the description in FIG. 6 , and will not be repeated for simplicity.

In the second stage, the finite state machine 912 sends a control signal to the multiplexer 413 to connect the area 435 to the change node calculation circuit 916 , and then drives the change node calculation circuit 916 to execute the second stage operation. Referring to the schematic diagram of the data flow in the second stage shown in FIG. 11 , the change node calculation circuit 416 reads the hard bit (indicated by the symbol "sgn") from the area 435 through the multiplexer 413, and sets the soft bit to a preset value (Denoted by the symbol "mag*", for example, all are strong, all are medium or all are weak), according to the syndrome calculated in the first stage, the hard bit sgn and the preset soft bit mag*, execute learning The known bit flipping algorithm is used to update the hard bit sgn to become the change node sgn', and calculate the corresponding soft bit mag' according to the updated change node sgn' using a known formula. Next, the changed node calculation circuit 416 transmits the changed node sgn' and the corresponding soft bit mag' to the check node calculation circuit 418. For subsequent technical details in the second stage, reference may be made to the corresponding description in FIG. 7 , which will not be repeated for simplicity.

The schematic diagram of data flow in the third stage shown in FIG. 12 is similar to that in FIG. 8 . Therefore, the technical details of the third stage can be derived from the description in FIG. 8 , and will not be repeated for simplicity.

In some other embodiments, the flash memory interface 139 includes a soft bit calculation circuit, and the LDPC encoder is a zero-based differential encoder (Zero-based Differential Decoder). According to this configuration, the NAND flash memory controller 137 shown in FIG. 4 can be changed to the block diagram shown in FIG. 13 . Compared with the SRAM 430 , the SRAM 1330 is not configured with an area for storing changed nodes, but instead, the SRAM 1330 is configured with an area 1335 for storing flipped states. The toggle status contains multiple bits, and each bit stores information about whether the corresponding hard bit is toggled, for example, "0b1" means flip (that is, change the state), "0b0" means not flip (that is, maintain the original state) . The flip state is initially all "0". LDPC decoder 1310 includes finite state machine 1312 , exclusive OR calculator 1313 , multiplexer 414 , change node calculation circuit 1316 and check node calculation circuit 1318 . The exclusive OR calculator 1313 is used to perform exclusive OR calculation on the hard bits stored in the area 431 and the inversion state stored in the area 1335 to generate the original hard bits or the updated change nodes. The check node calculation circuit 1318 is used to calculate the syndrome according to the calculation result output by the exclusive OR calculator 1313 and the parity check matrix. The change node calculation circuit 1316 is roughly the same as the change node calculation circuit 416 for the judgment of the syndrome and its subsequent operations, the execution of the conventional bit flipping algorithm, and the calculation of soft bits. Let me repeat. Different from the changed node calculation circuit 416 , the changed node calculation circuit 1316 stores the updated toggle state in the area 1335 of the SRAM 1330 .

The finite state machine 1312 uses three stages to manage the entire process of LDPC decoding. In each stage, appropriate control signals are output to the multiplexer 1314 and the change node calculation circuit 1316 to drive these elements to jointly complete the LDPC decoding. The finite state machine 1312 can use the example state transition shown in FIG. 5 to control the entire LDPC decoding process.

In the first stage, the finite state machine 1312 drives the change node calculation circuit 1316 to perform the operations of the first stage. Referring to the schematic diagram of data flow in the first stage shown in Figure 14, the change node calculation circuit 1316 reads the hard bit (indicated by the symbol "sgn") through the mutex OR calculator 1313, and transmits the hard bit to the check node computing circuit 1318 . The check node calculation circuit 1318 calculates the syndrome according to the acquired hard bits and the preset parity check matrix, and transmits the syndrome to the change node calculation circuit 1316 . It should be noted here that the check node calculation circuit 1318 does not transmit hard bits to the change node calculation circuit 1316 . When the syndrome is all “0”, the change node calculation circuit 1316 sends a decoding success message to the finite state machine 1312 , so that the finite state machine 1312 enters the decoding success state 551 . When the syndrome is not all “0”, the change node calculation circuit 1316 stores the hard bits in the area 435 and sends a decoding failure message to the finite state machine 1312 , so that the finite state machine 1312 enters the second stage state 532 . It should be noted here that the area 431 cannot be released because the hard bits are always used.

Referring to the data flow schematic diagram of the second stage shown in FIG. 15, in the second stage, the finite state machine 1312 sends a control signal to the multiplexer 1314 to connect the area 433 to the change node calculation circuit 1316, and then drives the change node calculation circuit Circuit 1316 performs the second stage of operations. Referring to the schematic diagram of data flow in the second stage shown in FIG. 13, the change node calculation circuit 1316 reads soft bits (indicated by the symbol "mag") from the area 433 through the multiplexer 1314, and according to the checksum calculated in the first stage Sub, preset hard bit (default is all "0", expressed by symbol "sgn*", that is, the actual hard bit stored in the area 431 is temporarily replaced by the default value) and soft bit mag, execute the practice The known bit flip algorithm is used to update the hard bit sgn to become the change node sgn' (the change node at this time contains the error pattern, Error Pattern), and calculate the difference between the hard bit sgn and the change node sgn' to A flip state (indicated by the symbol "flp'") is generated, and the corresponding soft bit mag' is calculated using a known formula according to the updated change node sgn'. Next, the changed node calculation circuit 1316 transmits the changed node sgn' and the corresponding soft bit mag' to the check node calculation circuit 1318. The check node calculation circuit 1318 calculates the syndrome according to the obtained changed node sgn' and the preset parity check matrix, and transmits the changed node sgn', the corresponding soft bit mag' and the syndrome to the changed node calculation circuit 1316. Since the change node sgn' is an error mode, the change node calculation circuit 1316 obtains the result that the syndrome is not all "0", stores the flip state flp' in the area 1335, and stores the corresponding soft bit mag' in the area 437 , and send a decoding failure message to the finite state machine 1312 , so that the finite state machine 1312 enters the third stage state 533 . Since the initial soft bits have been updated and successfully stored in area 437, area 433 is no longer needed for the codeword currently being processed. Therefore, area 433 can be released to allow flash memory interface 139 to store the corresponding codeword for the next codeword. soft bits.

The third stage may include a second or subsequent number of decoding iterations. This stage will be executed repeatedly until the decoding is successful, or the decoding fails after more than the preset number of iterations. At the beginning of entering the third stage, the finite state machine 1312 sends a control signal to the multiplexer 1314 to connect the region 437 to the change node calculation circuit 1316, and then drives the change node calculation circuit 1316 to perform the operation of the third stage. Referring to the data flow schematic diagram of the third stage shown in FIG. 16, the change node calculation circuit 1316 obtains the change node (indicated by the symbol "sgn'") from the mutex OR calculator 1313, and reads the corresponding The soft bit (indicated by the symbol "mag'"), based on the syndrome, the change node sgn' and the soft bit mag' calculated in the previous decoding iteration (which can exist in the second stage or the third stage), Executes the known bit-flip algorithm for updating the change node sgn' to become a change node sgn", computing the difference between the hard bit sgn and the change node sgn" to produce a new flipped state (denoted by "flp'' "Indicates), and according to the updated change node sgn", use the known formula to calculate the corresponding soft bit mag". Next, the changed node calculation circuit 1316 transmits the changed node sgn″ and the corresponding soft bit mag” to the check node calculation circuit 1318 . The check node calculation circuit 1318 calculates the syndrome according to the obtained changed node sgn" and the preset parity check matrix, and transmits the changed node sgn", the corresponding soft bit mag" and the syndrome to the changed node calculation circuit 1316. When the syndrome is all "0", the change node calculation circuit 1316 sends a successful decoding message to the finite state machine 1312, so that the finite state machine 1312 enters the decoding success state 551. When the syndrome is not all "0" , the change node calculation circuit 1316 stores the flip state flp" in the area 1335, stores the corresponding soft bit mag" in the area 437, and sends a decoding failure message to the finite state machine 1312, so that the finite state machine 1312 maintains the third Phase state 533, or enter Decoding Error state 553.

Although Fig. 1, Fig. 2, Fig. 4, Fig. 9 and Fig. 13 contain the elements described above, it does not rule out the use of more other additional elements to achieve better technical effects without violating the spirit of the invention.

Although the present invention is described using the above examples, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, the invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

10: Electronic device 110: Host side 130: Flash memory controller 131: host interface 134: processing unit 136: random access memory 137: NAND flash memory controller 138: LDPC decoder 139: Flash interface 140: static random access memory 150: Flash memory module 151: interface 153#0~153#15: NAND flash memory unit CH#0~CH#3: channel CE#0~CE#3: enable signal 31#0~31#2: check node 33#0~33#5: change node 410: LDPC encoder 412: Finite state machine 413,414: multiplexer 416: Change node calculation circuit 418: check node calculation circuit 430: static random access memory 431, 433, 435, 437: areas in static random access memory 510,531~533,551~553: Status 910: LDPC encoder 912: Finite state machine 916: change node calculation circuit 930: static random access memory 1310: LDPC encoder 1312: Finite state machine 1313: mutex or calculator 1314: multiplexer 1316: change node calculation circuit 1318: check node calculation circuit 1330: static random access memory 1335: Area in SRAM

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the invention.

FIG. 3 is a schematic diagram of an example LDPC code according to an embodiment of the invention.

FIG. 4 is a block diagram of a NAND flash memory controller according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of state transitions of a finite state machine according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of data flow corresponding to the first stage of the hardware architecture of FIG. 4 according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of data flow corresponding to the second stage of the hardware architecture of FIG. 4 according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of data flow corresponding to the third stage of the hardware architecture of FIG. 4 according to an embodiment of the present invention.

FIG. 9 is a block diagram of a NAND flash memory controller according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of data flow corresponding to the first stage of the hardware architecture of FIG. 9 according to an embodiment of the present invention.

FIG. 11 is a schematic diagram of data flow corresponding to the second stage of the hardware architecture of FIG. 9 according to an embodiment of the present invention.

FIG. 12 is a schematic diagram of data flow corresponding to the third stage of the hardware architecture of FIG. 9 according to an embodiment of the present invention.

FIG. 13 is a block diagram of a NAND flash memory controller according to an embodiment of the present invention.

FIG. 14 is a schematic diagram of data flow corresponding to the first stage of the hardware architecture of FIG. 13 according to an embodiment of the present invention.

FIG. 15 is a schematic diagram of data flow corresponding to the second stage of the hardware architecture of FIG. 13 according to an embodiment of the present invention.

FIG. 16 is a schematic diagram of data flow corresponding to the third stage of the hardware architecture of FIG. 13 according to an embodiment of the present invention.

510,531~533,551~553: Status

Claims (14)

A decoding method of a low-density parity-check code, performed by a low-density parity-check decoder, wherein the low-density parity-check decoder includes a change node calculation circuit and a check node calculation circuit, and the method includes: When it is detected that the code word is stored in the static random access memory, the low density parity check decoder enters the first stage state, and in the first stage state, the check node computing circuit performing a modular square multiplication method on the code word and the parity check matrix to calculate the first syndrome, wherein the code word includes user data and a low density parity check code; When the first syndrome indicates that the codeword acquired in the first-stage state is incorrect, the low-density parity-check decoder enters a second-stage state, and in the second-stage state wherein, the change node calculation circuit executes a bit flipping algorithm according to the codeword, a plurality of first soft bits corresponding to the codeword and the first syndrome to generate a plurality of change nodes, and calculating a plurality of second soft bits of the change node; the check node calculation circuit performs a modular square multiplication method on the change node and the parity check matrix to calculate a second syndrome, wherein the Each hard bit in the codeword corresponds to at least one of the first soft bits, which is used to indicate the degree of confidence of this hard bit, and each of the change nodes corresponds to at least one of the second soft bits, used for Indicate the confidence level of this change node; and When the second syndrome indicates that the changed node generated in the second-stage state is incorrect, the LDPC decoder repeatedly enters the third-stage state until decoding succeeds or the first-stage Until the number of iterations of the three-stage state exceeds a threshold value, in each iteration of the third-stage state, the change node calculation circuit is based on the change node, the second soft bit corresponding to the change node and The second syndrome executes a bit flipping algorithm to generate a plurality of new change nodes, and calculates a plurality of new second soft bits of the new change nodes; Perform a modular square multiplication method on the new change node and the parity check matrix to calculate a new second syndrome. The decoding method of the low-density parity-check code according to claim 1, wherein the low-density parity-check decoder includes a finite state machine, and the decoding method of the low-density parity-check code includes: The finite state machine causes the LDPC decoder to be in the first stage state in response to the codeword being stored in the SRAM; the finite state machine causes the LDPC decoder to be in the second state in response to the first syndrome indicating that the codeword acquired in the first phase state is incorrect stage status; The finite state machine makes the low-density parity the parity decoder is in said third stage state; and The finite state machine controls the number of iterations to enter the third-stage state to not exceed the threshold. The decoding method of the low-density parity-check code according to claim 1, wherein the codeword is read from the flash memory module through a flash memory interface and stored in the static random access memory. The decoding method of low-density parity-check code according to claim 1, wherein the low-density parity-check decoder includes a finite state machine, a first multiplexer and a second multiplexer, and the first multiplexer The output terminal of the multiplexer is coupled to the change node calculation circuit, and the two input terminals of the first multiplexer are respectively coupled to the first area and the second area in the SRAM, so The output terminal of the second multiplexer is coupled to the change node calculation circuit, and the two input terminals of the second multiplexer are respectively coupled to the third area and the first area in the SRAM. Four regions, the codeword is read from the flash memory module and stored in the first region via a flash memory interface, the flash memory interface generates the first soft bit corresponding to the codeword, and the The first soft bit is stored in the third area, and the decoding method of the low-density parity-check code includes: In the first stage state, the finite state machine sends a first control signal to the first multiplexer to couple the first region to the change node calculation circuit, and to drive the change node The calculation circuit executes the operation of the first stage, the change node calculation circuit reads the code word from the first area through the first multiplexer, and transmits the code word to the check node calculation circuit, Obtaining the first syndrome from the check node calculation circuit, sending a decoding success or decoding failure message to the finite state machine according to the first syndrome, and storing the codeword in the second syndrome. Second area; In the second stage state, the finite state machine sends a second control signal to the second multiplexer to couple the third region to the change node calculation circuit, and drive the change node The calculation circuit executes the operation of the second stage, the change node calculation circuit reads the first soft bit from the third area through the second multiplexer, and transmits the change node to the check node a calculation circuit, obtaining the second syndrome from the check node calculation circuit, sending a decoding success or decoding failure message to the finite state machine according to the second syndrome, and storing the changed node in the the second area, and store the second soft bit in the fourth area; In each iteration of the third stage state, the finite state machine sends a third control signal to the first multiplexer to couple the second region to the change node calculation circuit, and sends a third control signal to the first multiplexer to couple the second region to the change node calculation circuit. Four control signals to the second multiplexer to couple the fourth area to the change node calculation circuit, the change node calculation circuit reads from the second area through the first multiplexer The change node reads the second soft bit corresponding to the change node from the fourth area through the second multiplexer, and transmits the new change node to the check node for calculation The circuit obtains the new second syndrome from the check node calculation circuit, transmits a decoding success or decoding failure message to the finite state machine according to the new second syndrome, and stores the new change node to the second area, and store the new second soft bit in the fourth area. The decoding method of the low-density parity-check code as described in claim item 4, comprising: releasing the first area after the codeword is stored in the second area; and After the second soft bits are stored in the fourth area, the third area is released. The method for decoding low-density parity-check codes according to claim 1, wherein the low-density parity-check decoder includes a finite state machine and a multiplexer, and the output of the multiplexer is coupled to the A variable node calculation circuit, the two input terminals of the multiplexer are respectively coupled to the first area and the second area in the SRAM, and the codeword is read from the flash memory module through the flash memory interface Fetched and stored in the first area, the decoding method of the low-density parity-check code includes: In the first stage state, the finite state machine sends a first control signal to the multiplexer to couple the first region to the change node calculation circuit, and drive the change node calculation circuit Execute the operation of the first stage, the change node calculation circuit reads the code word from the first area through the multiplexer, transmits the code word to the check node calculation circuit, and reads the code word from the check node calculation circuit. The verification node calculation circuit obtains the first syndrome, transmits a decoding success or decoding failure message to the finite state machine according to the first syndrome, and stores the codeword in the second area; In the second stage state, the finite state machine drives the change node calculation circuit to perform the operation of the second stage, and the change node calculation circuit takes a preset value as the first soft bit and transmits the the change node to the check node calculation circuit, obtain the second syndrome from the check node calculation circuit, and send a decoding success or decoding failure message to the finite state according to the second syndrome a machine that stores the changed node in the second area, and stores the second soft bits in a third area; and In each iteration of the third stage state, the finite state machine sends a second control signal to the multiplexer to couple the second region to the change node calculation circuit, the change node The calculation circuit reads the change node from the second area through the multiplexer, reads the second soft bit corresponding to the change node from the third area, and transmits the new change The node sends the check node calculation circuit, obtains the new second syndrome from the check node calculation circuit, and transmits a decoding success or decoding failure message to the check node calculation circuit according to the new second syndrome. The finite state machine stores the new changed node in the second area, and stores the new second soft bit in the third area. The decoding method of the low-density parity-check code as described in claim 6, comprising: After the codeword is stored in the second area, the first area is released. The decoding method of the low-density parity-check code according to claim 1, wherein the low-density parity-check decoder includes a finite state machine, a mutual exclusion OR calculator, and a multiplexer, and the output of the multiplexer The terminal is coupled to the change node calculation circuit, the two input terminals of the multiplexer are respectively coupled to the third area and the fourth area in the SRAM, and the codeword is passed through the flash memory interface read from the flash memory module and stored in the first area of the SRAM, the second area in the SRAM stores a toggle state, the toggle state Initially all "0", the flash memory interface generates the first soft bit corresponding to the codeword, the first soft bit is stored in the third area, the mutex or calculator performing exclusive OR calculation on the codeword in the first area and the inversion state in the second area and outputting the calculation result to the change node calculation circuit, the low-density parity-check code Decoding methods include: In the first stage state, the finite state machine drives the change node calculation circuit to perform the first stage operation, and the change node calculation circuit obtains the code word from the mutex or calculator, and transmits the The code word is sent to the check node calculation circuit, the first syndrome is obtained from the check node calculation circuit, and a decoding success or decoding failure message is sent to the limited state machine; In the second stage state, the finite state machine sends a control signal to the multiplexer to couple the third region to the change node calculation circuit, and drive the change node calculation circuit to execute the first Two-stage operation, the change node calculation circuit regards the codeword as all "0", reads the first soft bit from the third area through the multiplexer, and calculates the codeword and the difference between the change node to generate the flip state, transmit the change node to the check node calculation circuit, obtain the second syndrome from the check node calculation circuit, and according to the first The second syndrome transmits a decoding success or decoding failure message to the finite state machine, stores the inverted state in the second area, and stores the second soft bit in the fourth area; In each iteration of the third stage state, the finite state machine sends a second control signal to the multiplexer to couple the fourth region to the change node calculation circuit, the change node The calculation circuit obtains the change node from the mutex or calculator, reads the second soft bit corresponding to the change node from the fourth area through the multiplexer, and calculates the codeword and the difference between the new change node to generate a new flip state, transmit the new change node to the check node calculation circuit, and obtain the new second check from the check node calculation circuit Sub, according to the new second syndrome, send a decoding success or decoding failure message to the finite state machine, store the new flip state in the second area, and store the new second software bits to the fourth field. The decoding method of the low-density parity-check code as described in claim item 8, comprising: After the second soft bits are stored in the fourth area, the third area is released. A decoding device for low-density parity-check codes, comprising: a change node computing circuit coupled to the static random access memory; and a check node calculation circuit, coupled to the change node calculation circuit, Wherein, when it is detected that the code word is stored in the static random access memory, the decoding device of the low density parity check code enters the first stage state, and in the first stage state, the check The node calculation circuit performs a modular square multiplication method on the code word and the parity check matrix to calculate a first syndrome, wherein the code word includes user data and a low-density parity check code; When the first syndrome indicates that the codeword obtained in the first stage state is incorrect, the decoding device of the low density parity check code enters the second stage state, and in the second stage In the stage state, the change node calculation circuit executes a bit flipping algorithm according to the codeword, a plurality of first soft bits corresponding to the codeword and the first syndrome to generate a plurality of change nodes , and calculate a plurality of second soft bits of the change node; the check node calculation circuit performs a modulo square method on the change node and the parity check matrix to calculate a second syndrome, wherein, Each hard bit in the codeword corresponds to at least one of the first soft bits, which is used to indicate the degree of confidence of the hard bit, and each of the change nodes corresponds to at least one of the second soft bits, used to indicate the degree of confidence in this change node; and When the second syndrome indicates that the changed node generated in the second-stage state is incorrect, the decoding device of the low-density parity-check code repeatedly enters the third-stage state until the decoding is successful or the Until the number of iterations of the third-stage state exceeds a threshold, in each iteration of the third-stage state, the change node calculation circuit according to the change node, the second soft bit corresponding to the change node The element and the second syndrome perform a bit flipping algorithm to generate a plurality of new change nodes, and calculate a plurality of new second soft bits of the new change nodes; the check node calculation circuit performing a modular square multiplication method on the new changed node and the parity check matrix to calculate a new second syndrome. The decoding device of the low-density parity-check code as described in claim 10, comprising: A finite state machine, configured to keep the decoding device of the low-density parity-check code in the first-stage state when the codeword is stored in the SRAM; in response to the first When the syndrome indicates that the codeword obtained in the first stage state is incorrect, the decoding device of the low density parity check is placed in the second stage state; in response to the second check When the syndrome indicates that the change node generated in the second stage state or the previous third stage state is incorrect, the decoding device of the low density parity check is in the third stage state; and controlling said number of iterations to enter said third stage state does not exceed said threshold. The decoding device of the low-density parity-check code as described in claim 10, comprising: Finite State Machine; A first multiplexer, including a first output terminal coupled to the change node calculation circuit, and two first input terminals respectively coupled to the first area and the second area in the SRAM; as well as The second multiplexer includes a second output terminal coupled to the change node calculation circuit, and two second input terminals respectively coupled to the third area and the fourth area in the SRAM, Wherein, the codeword is read from the flash memory module via the flash memory interface and stored in the first area, wherein the flash memory interface generates the first soft bits corresponding to the codeword, and the first soft bits are stored in the third area, Wherein, in the first stage state, the finite state machine sends a first control signal to the first multiplexer to couple the first region to the change node computing circuit, and drive the The change node calculation circuit executes the operation of the first stage, the change node calculation circuit reads the code word from the first area through the first multiplexer, and transmits the code word to the check node for calculation A circuit, obtaining the first syndrome from the check node calculation circuit, sending a decoding success or decoding failure message to the finite state machine according to the first syndrome, and storing the codeword in the finite state machine said second region, enabling said first region to be released; Wherein, in the second stage state, the finite state machine sends a second control signal to the second multiplexer to couple the third region to the change node computing circuit, and drive the The change node calculation circuit executes the operation of the second stage, the change node calculation circuit reads the first soft bit from the third area through the second multiplexer, and transmits the change node to the school A verification node calculation circuit, which obtains the second syndrome from the check node calculation circuit, transmits a decoding success or decoding failure message to the finite state machine according to the second syndrome, and stores the changed node to the second area, and storing the second soft bits into the fourth area so that the third area can be released, Wherein, in each iteration of the third stage state, the finite state machine sends a third control signal to the first multiplexer to couple the second region to the change node computing circuit, Sending a fourth control signal to the second multiplexer to couple the fourth area to the change node calculation circuit, and the change node calculation circuit receives from the second area through the first multiplexer Read the changed node, read the second soft bit corresponding to the changed node from the fourth area through the second multiplexer, and transmit the new changed node to the verification The node calculation circuit obtains the new second syndrome from the check node calculation circuit, and transmits a decoding success or decoding failure message to the finite state machine according to the new second syndrome, and stores the storing the new changed node in the second area, and storing the new second soft bit in the fourth area. The decoding device of the low-density parity-check code as described in claim 10, comprising: a finite state machine; and a multiplexer, comprising an output end coupled to the change node calculation circuit, and two input ends respectively coupled to the first area and the second area in the SRAM, Wherein, the code word is read from the flash memory module via the flash memory interface and stored in the first area, Wherein, in the first stage state, the finite state machine sends a first control signal to the multiplexer to couple the first region to the change node computing circuit, and drive the change node The calculation circuit executes the operation of the first stage. The change node calculation circuit reads the code word from the first area through the multiplexer, transmits the code word to the check node calculation circuit, and obtains the code word from the check node calculation circuit. The check node calculation circuit obtains the first syndrome, transmits a decoding success or decoding failure message to the finite state machine according to the first syndrome, and stores the codeword in the second area, enabling the first region to be released, Wherein, in the second stage state, the finite state machine drives the change node calculation circuit to perform the operation of the second stage, and the change node calculation circuit takes a preset value as the first soft bit, transmitting the change node to the check node calculation circuit, obtaining the second syndrome from the check node calculation circuit, and transmitting a decoding success or decoding failure message to the check node calculation circuit according to the second syndrome a finite state machine storing the changed nodes in the second area, and storing the second soft bits in a third area, Wherein, in each iteration of the third stage state, the finite state machine sends a second control signal to the multiplexer to couple the second region to the change node computing circuit, the The changed node calculation circuit reads the changed node from the second area through the multiplexer, reads the second soft bit corresponding to the changed node from the third area, and transmits the new The change node of the check node is sent to the check node calculation circuit, the new second syndrome is obtained from the check node calculation circuit, and the decoding success or decoding failure message is sent to the new second syndrome according to the new second syndrome. The finite state machine stores the new changed node in the second area, and stores the new second soft bit in the third area. The decoding device of the low-density parity-check code as described in claim 10, comprising: Finite State Machine; mutex or calculator; and a multiplexer, comprising an output end coupled to the change node calculation circuit, and two input ends respectively coupled to the third area and the fourth area in the SRAM, wherein the codeword is read from a flash memory module via a flash memory interface and stored in the first area of the static random access memory, Wherein, the second area in the static random access memory stores an inversion state, and the inversion state is initially all "0", Wherein, the flash memory interface generates the first soft bit corresponding to the codeword, and the first soft bit is stored in the third area, Wherein, the exclusive OR calculator performs exclusive OR calculation on the codeword in the first area and the inversion state in the second area and outputs the calculation result to the change node calculation circuit, Wherein, in the first stage state, the finite state machine drives the change node calculation circuit to perform the operation of the first stage, and the change node calculation circuit obtains the codeword from the mutex OR calculator, transmitting the code word to the check node calculation circuit, obtaining the first syndrome from the check node calculation circuit, and transmitting a decoding success or decoding failure message to the check node calculation circuit according to the first syndrome The finite state machine described above, Wherein, in the second stage state, the finite state machine sends a control signal to the multiplexer to couple the third region to the change node calculation circuit, and drive the change node calculation circuit Executing the operation of the second stage, the change node calculation circuit regards the code word as all "0", reads the first soft bit from the third area through the multiplexer, and calculates the The difference between the code word and the changed node to generate the flipped state, transmit the changed node to the check node calculation circuit, obtain the second syndrome from the check node calculation circuit, according to the The second syndrome transmits a decoding success or decoding failure message to the finite state machine, storing the flipped state to the second area, and storing the second soft bit to the fourth area, Wherein, in each iteration of the third stage state, the finite state machine sends a second control signal to the multiplexer to couple the fourth region to the change node computing circuit, the The change node calculation circuit obtains the change node from the mutex or calculator, reads the second soft bit corresponding to the change node from the fourth area through the multiplexer, and calculates the The difference between the code word and the new change node is used to generate a new flip state, and the new change node is sent to the check node calculation circuit, and the new second change node is obtained from the check node calculation circuit. a syndrome, sending a decoding success or decoding failure message to the finite state machine according to the new second syndrome, storing the new flipped state in the second area, and storing the new second syndrome Two soft bits to the fourth field.

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