CN111046334A - Cyclic matrix fast generation method based on digital signal processor - Google Patents
Cyclic matrix fast generation method based on digital signal processor Download PDFInfo
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Abstract
The invention provides a method for quickly generating a cyclic matrix based on a digital signal processor, which has the following basic principle: filling the b-bit generated vector into m 32-bit registers R0、R1、……、Rm–1The j-th row vector of the circulant matrix can be generated sequentially by circularly right-shifting the effective content of the group of registers by 32 bits or 33 bits, thereby obtaining the whole circulant matrix, wherein b is a positive integer and b is 2n-1 or b ═ 2n，m＝2n–5，n≥6，j＝(32*i)mod(2n-1), i ═ 0, 1, … …, b-1, mod denotes the modulo operation. The invention has high speed of generating the cyclic matrix and is suitable for the digital signal processor with single core/multi-core or single operation unit/multi-operation unit.
Description
Technical Field
The invention relates to the field of channel coding, in particular to a method for quickly generating a cyclic matrix based on a digital signal processor.
Background
The quasi-cyclic low-density parity-check (QC-LDPC) code has excellent performance and is widely applied to a plurality of systems such as CDR, DTMB-A, near-earth communication, deep space communication and the like. Generation matrix and check matrix of QC-LDPC codeAre arrays of b x b circulant matrices. For QC-LDPC codes in CDRs, b is 256; for QC-LDPC codes in DTMB, b 127; for QC-LDPC codes in DTMB-a, b is 128 and 512; for QC-LDPC codes in near-earth communications, b is 511; for QC-LDPC codes in deep space communications, b is 32, 64, 128, 256, 512, 1024 and 2048. Obviously, the parameter b in these systems is either a power of 2 or a power of 2 minus one, i.e. b is 2nOr b is 2n-1, wherein n is a positive integer.
From the row perspective, the first row of the circulant matrix is the result of the last row being cyclically shifted to the right by one bit, and each of the remaining rows is the result of the last row being cyclically shifted to the right by one bit. Thus, any circulant matrix is determined entirely by its leading row, which is referred to as its generation vector. That is, if the generated vector of one circulant matrix is known, the vectors of the 0 th row, the 1 st row, … …, and the b-1 th row of the circulant matrix are sequentially generated by the operation of shifting right by one bit, and the whole circulant matrix is obtained.
A field programmable logic array (FPGA) processor is well suited to enable the generation of circulant matrices. For the above-mentioned b with various values, the generated vector is stored in b 1-bit registers in the FPGA chip, and the whole cyclic matrix can be easily generated by circularly shifting right one bit for many times. Only 1 clock cycle is needed for generating each row, and b clock cycles are needed for generating the whole cyclic matrix.
Compared with FPGA, the Digital Signal Processor (DSP) has the advantages of high working frequency, low power consumption, short development period, good portability, easy maintenance and the like. However, DSP is not good at right-shifting by one bit for long vector cycles where b is large. The registers in the DSP chip are typically 32 bits, with m being 2n/32＝2n–5. For the above various values of b, the generated vector is stored in m 32-bit registers R in the DSP chip0、R1、……、Rm–1Middle, register RkIs Rk,31The lowest order is Rk,0Wherein k is more than or equal to 0 and less than or equal to m-1. When b is 2n1, the vector is generated to fill the set of registers left-aligned, register R is not used0Lowest order of (R)0,0Cycling right on the generated vectorThe operation of shifting a bit is shown in FIG. 1; and when b is 2nThe resulting vector fills all registers and the operation of shifting the resulting vector one bit to the right is shown in figure 2. Generating each row of the circulant matrix using a DSP requires multiple clock cycles, with the difficulty being shifting between registers. In particular, the difficulty is to put the register RkLowest order of (R)k,0Shift right to register Rk-1Highest bit R ofk-1,31(1. ltoreq. k. ltoreq. m-1), and R in FIG. 10,1And R in FIG. 20,0Move to register Rm-1Highest bit R ofm-1,31. Taking the former as an example, the common way is to first register Rk-1Right shifted by one bit, according to Rk,0Content pair R in (1)k-1,31Clearing or setting: if R isk,0If the content in (1) is "0", then R is selectedk-1,31Clearing; otherwise, for Rk-1,31And setting. R in FIG. 10,1And R in FIG. 20,0Move to register Rm-1Highest bit R ofm-1,31A similar operation is performed. Any row of the circulant matrix is generated m times. For a common DSP, 3-5 clock cycles are needed for one operation, so that 3-5 m clock cycles are needed for any row of the cyclic matrix generated by the DSP, and the clock cycle is usually much longer than 1 clock cycle needed by the FPGA processor. It can be seen that the existing solution of using DSP to generate circulant matrix has the disadvantage of slow running speed. At present, a circulant matrix generation scheme based on an FPGA processor is almost adopted.
Disclosure of Invention
The existing scheme for generating the cyclic matrix by using the DSP has the defect of low running speed, and aiming at the technical problem, the invention provides a rapid cyclic matrix generation method based on the DSP.
The steps for fast generating the circulant matrix based on the DSP are shown in fig. 6, and the basic principle is: filling the b-bit generated vector into m 32-bit registers R0、R1、……、Rm–1The j-th row vector of the circulant matrix can be generated sequentially by circularly right-shifting the effective content of the group of registers by 32 bits or 33 bits, thereby obtaining the whole circulant matrix, wherein b is a positive integer and b is 2n-1 or b ═ 2n，m＝2n–5，n≥6，j＝(32*i)mod(2n-1), i ═ 0, 1, … …, b-1, mod denotes the modulo operation.
The method for generating the circulation matrix has high speed and is suitable for digital signal processors of single core/multi-core or single operation unit/multi-operation unit.
The advantages and methods of the present invention will be further understood by reference to the following detailed description and drawings.
Drawings
FIG. 1 shows b-2n-1 time right shift by one bit of the generated vector in m 32-bit registers;
FIG. 2 shows that b is 2nThe schematic diagram of circularly right shifting the generated vector in m 32-bit registers by one bit;
FIG. 3 shows b-2n-a schematic representation of a cyclic right shift of 32 bits for a resulting vector in m 32-bit registers at 1;
FIG. 4 shows that b is 2nSchematic diagram of cyclic right shift 32 bits of the generated vector in m 32-bit registers;
FIG. 5 shows that b is 2nSchematic diagram of cyclic right shift by 33 bits for the generated vector in m 32-bit registers;
FIG. 6 shows that b is 2n-1 and b ═ 2nA flow chart for generating a circulant matrix based on the DSP.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
Registers in a DSP processor are 32 bits and moving the contents of one register to another requires only 1 clock cycle, so moving the contents of a vector to the right is relatively simple and fast to generate 32 bits of a cycle. In fig. 3 and 4, b is 2n-1 and b ═ 2nThe schematic diagram of the generation vector in the register set is circularly shifted to the right by 32 bits.
In FIG. 3, the generated vector left-aligns fills m registersRegister, not using register R0Lowest order of (R)0,0. The operation of cyclically right-shifting the generated vector by 32 bits is as follows: register R0Right shifted by one bit, according to R1,0Content pair R in (1)0,31Zero clearing or setting, register R0The content in (1) is moved to the register Rm-1Middle, register RkThe content in (1) is moved to the register Rk-1Wherein k is more than or equal to 1 and less than or equal to m-1. The above operation requires m +2 to m +4 clock cycles, and when m is large, the required time is about 1/3 to 1/5 for the right shift operation of the generated vector cycle. When the above operation is completed, the 32 nd row vector of the circulant matrix is stored in the register set. Repeating the above operations will generate the 0 th, 32 th, … … th, 2 nd of the circulant matrix in turnn–32、1、33、……、2n–31、……、30、62、……、2n–2、31、63、……、2n33 row vectors, i.e. the j ═ (32 × i) mod (2) which in turn generates the circulant matrixn-1) row vectors, wherein i ═ 0, 1, … …, 2n-2 (═ b-1), mod denotes the modulo operation. This generates all row vectors of the circulant matrix. The above scheme requires m +2 to m +4 clock cycles to generate any row vector of the circulant matrix, which is much faster than the prior art scheme of shifting the circulant vector by one bit to the right, and when m is larger, the time required is about 1/3 to 1/5 of the prior art scheme.
In fig. 4, the generated vector fills m registers. The operation of cyclically right-shifting the generated vector by 32 bits is as follows: register R0The content in (1) is moved to the register Rm-1Middle, register RkThe content in (1) is moved to the register Rk-1Wherein k is more than or equal to 1 and less than or equal to m-1. The above operation requires m clock cycles, the time required is 1/3-1/5 for the generation of the vector cycle right shift operation. When the above operation is completed, the 32 nd row vector of the circulant matrix is stored in the register set. Repeating the above operations will generate the 0 th, 32 th, … … th, 2 nd of the circulant matrix in turnn–32、0、32、……、2n-32, … … row vectors. To avoid repeated generation of the same row vector, the 2 nd generation is performed for the first timenAfter 32 lines of vectors, the register bank needs to be cycled throughShifted right by 33 as shown in fig. 5. That is, the register bank is shifted right by 32 bits m-1 cycles first, and then shifted right by 33 bits once. Repeating the above operations will generate the 0 th, 32 th, … … th, 2 nd of the circulant matrix in turnn–32、1、33、……、2n–31、……、30、62、……、2n–2、31、63、……、2n-1 row vector, i.e. the j ═ (32 × i) mod (2) which in turn generates the circulant matrixn-1) row vectors, wherein i ═ 0, 1, … …, 2n-1 (═ b-1). This generates all row vectors of the circulant matrix. The operation of FIG. 5 to cycle the register set right by 33 bits is as follows: for register R0Right shifted by one bit, according to R1,0Content pair R in (1)0,31Clearing or setting the register R thus obtained0The content in (1) is moved to the register Rm-1Performing the following steps; for register Rm-1Right shifted by one bit, according to R0,0Content pair R in (1)m-1,31Clearing or setting the register R thus obtainedm-1The content in (1) is moved to the register Rm-2Performing the following steps; for register Rk-1Right shifted by one bit, according to Rk,0Content pair R in (1)k-1,31Clearing or setting the register R thus obtainedk-1The content in (1) is moved to the register Rk-2Wherein k is more than or equal to 2 and less than or equal to m-1. It takes m clock cycles to generate a vector cycle shifted to the right by 32 bits, and the time required to generate a vector cycle shifted to the right by 33 bits is the same as the time required to shift the cycle to the right by one bit, also 3m to 5m clock cycles. In the process of generating the circulant matrix, the ratio of the number of times of right shift of the register group by 32 bits to the number of times of right shift of the register group by 33 bits is (m-1): 1. therefore, a certain row of vectors of the cyclic matrix needs m +2 to m +4 clock cycles on average, which is much faster than the prior art scheme of shifting the generated vectors to the right by one bit, and when m is larger, the time is about 1/3 to 1/5 of the prior art scheme.
According to the above discussion, the present invention provides a method for fast generating a circulant matrix based on a DSP, and the basic principle thereof is: filling the b-bit generated vector into m 32-bit registers R0、R1、……、Rm–1The j-th row vector of the circulant matrix can be generated sequentially by circularly right-shifting the effective content of the group of registers by 32 bits or 33 bits, thereby obtaining the whole circulant matrix, wherein b is a positive integer and b is 2n-1 or b ═ 2n，m＝2n–5，n≥6，j＝(32*i)mod(2n-1), i ═ 0, 1, … …, b-1. Theoretical analysis shows that the above method is much faster than the prior art scheme of circularly right shifting the generating vector by one bit, and when m is larger, the time is about 1/3-1/5 of the prior art scheme. The specific process of generating the circulant matrix based on the DSP is shown in fig. 6.
In fig. 6, when b is 2nIn case-1, the steps of generating the circulant matrix based on the DSP are described in detail as follows:
step 3, circularly right shifting the effective content in the register group by 32 bits to obtain a jth row vector;
step 4, if j is more than or equal to 2n-33, the next step is performed; otherwise, jumping to the step 2;
step 5, if j is equal to (2)n-33), the cyclic matrix generation is completed; otherwise, executing the next step;
step 6, j is decreased (2)n-33), jumping to step 3.
In fig. 6, when b is 2nThen, the steps of generating the circulant matrix based on the DSP are described in detail as follows:
step 3, circularly right shifting the content in the register group by 32 bits to obtain a jth row vector;
step 4, if j is more than or equal to 2n32, then the next step is performed; otherwise, jumping to the step 2;
step 5, if j is equal to (2)n-1), the cyclic matrix generation is completed; otherwise, executing the next step;
step 6, j is decreased (2)n–33)；
And 7, circularly right shifting the content in the register group by 33 bits to obtain a jth row vector, and jumping to the 4 th step.
In the invention, the core operation is to circularly right shift the effective content of a group of registers formed by m 32-bit registers by 32 bits or 33 bits, and determines that m +2 to m +4 clock cycles are averagely needed for generating a certain row vector of a circular matrix. The time consumption is estimated based on a single-core or single-operation-unit DSP, and when a multi-core or multi-operation-unit DSP is adopted, the required time is greatly reduced.
Taking the cyclic matrix of the QC-LDPC code used in the near-earth communication as an example, b is 511 and m is 16. If a common DSP and the existing scheme are adopted, 48-80 clock cycles are needed for generating a certain row vector of the circular matrix. If a common DSP and the rapid method provided by the invention are adopted, 18-20 clock cycles are needed for generating a certain row vector of the cyclic matrix, and the speed is improved by 2.7-4 times. If the DSP adopts TMS320C6748 with 8 arithmetic units of TI company, 16 32-bit registers B24, B25, B26, B27, B28, B29, B30, B31, A24, A25, A26, A27, A28, A29, A30 and A31 in the DSP chip are registers R for storing generated vectors0～R15Registers A0 and B0 are used as register aids in the cycle right shift. General register R0～R15The assembly code of (1) is circularly right-shifted by 32 bits as follows:
in the above code, | | denotes that the instruction of the current line is executed in parallel with the instruction of the previous line. It can be seen that the TMS320C6748 is used for generating a certain row vector of the 511 multiplied by 511 circular matrix only needs 3 clock cycles, and the speed of the method is 16-27 times that of the existing scheme based on the common DSP and 6-7 times that of the proposed scheme based on the common DSP.
Taking the cyclic matrix of the QC-LDPC code with b being 512 as an example, m being 16. If a common DSP and the existing scheme are adopted, 48-80 clock cycles are needed for generating a certain row vector of the circular matrix. If adoptedThe common DSP and the rapid method provided by the invention have the advantages that 18-20 clock cycles are needed for generating a certain row vector of the cyclic matrix, and the speed is increased by 2.7-4 times. If the DSP adopts TMS320C6748 with 8 arithmetic units of TI company, 16 32-bit registers B24, B25, B26, B27, B28, B29, B30, B31, A24, A25, A26, A27, A28, A29, A30 and A31 in the DSP chip are registers R for storing generated vectors0～R15Registers A0, A1, A2, A3, B0, B1, B2, and B3 are used as registers to assist in the right shift of the loop. General register R0～R15The assembly code of (1) is circularly right-shifted by 32 bits as follows:
only 3 clock cycles are required to execute the code. General register R0～R15The assembly code of (1) is circularly right shifted by 33 bits as follows:
only 9 clock cycles are required to execute the code. Calculation shows that, the average of a certain row vector of the 512 × 512-order cyclic matrix generated by using the TMS320C6748 only needs 3 × 15/16+9 × 1/16 ≈ 3.4 clock cycles, and the speed is 14.2-23.7 times of that of the conventional scheme based on the common DSP and 5.3-5.9 times of that of the proposed scheme based on the common DSP.
In summary, compared with a DSP based on a single core or a single operation unit, the time required for generating the circular matrix by the DSP adopting a multi-core or multi-operation unit is greatly reduced.
For b 511 and b 512, 3 and 3.4 clock cycles are respectively needed for generating a certain row of vectors of the circulant matrix by using the TMS320C6748 DSP, while 1 clock cycle is needed for generating a certain row of vectors of the circulant matrix based on the FPGA. Although the former speed is slower than the latter, the difference is not large, and the DSP has the advantages of high working frequency, low power consumption, short development period, good portability, easy maintenance and the like, so that the generation of the cyclic matrix based on the DSP is a preferable scheme.
The above description is only one embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can change or replace the present invention within the technical scope of the present invention without creative efforts, and the present invention shall be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope defined by the claims.
Claims (3)
1. A quick cyclic matrix generating method based on digital signal processor features that the generated matrix and check matrix of QC-LDPC code are both array composed of b × b cyclic matrix, where b is positive integer and b is 2n-1 or b ═ 2nN is more than or equal to 6, the generation method fills the b-bit generation vector into m 32-bit registers R0、R1、……、Rm–1The j row vector of the cyclic matrix can be generated sequentially by circularly right shifting the effective content of the group of registers by 32 bits or 33 bits, so as to obtain the whole cyclic matrix, wherein m is 2n–5，j＝(32*i)mod(2n-1), i ═ 0, 1, … …, b-1, mod denotes the modulo operation.
2. The method for rapidly generating circulant matrices based on digital signal processors as claimed in claim 1, wherein when b-2n1, the step of generating the circulant matrix is:
step 1, initializing j to 0, generating vector left-aligned filling m registers, and not using register R0Lowest order of (R)0,0；
Step 2, j is increased by 32;
step 3, circularly right shifting the effective content in the register group by 32 bits to obtain a jth row vector;
step 4, if j is more than or equal to 2n-33, the next step is performed; otherwise, jumping to the step 2;
step 5, if j is equal to (2)n-33), the cyclic matrix generation is completed; otherwise, executing the next step;
step 6, j is decreased (2)n-33), jumping to step 3.
3. The method for rapidly generating circulant matrices based on digital signal processors as claimed in claim 1, wherein when b-2nThen, the step of generating the circulant matrix is:
step 1, initializing j to 0, and generating vectors to fill m registers;
step 2, j is increased by 32;
step 3, circularly right shifting the content in the register group by 32 bits to obtain a jth row vector;
step 4, if j is more than or equal to 2n32, then the next step is performed; otherwise, jumping to the step 2;
step 5, if j is equal to (2)n-1), the cyclic matrix generation is completed; otherwise, executing the next step;
step 6, j is decreased (2)n–33)；
And 7, circularly right shifting the content in the register group by 33 bits to obtain a jth row vector, and jumping to the 4 th step.
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| US20100162074A1 (en) * | 2008-12-19 | 2010-06-24 | Electronics And Telecommunications Research Institute | Apparatus and method for coding qc-ldpc code |
| CN102882532A (en) * | 2012-09-27 | 2013-01-16 | 苏州威士达信息科技有限公司 | LDPC (low density parity check) encoder in CMMB (China mobile multimedia broadcasting) based on rotate right accumulation and encoding method |
| CN103236850A (en) * | 2013-04-19 | 2013-08-07 | 荣成市鼎通电子信息科技有限公司 | Rotate left-based quasi-cyclic (QC) matrix serial multiplier in deep space communication |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100162074A1 (en) * | 2008-12-19 | 2010-06-24 | Electronics And Telecommunications Research Institute | Apparatus and method for coding qc-ldpc code |
| CN102882532A (en) * | 2012-09-27 | 2013-01-16 | 苏州威士达信息科技有限公司 | LDPC (low density parity check) encoder in CMMB (China mobile multimedia broadcasting) based on rotate right accumulation and encoding method |
| CN103236850A (en) * | 2013-04-19 | 2013-08-07 | 荣成市鼎通电子信息科技有限公司 | Rotate left-based quasi-cyclic (QC) matrix serial multiplier in deep space communication |
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