CN102064835A - Decoder suitable for quasi-cyclic LDPC decoding - Google Patents

Abstract

The invention discloses a decoder suitable for quasi-cyclic low density parity check (LDPC) decoding. The decoder comprises a control unit, an address generation unit, a channel value storage unit, a mutual information storage cell, a matrix value storage cell, a variable node processing unit, a check node processing unit, a selection unit and an output unit; and the control unit generates an appropriate control signal according to input states and parameters to coordinate iterative decoding processing of all modules of the decoder. The minimized design strategy of the mutual information storage cell is adopted by the decoder provided by the invention; and due to the one-to-one correspondence principle of non-null values of the mutual information storage cell and a base matrix, the expenditure of a memory is reduced to the maximum extent. An offset minterm algorithm is adopted by the check node processing unit so as to reduce implementation complexity, and the decoding performance is improved through appropriate offset, the check node processing unit with any degree can be constructed by a layering method and the decoder is suitable for regular and irregular LDPC codes.

Description

Be applicable to the quasi-cyclic LDPC decoders for decoding

Technical field

The present invention relates to channel coding technology field, the communications field, relate in particular to a kind of quasi-cyclic LDPC decoders for decoding that is applicable to.

Background technology

In wireless communication system,, will inevitably introduce distortion and signal decision mistake to the transmission data because transmission channel exists noise, decline, multipath.The signal error that takes place in the transmission is found, corrected to channel coding technology by add redundancy symbol in information sequence, thereby improve the reliability of system.

Low density parity check code (LDPC) sign indicating number is a kind of channel coding/decoding method that can approach the excellent performance of Shannon (Shannon) limit.The standard Soft decision decoding of LDPC sign indicating number adopts a kind of belief propagation algorithm, is referred to as sum-product algorithm (SPA).Sum-product algorithm makes the LDPC sign indicating number obtain optimum decoding performance, but the hardware implementation complexity of the hyperbolic cotangent function algorithm in the check node calculation is very high.Minterm algorithm (MS) has replaced complicated hyperbolic cotangent function with minimum value function, greatly reduces the decoding algorithm complexity, but performance has bigger loss.Biasing minterm algorithm is introduced the performance loss that bias has compensated the MS algorithm in check node calculation on the basis of MS algorithm.

At present, the most of LDPC sign indicating number that uses in practical communication system is quasi-cyclic LDPC sign indicating number, and these quasi-cyclic LDPC sign indicating numbers are divided into rule type and non-rule type, the LDPC sign indicating number of rule type is meant that all check-node number of degrees of check matrix are identical, the number of degrees of all variable nodes are also identical, the LDPC sign indicating number of non-rule type then has the different number of degrees, and the introducing of this non-rule can bring the raising on the LDPC code performance.

At the extensive use of quasi-cyclic LDPC code, propose a kind ofly to be suitable for that the decoder of non-rule and rule type is a problem demanding prompt solution in the quasi-cyclic LDPC code.

Summary of the invention

(1) technical problem that will solve

In view of this, main purpose of the present invention is to provide a kind of decoder that is applicable to non-rule and rule type in the quasi-cyclic LDPC code.

(2) technical scheme

For achieving the above object, the invention provides a kind of quasi-cyclic LDPC decoders for decoding that is applicable to, comprising:

Control unit: produce control signal according to the control signal of input and status signal, coordinate the iterative decoding process of decoder at other functional units in the decoder;

Address-generation unit: the read/write address and corresponding read-write enable signal and the chip selection signal that are used for producing channel value memory cell and interactive information memory cell;

Channel value memory cell: be used to store the M bit quantization channel information value of separating after the mapping, if the columns of the basic matrix of quasi-cyclic code correspondence is NCOL, spreading factor is Z, then Dui Ying channel value memory cell is made up of NCOL group single port RAM, the size of every group of single port RAM is Z * M bit, according to the application size of one-port memory reality, every group of single port RAM size that may need is bigger slightly than Z * M;

Interactive information memory cell: be used for the information that storage of variables node processing unit and code check node processing unit transmit, if the number of non-null value is W in the quasi-cyclic code basic matrix, then Dui Ying interactive information memory cell is made up of W group two-port RAM, the size of every group of two-port RAM is Z * M bit, needs here according to the big or small needs of actual storage the physical storage size to be enlarged a little;

Matrix value memory cell: the numerical values recited that is used for storing the basic matrix non-null value;

Variable node processing unit: handle (VNU) by NCOL parallel variable node and form, finish the processing of variable node;

The code check node processing unit: if the line number of basic matrix is NROW, then the check-node unit is made up of NROW code check node processing (CNU) unit, finishes the processing of check-node;

Selected cell: the information that selection deposits the interactive information memory cell in is from variable node processing unit or code check node processing unit;

Output unit: the output decoding unit of decoder.

In the such scheme, described control unit is the finite state machine of one 9 state, comprises: idle condition, channel value store status, VNU for the first time computing mode, VNU for the first time to CNU transition state, CNU computing mode, VNU computing mode, VNU to CNU transition state, CNU to VNU transition state and output decoding state.

In the such scheme, described address-generation unit produces the read/write address of channel information memory cell and interactive information memory cell and read-write enables and chip selection signal, wherein the read/write address of interactive information memory cell adopts the method that writes back with the location, obtain information from the interactive information memory cell, with the information via CNU that obtains with write back to address identical when reading after VNU calculates.

In the such scheme, described channel information memory cell just begins to deposit in effective channel information value after detecting code word and beginning, the principle of storage is one group by spreading factor and is deposited among the corresponding single port RAM, after the channel information value of a code word has been deposited, just begin iterative decoding process, in the decoding iterative process only when variable node is handled ability from value wherein.

In the such scheme, described interactive information memory cell need be carried out initialized operation to the interactive information memory when initial CNU calculates, read the value of information and adopt the method that writes back with the location to write back in the interactive information memory through VNU or CNU calculating back in the interative computation process from the interactive information memory.

In the such scheme, described matrix value memory cell is used for storing the non-null value numerical values recited of basic matrix, produces the initial address that reads the interactive information memory when CNU calculates.

In the such scheme, described variable node processing unit is made up of NCOL parallel VNU, and VNU has adopted adder tree corresponding with the variable node annexation and bit wide to adjust the circuit composition.

In the such scheme, the computing that described variable node is finished is expressed as follows:

Variable node handle to calculate the information that passes to check-node j from variable node i, by as shown in the formula calculating

$L\left(q_{\mathrm{ij}}\right)=p_i+\underset{j^{\′}\∈C_i\backslash j}{\mathrm{\Σ}}L\left(r_{j^{\′}i}\right)$

C wherein _iJ the set representing to link to each other except other check-nodes of check-node j with variable node i; Simultaneously decoder is made a hard decision to variable node i herein, by as shown in the formula calculating:

$L\left(Q_i\right)=p_i+\underset{j\∈C_i}{\mathrm{\Σ}}L\left(r_{\mathrm{ji}}\right)$

If

Otherwise

When reaching maximum iteration time, then finish computing, otherwise continue interative computation.

In the such scheme, described code check node processing unit is made up of NROW parallel CNU, and CNU has adopted the hierarchical structure of band biasing minterm algorithm, and this method comprises:

$L\left(r_{\mathrm{ji}}\right)=\underset{i^{\′}\∈V_j\backslash i}{\mathrm{\Π}}\mathrm{sign}\left[L\left(q_{i^{\′}j}\right)\right]\·\max \left\{\right[\underset{i^{\′}\∈V_j\backslash i}{\min }\left(\right|L\left(q_{i^{\′}j}\right)\left|\right)-\mathrm{\β}],0\}$

V wherein _jI the set representing to link to each other except other check-nodes of variable node i with check-node j, β represents bias; Here, its expression formula is deformed into the expression formula that can adopt the stratification hardware designs, as follows:

$L(x\⊕y)=\mathrm{sign}\left(\mathrm{xy}\right)\min \left\{\right|x|,|y\left|\right\}+\mathrm{\β}$

Wherein x and y represent two numerical value of input validation node processing unit, and adopting bit wide is the signed number of 6 bits, and the big I of β obtains according to emulation, obtain ± the 3rd, performance best choice during bit wide 6 bits;

Stratification expansion relatively can obtain the CNU of the even number input of any number of degrees based on this two values, if the check-node number of degrees are odd number, then the greatest measure of representing with 6 bits 31 is configured to the CNU of the input of even number as an input.

(3) beneficial effect

From technique scheme as can be seen, the present invention has following beneficial effect:

1, the quasi-cyclic LDPC decoders for decoding that is applicable to provided by the invention, interactive information memory cell and basic matrix non-null value one-to-one principle have at utmost reduced the expense of memory.

2, the quasi-cyclic LDPC decoders for decoding that is applicable to provided by the invention, biasing minterm algorithm reduces complexity, and select suitable amount of bias and improve decoder performance, can utilize simultaneously hierarchical setting to construct and be fit to any quasi-cyclic LDPC decoder, comprise rule and non-rule.

Description of drawings

The present invention is further described below in conjunction with drawings and Examples:

Fig. 1 is the structural representation that is applicable to the quasi-cyclic LDPC decoders for decoding provided by the invention;

Fig. 2 is the state transition graph of the finite state machine of decoder control unit;

Fig. 3 is that the back method key diagram is write in the same location of interactive information memory;

Fig. 4 is the structure chart of VNU;

Fig. 5 is the VNU circuit structure diagram of 4 inputs;

Fig. 6 is the ber curve figure under the different deviants;

Fig. 7 is the CNU structure chart of 2 inputs;

Fig. 8 is the CNU structure chart of 4 inputs;

Fig. 9 is the CNU structure chart of 8 inputs.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

This example is an example with the LDPC sign indicating number of IEEE 802.11n.Code check among the IEEE 802.11n is that 1/2 code length is that the basis matrix of 1944 LDPC sign indicating number is as follows:

The LDPC sign indicating number of its matrix right and wrong rule, code length is 1944, spreading factor is 81,81 * 81 full null matrix is represented in the place that in the basis matrix is "-", what be that the place of " 0 " represents is 81 * 81 unit matrix, and the magnitude value that has in other places has been represented the matrix that the ring shift right to 81 * 81 unit matrix obtains.

The quasi-cyclic LDPC decoders for decoding that is applicable to provided by the invention has been used interactive information memory miniaturized design strategy, and interactive information memory cell and basic matrix non-null value one-to-one principle have at utmost reduced the expense of memory.Code check node processing has adopted biasing minterm algorithm to reduce complexity, and selects suitable amount of bias and improve decoder performance, can utilize simultaneously hierarchical setting to construct and be fit to any quasi-cyclic LDPC decoder, comprises rule and non-rule.

Provided by the inventionly be applicable to the quasi-cyclic LDPC decoders for decoding as shown in Figure 1: comprise control unit, address-generation unit, channel value memory cell, interactive information memory cell, matrix value memory cell, variable node processing unit, code check node processing unit, selected cell and output unit.

Wherein, control unit is the control signal that produces all the other modules of decoder according to the control signal of input and status signal, coordinates the iterative decoding process of decoder, the transition diagram of its state as shown in Figure 2, wherein:

Idle: the decoder idle condition, decoder is not worked, and the decoder of idle state detects " code word opening flag " signal, as to detect be to represent then that code word had begun at 1 o'clock, enters the cram state;

Cram: the store status of channel value, the chip selection signal, the read-write that produce the channel value memory cell according to " input effectively " signal controlling address-generation unit enable and address signal, finish the storage of a code word when the channel value memory cell after, the channel value memory cell feeds back to " channel value has been deposited " signal of control unit, at this moment begin iterative decoding process, enter the vnu_first state;

Vnu_first: interactive information initialize memory state, because the showing of informational needs in the interactive information memory, the numerical value that reads from the interactive information memory at this state variations per hour node should be 0, carrying out variable node with the respective channel value that reads from the channel value information memory cell handles, according to the method that writes back with the location variable node is handled the information that obtains simultaneously and write back to the initialization procedure of having finished the interactive information memory in the interactive information memory, enter the vnu_first2cnu state then;

Vnu_first2cnu: because the time-delay clock number of the progression of the streamline of variable node processing unit decision, here the progression of She Ji variable node processing unit is 3 grades, so this state needs 3 clocks, the main data of waiting for that variable node is handled write back the interactive information memory fully, enter the cnu state then;

Cnu: mainly be the code check node processing process, from the interactive information memory, obtain data and be sent to the code check node processing unit and handle the information that obtains, enter the cnu2vnu state then being written in the interactive information memory according to the method that writes back with the location;

Cnu2vnu: because the time-delay clock number of the progression of the streamline of code check node processing unit decision, here the progression of She Ji code check node processing unit is 3 grades, so this state needs 3 clocks, the main data of code check node processing of waiting for write back the interactive information memory fully, enter the vnu state then;

Vnu: variable node processing procedure, need utilize the data in channel value memory cell and the interactive information to come together to finish the variable node processing procedure, and among the vnu_first entering variable node processing unit be data and complete zero in the channel value memory cell, promptly with complete zero data that substituted in the interactive information memory, all the other processes are identical with vnu_first, whether the number of times that detects iterative decoding in this process has reached maximum iterative decoding number of times, if reached, then enter decoding output state out, otherwise continue iterative process as the circulation among Fig. 2;

Out: the decoding output state, to finish the decoding bit serial of decoder by a buffer and export, buffer adopts register to realize.

Address-generation unit is used for producing read/write address and the corresponding read-write enable signal and the chip selection signal of channel value memory cell and interactive information memory cell, when the state of channel value storage, need to produce read/write address, chip selection signal and the read-write enable signal of channel value memory cell; When variable node is handled, need to produce read/write address, chip selection signal and the read-write enable signal of channel value memory cell, also need to produce read/write address, chip selection signal and the read-write enable signal of interactive information memory cell; When code check node processing, need to produce read/write address, chip selection signal and the read-write enable signal of interactive information memory cell;

The channel value memory cell is used to store the M bit width quantized channel value of information of separating after the mapping;

The interactive information memory cell is used for the information of storage of variables node processing unit and the transmission of code check node processing unit, the read-write mode of information is the method that writes back with the location, the connection layout of itself and address-generation unit as shown in Figure 3, address-generation unit produce the interactive information memory cell read the address after, directly utilize the method for what register series connection to come the cache read address to obtain write address, this method that writes back with the location is simple, but needs more register;

The matrix value memory cell is used for storing basic matrix non-null value numerical values recited, in address-generation unit, produce the interactive information memory cell read the address time needs;

The variable node processing unit is finished the processing of variable node, is 1944 according to code length, and code check is that the number of degrees of variable node of 1/2 matrix are as follows: the number of degrees are that 2 (12), the number of degrees are that 3 (8), the number of degrees are that 4 (1), the number of degrees are 11 (3).Like this, need the VNU of four kinds of sizes, i.e. 2 input VNU, 3 input VNU, 4 input VNU, 11 input VNU.The structure chart of VNU such as Fig. 4 are made up of an adder tree and subtraction and bit wide adjusting module.All on its basis it is expanded for the VNU of the different number of degrees and to obtain.Fig. 5 is the circuit structure diagram of VNU of 4 inputs, is to expand to obtain on the basis of Fig. 4, and the VNU of other any number of degrees can construct with reference to Fig. 4 and Fig. 5 and obtain.

The processing of check-node is finished in the code check node processing unit, by equivalence transformation to the minterm of band biasing, the CNU of any number input that the code check node processing of band biasing minterm can be represented be converted to the combination of 2 input CNU, the CNU of 2 inputs handle be equivalent to as shown in the formula

$L(x\⊕y)=\mathrm{sign}\left(\mathrm{xy}\right)\min \left\{\right|x|,|y\left|\right\}+\mathrm{\β}$

What wherein β represented is signed deviant.Choosing of β value in the real system exploitation has a direct impact decoding performance, by the RTL fixed-point simulation, obtains the ber curve of different beta value as shown in Figure 6, and when the absolute value of β got 3, hardware performance was best, so the β value is 3.

The corresponding design of in the CNU design, having adopted a kind of stratification, CNU for the different number of degrees can construct by the CNU and the register of 2 inputs, the method of this stratification is not only simple on the structure, and can make things convenient for the structure of the CNU unit of the different number of degrees, is particularly suitable for the application of non-regular code.The number of degrees of the check-node of (1944,972) check matrix have two kinds: 7 and 8, need 12 CNU unit altogether.That the code check node processing unit adopts here all is 8 input CNU, and when the number of degrees are 7 to be, idle position is set to positive maximum 31 (if information adopt be that 6 bit signed numbers are represented).The CNU of 8 inputs can form with the CNU and the register of a plurality of 2 inputs.Fig. 7 is the 2 designed CNU that import, and what Fig. 8 represented is the CNU structure charts of 4 inputs, and it is made up of a plurality of registers and 72 input CNU.Fig. 9 is the structure chart of 8 input CNU, is made up of 24 CNU that import and 92 input CNU.

In fact can on the basis of minimum unit 2 input CNU, construct the CNU of even number input, when the number of degrees of reality are odd number, choose CNU than an even number numerical value input of this odd number big 1, it is that (as the information employing is that 6 bit signed numbers are represented to the maximum that symbol is arranged that a few input is composed, then this numerical value is 31), the CNU of any number of degrees can be constructed by the method for this stratification, thereby the code check node processing unit of any quasi-cyclic code can be obtained.

The information that the selected cell selection deposits the interactive information memory cell in is from variable node processing unit or code check node processing unit.

Output unit is finished the buffering output of decoder, when decoder reaches maximum iteration time, control unit produces output unit and enables to bring in control input decoding bit, what output unit adopted is the buffer that register is formed, the value of information that will obtain in the variable node processing unit and being up to of channel value information addition result deposit in the output unit, decipher bit by the serial output that is used for of register buffer.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (9)

1. one kind is applicable to the quasi-cyclic LDPC decoders for decoding, it is characterized in that, comprising:

Control unit: produce control signal according to the control signal of input and status signal, coordinate the iterative decoding process of decoder at other functional units in the decoder;

Address-generation unit: the read/write address and corresponding read-write enable signal and the chip selection signal that are used for producing channel value memory cell and interactive information memory cell;

Channel value memory cell: be used to store the M bit quantization channel information value of separating after the mapping, if the columns of the basic matrix of quasi-cyclic code correspondence is NCOL, spreading factor is Z, then Dui Ying channel value memory cell is made up of NCOL group single port RAM, the size of every group of single port RAM is Z * M bit, according to the application size of one-port memory reality, every group of single port RAM size that may need is bigger slightly than Z * M;

Interactive information memory cell: be used for the information that storage of variables node processing unit and code check node processing unit transmit, if the number of non-null value is W in the quasi-cyclic code basic matrix, then Dui Ying interactive information memory cell is made up of W group two-port RAM, the size of every group of two-port RAM is Z * M bit, needs here according to the big or small needs of actual storage the physical storage size to be enlarged a little;

Matrix value memory cell: the numerical values recited that is used for storing the basic matrix non-null value;

Variable node processing unit: handle (VNU) by NCOL parallel variable node and form, finish the processing of variable node;

The code check node processing unit: if the line number of basic matrix is NROW, then the check-node unit is made up of NROW code check node processing (CNU) unit, finishes the processing of check-node;

Selected cell: the information that selection deposits the interactive information memory cell in is from variable node processing unit or code check node processing unit;

Output unit: the output decoding unit of decoder.

2. the quasi-cyclic LDPC decoders for decoding that is applicable to according to claim 1, it is characterized in that, described control unit is the finite state machine of one 9 state, comprises: idle condition, channel value store status, VNU for the first time computing mode, VNU for the first time to CNU transition state, CNU computing mode, VNU computing mode, VNU to CNU transition state, CNU to VNU transition state and output decoding state.

3. the quasi-cyclic LDPC decoders for decoding that is applicable to according to claim 1, it is characterized in that, described address-generation unit produces the read/write address of channel information memory cell and interactive information memory cell and read-write enables and chip selection signal, wherein the read/write address of interactive information memory cell adopts the method that writes back with the location, obtain information from the interactive information memory cell, with the information via CNU that obtains with write back to address identical when reading after VNU calculates.

4. the quasi-cyclic LDPC decoders for decoding that is applicable to according to claim 1, it is characterized in that, described channel information memory cell just begins to deposit in effective channel information value after detecting code word and beginning, the principle of storage is one group by spreading factor and is deposited among the corresponding single port RAM, after the channel information value of a code word has been deposited, just begin iterative decoding process, in the decoding iterative process only when variable node is handled ability from value wherein.

5. the quasi-cyclic LDPC decoders for decoding that is applicable to according to claim 1, it is characterized in that, described interactive information memory cell need be carried out initialized operation to the interactive information memory when initial CNU calculates, read the value of information and adopt the method that writes back with the location to write back in the interactive information memory through VNU or CNU calculating back in the interative computation process from the interactive information memory.

6. the quasi-cyclic LDPC decoders for decoding that is applicable to according to claim 1 is characterized in that described matrix value memory cell is used for storing the non-null value numerical values recited of basic matrix, produces the initial address that reads the interactive information memory when CNU calculates.

7. the quasi-cyclic LDPC decoders for decoding that is applicable to according to claim 1, it is characterized in that, described variable node processing unit is made up of NCOL parallel VNU, and VNU has adopted adder tree corresponding with the variable node annexation and bit wide to adjust the circuit composition.

8. the quasi-cyclic LDPC decoders for decoding that is applicable to according to claim 7 is characterized in that the computing that described variable node is finished is expressed as follows:

Variable node handle to calculate the information that passes to check-node j from variable node i, by as shown in the formula calculating

$L\left(q_{\mathrm{ij}}\right)=p_i+\underset{j^{\′}\∈C_i\backslash j}{\mathrm{\Σ}}L\left(r_{j^{\′}i}\right)$

C wherein _iJ the set representing to link to each other except other check-nodes of check-node j with variable node i; Simultaneously decoder is made a hard decision to variable node i herein, by as shown in the formula calculating:

$L\left(Q_i\right)=p_i+\underset{j\∈C_i}{\mathrm{\Σ}}L\left(r_{\mathrm{ji}}\right)$

If

Otherwise

When reaching maximum iteration time, then finish computing, otherwise continue interative computation.

9. the quasi-cyclic LDPC decoders for decoding that is applicable to according to claim 1 is characterized in that, described code check node processing unit is made up of NROW parallel CNU, and CNU has adopted the hierarchical structure of band biasing minterm algorithm, and this method comprises:

$L\left(r_{\mathrm{ji}}\right)=\underset{i^{\′}\∈V_j\backslash i}{\mathrm{\Π}}\mathrm{sign}\left[L\left(q_{i^{\′}j}\right)\right]\·\max \left\{\right[\underset{i^{\′}\∈V_j\backslash i}{\min }\left(\right|L\left(q_{i^{\′}j}\right)\left|\right)-\mathrm{\β}],0\}$

V wherein _jI the set representing to link to each other except other check-nodes of variable node i with check-node j, β represents bias; Here, its expression formula is deformed into the expression formula that can adopt the stratification hardware designs, as follows:

$L(x\⊕y)=\mathrm{sign}\left(\mathrm{xy}\right)\min \left\{\right|x|,|y\left|\right\}+\mathrm{\β}$

Wherein x and y represent two numerical value of input validation node processing unit, and adopting bit wide is the signed number of 6 bits, and the big I of β obtains according to emulation, obtain ± the 3rd, performance best choice during bit wide 6 bits;

Stratification expansion relatively can obtain the CNU of the even number input of any number of degrees based on this two values, if the check-node number of degrees are odd number, then the greatest measure of representing with 6 bits 31 is configured to the CNU of the input of even number as an input.

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