CN103151078B - A kind of storer error-detection error-correction code generating method - Google Patents

Abstract

The invention discloses a kind of generation method of the error detection and correction code for storer reinforcing.The method comprises: estimate check bit number according to raw data bit wide and required error correction and detection ability; Initiation verification matrix; From syndrome to be tested vector pond, search meets the syndrome vector that Line independent requires and inserts check matrix one by one; Record and search the complete check matrix produced at every turn, and change the reference position of vector search, re-start search until the reference position limit of search whole syndrome vector pond; If do not obtain complete check matrix, then increase check bit number, and repeated execution of steps 2 to 4; If there is multiple complete check matrix, then the check matrix that therefrom selection one is optimum is as error detection and correction code.Adopting method proposed by the invention greatly can accelerate various storer and reinforce the formation speed of encoding, just can obtain more excellent result without the need to studying various encryption algorithm again.

Description

A kind of storer error-detection error-correction code generating method

Technical field

The present invention relates to storer and reinforce coding field, particularly a kind of storer error-detection error-correction code generating method.

Background technology

Error detection and correction code (Error Detection and Correction, EDAC) is a kind of conventional means that storer is reinforced.Existing Multi-encoding mode is used for different application demands at present, and as Hamming code (Hamming Code), code (Hsiao Code) is thought in sea, Reed Solomon code (Reed-SolomonCode) etc.Although various coded system algorithm is different, fundamental mode when reinforcing for storer is the same.As shown in Figure 1, in order to realize the function of error correction and detection, storer needs the storage space increasing some outside raw data to be used for depositing check bit.Represent the bit wide of raw information with alphabetical k, alphabetical n represents the bit wide after adding check bit, and corresponding coding is also referred to as (n, k) code.Obviously, there is the raw information of k position in the code word of n position, the check bit of (n-k) position redundancy.When carrying out write operation, to need raw information by coding circuit to generate check digit, and together stored in storer; And when carrying out read operation, by the data of raw information again by coding circuit, the check digit data of its result and reading are carried out XOR and are obtained syndrome, then carry out error correction and detection operation according to syndrome to data.Wherein it should be noted that the check bit that generates of coding circuit and raw information together store, therefore decoding circuit is not only wanted to entangle the mistake in inspection raw information, also wants to entangle the mistake in inspection check bit.

The storer adopted in current sorts of systems is of a great variety, and application surface is extensive, and different storeies has different applied environments and mode of operation, also different to the demand of error detection and correction code.Existing various coded system often function is fixed, and as Hamming code and Hai Si code can only carry out the function of " SECDED ", common parity check code can only realize the function detecting odd bits mistake, although and RS code can correcting multiposition error, cost is larger.The error correction and detection ability realizing different ability just needs to be grasped the Computing Principle of different coding, and this brings more challenges for reservoir designs.And, often can only obtain a kind of decoding matrix with fixing algorithm, further cannot optimize it.

Summary of the invention

(1) technical matters that will solve

For this reason, the present invention proposes to customize a kind of suitable check matrix in light of the circumstances, the method of encoding and customizing reinforced by the storer realized difference requires, realizes by the method for syndrome vector search the target completing specific reinforcing with minimum redundance, area and latency penalty.

(2) technical scheme

For realizing above-mentioned target, the invention provides a kind of generation method of the error detection and correction code for storer reinforcing, comprising:

Step 1, estimate check bit number according to raw data bit wide and required error correction and detection ability;

Step 2, initiation verification matrix;

Step 3, from syndrome to be tested vector pond, search meets the syndrome vector that Line independent requires and inserts check matrix one by one;

The complete check matrix produced searched in step 4, record at every turn, and change the reference position that vector searches, and re-start search until the vectorial pond of the whole syndrome of reference position limit of search;

If step 5 does not obtain complete check matrix, then increase check bit number, and repeated execution of steps 2 to 4;

If step 6 has multiple complete check matrix, then the check matrix that therefrom selection one is optimum is as error detection and correction code.

(3) beneficial effect

The invention provides a kind of general mode and reinforce coding to generate the different storer of various requirement, by estimating check bit number, adopt the whole check matrix of unit matrix initialization, then traversal is searched whole vector space and is filled check matrix.Obtain various different check matrix by the mode of conversion vector traversal, and therefrom select most the superior.Adopting method proposed by the invention greatly can accelerate the formation speed of various storer error detection and correction code, just can obtain more excellent result without the need to studying various encryption algorithm again.

Accompanying drawing explanation

Fig. 1 is the theory diagram adopting error detection and correction code to reinforce storer in the present invention;

Fig. 2 is the process flow diagram of storer error-detection error-correction code generating method in the present invention.

Embodiment

For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with instantiation, the present invention is described in further detail.

Fig. 1 shows the theory diagram that the present invention adopts error detection and correction code to reinforce storer.As shown in Figure 1, adopt error detection and correction code to carry out reinforcing to storer to need to realize coding module, syndrome computations module and error correction and detection module.Described coding module, when write operation, for calculating corresponding check bit when raw data input store and together stored in storer, when read operation, calculating check results equally to raw data.Described syndrome computations module, when read operation, carries out xor operation for the check results calculated by coding module and the check bit stored, and obtains syndrome.The syndrome that described error correction and detection module is used for obtaining according to described syndrome computations module carries out error correcting and detecting to memory data.

In the present invention, described coding module realizes the coding to raw data by the function realizing a check matrix.Principle and the generative process of this check matrix will be introduced in detail below.

The original data vector of definition k position is the data after the codeword vector of D, n position and encoded module add check bit is C.The generator matrix G that can be k × n by a size transfers vectorial D to vectorial C.Generator matrix G can be divided into two parts: I _kwith P.Wherein I _kfor the unit matrix of k bit wide, P is the encoder matrix of k × (n-k), is used for obtaining according to the raw data of k position the check bit of (n-k) position accordingly.Visible, the function that what described coding module realized is exactly representated by encoder matrix P.Should be noted because the data in storer are all binary data, therefore matrix used here is also all the matrix in binary field, its addition be equal to xor operation in bit manipulation (for the addition in binary field, 0+0=0,1+0=1,1+1=0).

Illustrate for the Hamming code carrying out SEC single error correction for 8 bit data, it is as follows to add matrix P:

$P=\left[\begin{array}{cccc}1& 1& 0& 0\\ 1& 0& 1& 1\\ 1& 0& 1& 0\\ 1& 0& 0& 1\\ 0& 1& 1& 1\\ 0& 1& 1& 0\\ 0& 1& 0& 1\\ 0& 0& 1& 1\end{array}\right]$

The addition in realization matrix can be carried out as described above with XOR, therefore this matrix is converted into and adopts the check bit of XOR to generate formula.If the low portion in code word C is raw data, i.e. C ₇~ C ₀equal D ₇~ D ₀; High-order portion C ₁₁~ C ₈for redundancy check bit, it generates the following (symbol of formula represent XOR):

$C_{11}=D_7\⊕D_6\⊕D_5\⊕D_4$

$C_{10}=D_7\⊕D_3\⊕D_2\⊕D_1$

$C_9=D_6\⊕D_5\⊕D_3\⊕D_2\⊕D_0$

$C_8=D_6\⊕D_4\⊕D_3\⊕D_1\⊕D_0$

And also can represent syndrome computations process by a check matrix H accordingly, H=[I _n-kp] ^t, I _n-kfor the unit matrix of n-k bit wide, H is n × k matrix.Usually can adopt check matrix H to represent a coding, its advantage is: surprisingly overturn if there are data, the row vector of the correspondence in matrix H of error bit just of syndrome display.Wherein unit matrix I _n-krepresentative be the initialized syndrome vector of checking information when makeing mistakes, matrix P represents the syndrome vector to be filled when original data portion is made mistakes.As raw data lowest order C ₀overturn, then syndrome computations result is just shown as the syndrome vector " 0011 " of minimum a line in matrix P.If there is long numeric data to meet accident upset, the syndrome obtained is the result of the syndrome vector XOR of each error bit, as minimum two C ₀and C ₁meet accident upset, and the syndrome obtained is " 0110 ".Error correction and detection module carries out error-detection error-correction according to syndrome to data, if syndrome is complete " 0 ", representative data is error-free, the data of raw information part is directly exported; If syndrome is not complete " 0 ", according to its concrete numerical value misjudgment type, carries out error correction or report an error.

Fig. 2 shows error detection and correction code in the present invention and generates method flow diagram.The present invention, from check matrix angle, by searching the method composition check matrix of syndrome vector, and obtains corresponding error detection and correction code with this.As shown in Figure 2, the error-detection error-correction code generating method for storer reinforcing that the present invention proposes comprises:

Step 1, the different syndrome vector needed for the actual bit wide of raw data and error correction and detection capacity calculation, and estimate required check bit number with this.

If the demand of error correction aspect, each different mistake needs independent syndrome vector, for the storage data (comprising the raw data of k position and the check digit data of n-k position) of n position, single mistake of total n kind, it is two wrong that n × (n-1) plants.The object that therefore will realize SEC single error correction needs the different syndrome vector of n kind, then needs n+n × (n-1) plant different syndrome vectors as wanted double-error-correction.If the demand of error detection aspect, different mistakes can share a syndrome vector, as long as different with the syndrome for error correction.As long as the minimum syndrome vector of the mistake of a type in theory.As carried out the reinforcing of " SECDED " to the storage data of n position, namely want to correct arbitrary single mistake, detect any two wrong, at least need n+1 kind syndrome vector.After obtaining required syndrome vector, ask the truth of a matter of 2 just can obtain the check bit number estimated to it.This estimates number may be less than minimum check bit number needed for reality, and especially when there being the demand of error detection, the situation that the method is estimated is too desirable, is not easy to realize in reality.Therefore successive ignition likely can be needed finally to determine the number of check digit.To the requirement of entangling two mistake arbitrarily for 8 bit data required in example, if check digit number is c, required syndrome vector comprises 8+c SEC code subvector and (8+c) × (7+c)/2 kind of double error correction subvector, need meet (8+c)+(8+c) × (7+c)/2 < 2 ^c, at least need the check bit of 7 as calculated.

In step 2, according to the check bit number estimated of step 1 gained, initiation verification matrix-vector.

First first initiation verification matrix H, namely insert the syndrome vector for check information, i.e. unit matrix I, and be sky for the syndrome vector that the encoder matrix P of raw data erroneous part represent, be in state to be filled in check matrix H.Check matrix after initialization is as follows.

For this example, because check bit is 7, check matrix size is 7 × 15, inserts the unit matrix of 7 bit wides during initialization, and remaining 8 column vectors need to fill.

In step 3, from syndrome to be tested vector pond, select vector one by one calculate, see the requirement whether meeting Line independent, if meet the part to be filled just inserting check matrix, with this back and forth until fill up whole check matrix.

Described syndrome to be tested vector pond is for comprising the c position binary vector of all non-fully " 0 ".The reason of removing complete " 0 " vector is that syndrome is that complete " 0 " representative data is error-free, cannot be used for representing other situations of makeing mistakes.The vector occurred in check matrix H also will take out from pond, and the vector therefore in unit matrix all will take out.

For binary vector, after Line independent is equal to each vector mutual position XOR, result is not complete " 0 " vector.According to order from small to large, the vector in syndrome vector pond is extracted one by one, and whether the vector that existed meets Line independent requirement in the vector that extracts of inspection institute and check matrix, the verified vector of vector sum in check matrix is no longer tested, and the vector wherein in check matrix comprises unit matrix vector sum and has been filled in vector in part to be filled.For different error correction and detection demands, the requirement of its Line independent is also different.Usually for entangling t dislocation, Line independent between any 2t vector is required.The SYSTEM OF LINEAR VECTOR demand for independence of several frequently seen error correction and detection demand is as shown in the table.

The different error correction and detection of table 1 requires the Line independent requirement of lower syndrome vector

Due to the singularity of vector in unit matrix, unit matrix itself meets any Line independent requirement.Therefore for syndrome to be tested vector, only need to check that the Line independent relating to this vector calculates, do not need to require to check to the Line independent before in check matrix between vector.Specifically for this example, from syndrome to be tested vector pond, { 0,0,0,0,0,1,1} starts to test minimum vector, need meet Line independent between any four vectors.By calculate can find vector in 0,0,0,0,0,1,1} and unit matrix { 0,0,0,0,0,0,1}, { 0,0,0,0,0,1,0} linear correlation does not meet the requirement of Line independent between any four vectors.Therefore can not insert check matrix, continue to choose vector from vectorial pond and test.Until detect that vector { just meets the requirements during 0,0,0,1,1,1,1}, therefore to insert in check matrix and to continue to search, terminate after filling up check matrix or searching complete vectorial pond.In this example, 4 satisfactory vectors can only be found after searching complete vectorial pond: { 0,0,0,1,1,1,1}, { 0,1,1,0,0,1,1}, { 1,0,1,0,1,0,1}, { 1,1,0,1,0,1,0} enough could not fill up check matrix.

In step 4, by again performing step 3, to obtain different search results after change search reference position.First effective vector that reference position searches before should being greater than, otherwise come to the same thing, insert the syndrome vector of check matrix for first when described first effective vector is previous search.In this example, if not from 0,0,0,0,0,1,1} but from 0,0,1,0,0,0,1} start search, the result obtained is { 0,0,1,0,1,1,1}, { 0,1,0,1,0,1,1}, { 1,0,0,1,1,0,1}, { 1,1,1,0,0,1,0}; If from { 0,1,0,0,0,0,1} starts search, and the result obtained is { 0,1,0,0,1,1,1}, { 0,1,1,1,0,0,1}, { 1,0,0,1,0,1,1}, { 1,0,1,0,1,1,0}.

In step 5, if change search reference position by step 4 do not obtain complete check matrix, just need increase by bit check position.Then step 2 is repeated to step 4.The minimum value that a just check bit tried to achieve in step 1 is estimated, can not ensure to realize final error-detection error-correction object.Check bit quantity is more, and the error-detection error-correction ability that can realize is stronger, but also therefore will increase the area of many redundancies.During design, under the prerequisite that assurance function realizes, always wish that the quantity of check bit is more few better.If just check bit number must be increased after still cannot finding qualified check matrix after therefore adjusting syndrome search reference position by step 4, but each also just increase by 1, although the calculated amount of iteration can be increased like this, can ensure to realize specific reinforcement criteria by minimum area cost.In this example, have 8 bit check positions after increasing by a bit check position, check matrix is also adjusted to 8 × 16.A qualified check matrix is obtained as follows after step 3.

$\left[\begin{array}{cccccccccccccccc}1& 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 0& 0& 1& 1& 1\\ 0& 1& 0& 0& 0& 0& 0& 0& 1& 1& 0& 1& 1& 1& 1& 0\\ 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 1& 0& 1& 0& 0& 1\\ 0& 0& 0& 1& 0& 0& 0& 0& 1& 0& 0& 1& 0& 1& 1& 1\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 1& 1& 0& 1& 0& 1& 0\\ 0& 0& 0& 0& 0& 1& 0& 0& 0& 1& 0& 1& 0& 1& 0& 1\\ 0& 0& 0& 0& 0& 0& 1& 0& 0& 0& 1& 1& 0& 0& 1& 1\\ 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 1& 1& 1& 1\end{array}\right]$

After step 4, reference position is searched in adjustment again, can obtain other same satisfactory results as follows.

$\left[\begin{array}{cccccccccccccccc}1& 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 0& 0& 0& 0& 1\\ 0& 1& 0& 0& 0& 0& 0& 0& 1& 1& 0& 1& 1& 0& 0& 0\\ 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 1& 0& 1& 1& 0& 0\\ 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 1& 0& 1& 0& 1& 0\\ 0& 0& 0& 0& 1& 0& 0& 0& 1& 0& 0& 1& 0& 1& 1& 0\\ 0& 0& 0& 0& 0& 1& 0& 0& 0& 1& 0& 1& 0& 1& 0& 1\\ 0& 0& 0& 0& 0& 0& 1& 0& 0& 0& 1& 1& 0& 0& 1& 1\\ 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 1& 1& 1& 1\end{array}\right]$

Can find that above-mentioned two check matrixes can realize the function of expecting through inspection.Need further to compare to determine net result to both.

In step 6, the difference of error detection and correction code on hardware implementing representated by each check matrix is screened, and obtains optimum result.

The number of " 1 " in check matrix represents XOR gate quantity required when realizing this matrix.If the number of " 1 " in check matrix is fewer, just mean less hardware spending.Meanwhile, the row vector that in check matrix, the number of " 1 " is maximum represents the critical path in coding-decoding circuit when realizing this matrix.If the XOR gate negligible amounts in critical path, just can have less time delay, also just mean better performance.

For two of above-mentioned raising check matrixes.For first matrix, often row has at most 7 " 1 ", and the critical path meaning decoding circuit needs execution 6 XORs, i.e. S ₇and S ₆the calculating of two syndromes.Have in whole matrix 45 " 1 ", mean in decoding circuit and need 37 XOR gate altogether.

And for second check matrix, the number of " 1 " in this matrix is 40, be less than the first decoding matrix, this illustrates that the number of XOR gate required is in coding and in decoding less, decreases area overhead; Often row only has 5 " 1 ", can see that each syndrome only needs 4 XORs from formula, is less than 6 XORs of the first decoding matrix, also namely means to adopt the second decoding matrix can realize higher arithmetic speed under same process conditions.Therefore select second check matrix as net result.

Definition information position is D ₇~ D ₀, check bit is C ₇~ C ₀, syndrome is S ₇~ S ₀.Check code computing formula can be obtained according to terminal check matrix:

$C_7=D_7\&CirclePlus;D_6\&CirclePlus;D_5\&CirclePlus;D_0$

$C_6=D_7\&CirclePlus;D_6\&CirclePlus;D_4\&CirclePlus;D_3$

$C_5=D_7\&CirclePlus;D_5\&CirclePlus;D_3\&CirclePlus;D_2$

$C_4=D_6\&CirclePlus;D_5\&CirclePlus;D_3\&CirclePlus;D_1$

$C_3=D_7\&CirclePlus;D_4\&CirclePlus;D_2\&CirclePlus;D_1$

$C_2=D_6\&CirclePlus;D_4\&CirclePlus;D_2\&CirclePlus;D_0$

$C_1=D_5\&CirclePlus;D_4\&CirclePlus;D_1\&CirclePlus;D_0$

$C_0=D_3\&CirclePlus;D_2\&CirclePlus;D_1\&CirclePlus;D_0$

The generation formula of syndrome is:

$S_7=C_7\&CirclePlus;D_7\&CirclePlus;D_6\&CirclePlus;D_5\&CirclePlus;D_0$

$S_6=C_6\&CirclePlus;D_7\&CirclePlus;D_6\&CirclePlus;D_4\&CirclePlus;D_3$

$S_5=C_5\&CirclePlus;D_7\&CirclePlus;D_5\&CirclePlus;D_3\&CirclePlus;D_2$

$S_4=C_4\&CirclePlus;D_6\&CirclePlus;D_5\&CirclePlus;D_3\&CirclePlus;D_1$

$S_3=C_3\&CirclePlus;D_7\&CirclePlus;D_4\&CirclePlus;D_2\&CirclePlus;D_1$

$S_2=C_2\&CirclePlus;D_6\&CirclePlus;D_4\&CirclePlus;D_2\&CirclePlus;D_0$

$S_1=C_1\&CirclePlus;D_5\&CirclePlus;D_4\&CirclePlus;D_1\&CirclePlus;D_0$

$S_0=C_0\&CirclePlus;D_3\&CirclePlus;D_2\&CirclePlus;D_1\&CirclePlus;D_0$

In sum, the present invention has following technical characteristic: (1) adopts the mode of error detection and correction code to reinforce storer.(2) calculate required syndrome vector according to actual error-detection error-correction demand and data bit width, and with this, check bit number is estimated.(3) adopt unit matrix initiation verification matrix, and find other vector in check matrix by the mode of the whole syndrome vector space of search.(4) to obtain in check matrix the required Line independent relation met between each vector according to error-detection error-correction demand, and as standard, syndrome vector is screened.(5) reference position by changing syndrome space carries out repeatedly the filling of check matrix, to obtain different check matrixes.(6) the logic gate quantity needed for realizing circuit and critical path depth are screened wherein, to obtain more excellent result.Each step of method provided by the present invention all can realize automatic computing by the mode of software programming, is conducive to reducing design basis ground motion difficulty.

Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1., for a generation method for the error detection and correction code of storer reinforcing, comprising:

Step 1, estimate check bit number according to raw data bit wide and required error correction and detection ability;

Step 2, initiation verification matrix;

Step 3, from syndrome to be tested vector pond, search meets the syndrome vector that Line independent requires and inserts check matrix one by one;

The complete check matrix produced searched in step 4, record at every turn, and change the reference position that vector searches, and re-start search until the vectorial pond of the whole syndrome of reference position limit of search;

If step 5 does not obtain complete check matrix, then increase check bit number, and repeated execution of steps 2 to 4;

If step 6 has multiple complete check matrix, then the check matrix that therefrom selection one is optimum is as error detection and correction code.

2. the method for claim 1, it is characterized in that, described check matrix is made up of the encoder matrix of n-k unit matrix and k × (n-k), and wherein k is raw data bit wide, n is coded data bit wide, and described coded data comprises raw data and check bit.

3. method as claimed in claim 2, it is characterized in that, when write operation, utilize described encoder matrix to carry out coding to raw data and generate and store check bit, when read operation, utilize described encoder matrix to encode to raw data, and the result obtained and the check bit that stores are carried out XOR obtain syndrome, then according to syndrome, error correction and detection operation is carried out to data.

4. the method for claim 1, is characterized in that, described syndrome to be tested vector pond for comprising all binary vectors of non-full 0, and does not wherein comprise vector of unit length, and its bit wide is check bit number.

5. the method for claim 1, is characterized in that, for binary vector, Line independent refers to that between each vector, after mutual XOR, result is not 0.

6. method as claimed in claim 2, it is characterized in that, the matrix of initiation verification described in step 2 is initialization unit matrix wherein, and described encoder matrix is set to part to be filled.

7. method as claimed in claim 6, it is characterized in that, step 3 is specially extracts syndrome vector one by one from syndrome vector pond, and the linear independent between the vector calculating respective numbers in the syndrome vector and check matrix extracted, and be filled into check matrix part to be filled by having the syndrome vector that Line independent requires between the vector of respective numbers in check matrix.

8. the method for claim 1, is characterized in that, in step 4, the search reference position after change is greater than previous first of searching effectively vector, inserts the syndrome vector of check matrix for first when described first effective vector is previous search.

9. the method for claim 1, is characterized in that, selects optimum check matrix in step 6 according to the difference on hardware implementing.

10. method as claimed in claim 7, it is characterized in that, described respective numbers is determined according to error correcting and detecting ability.