CN108170556A - Error correcting code generates and the guard method of check matrix and matrix storage/generation device - Google Patents
Error correcting code generates and the guard method of check matrix and matrix storage/generation device Download PDFInfo
- Publication number
- CN108170556A CN108170556A CN201810049056.4A CN201810049056A CN108170556A CN 108170556 A CN108170556 A CN 108170556A CN 201810049056 A CN201810049056 A CN 201810049056A CN 108170556 A CN108170556 A CN 108170556A
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- China
- Prior art keywords
- matrix
- correcting code
- error correcting
- check
- check bit
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/102—Error in check bits
Abstract
The invention discloses a kind of generations of error correcting code and the guard method of check matrix, are generated and the check bit that adds entry during storage in generator matrix and check matrix.Make its not by or reduce mistake interference to maintain error-correcting code system normal operation.The invention also discloses a kind of error correcting code matrix storage/generation devices, and corresponding matrix entries check bit is stored or generate while storing or generating matrix entries.
Description
Technical field
The present invention relates to the generator matrix of error correcting code check bit and the protection fields of check matrix.
Background technology
For the generator matrix and check matrix of the error correcting code check bit of data memory device system, if information is transmitted
Its correctness is caused to be unable to maintain that by the memory element mistake of mistake interference or storage, error-correcting code system must be caused normal
Running.If generator matrix entry errors, the code word check bit generated can be caused incorrect.If check matrix entry generates wrong
Accidentally, even if code word check bit generates correctly, verification can not be also correctly completed, even correct codeword information is verified into mistake
Information.Therefore maintain the entry information correctness of generator matrix and check matrix of crucial importance.
Invention content
One of the objects of the present invention is to provide error correcting code generation and the guard method of check matrix, make its not by or reduce
Mistake is interfered to maintain error-correcting code system normal operation.
The second object of the present invention is to provide error correcting code matrix storage/generation device, in storage or generation matrix entries
While store or generate corresponding matrix entries check bit.
Realizing the technical solution of above-mentioned purpose is：
The error correcting code generation of one of the present invention and the guard method of check matrix are generated and are stored in generator matrix and check matrix
Shi Jun adds entry check bit.
Preferably, the mode for adding in check bit is：The mode of verification or Hamming code is recycled based on check bit, to each matrix
Entry adds in corresponding entry check bit.
Preferably, when mistake occurs for generator matrix in coding and decoding core operational process and check matrix, coding and decoding core according to
Matrix entries coordinate the verification operation of its entry check bit, carry out wrong detection and error correction.
According to above-mentioned technical proposal, the present invention is used by the check bit that additionally adds entry when matrix is generated with storing
To protect generator matrix and check matrix, its information correctness is maintained.Its correct running is enable to ensure the school of error-correcting code system
It tests position generation flow correctly to be run with checking process, to lower or it is made not interfered by mistake, maintains error-correcting code system work(
Correctness that can normally with effect result.
Error correcting code matrix storage/generation device of the two of the present invention, store or generate matrix entries when, while store or
Generate corresponding matrix entries check bit.
Preferably, the error correcting code matrix storage/generation device output matrix entry to error correcting code operation when export square simultaneously
Battle array entry check bit.
According to above-mentioned technical proposal, the present invention provides error correcting code matrix storage/generation device, is storing or generating matrix item
Purpose stores or generates simultaneously corresponding matrix entries check bit, error correcting code is caused to be compiled with mistake occurs to avoid matrix entries
Relevant error derived from code/decoding.
Description of the drawings
Fig. 1 is normal encoding/decoded state figure when verifying function protection is not configured；
Coding/decoding state diagram when Fig. 2 is generator matrix entry errors；
Coding/decoding state diagram when Fig. 3 is check matrix entry errors；
Normal encoding/decoded state figure when Fig. 4 is configuration verifying function protection；
Coding/decoding state diagram when Fig. 5 is generator matrix and check matrix entry errors；
Fig. 6 is the output state figure of error correcting code matrix storage/generation device.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings.
Error correcting code generation and the guard method of check matrix of one of the present invention, for current art for generator matrix with
Check matrix has no the defects of being protected using check bit and other modes, and verification or Hamming code are recycled using based on check bit
Mode, generated in generator matrix and check matrix with adding in the entry check bit corresponding to each matrix entries during storage.
When causing generator matrix and check matrix that mistake occurs because of unknown cause in coding and decoding core operational process, coding and decoding core is according to square
Battle array entry coordinates the verification operation of its entry check bit, carries out wrong detection and error correction.Its correct running is enable to ensure
The check bit of error-correcting code system generates flow and is correctly run with checking process, to lower or it made not interfered by mistake, dimension
Hold correctness of the error-correcting code system function normally with effect result.
As shown in Figure 1, for commonly without the matrix entries of configuration verifying function protection.
As shown in Fig. 2, generator matrix entry errors lead to the code word verification bit-errors that error correcting code generates, so as to cause verification
The data gone out follows mistake.
As shown in figure 3, check matrix entry errors, even if after generating correct code word check bit, check matrix entry is wrong
Mistake but causes to verify the data to make mistake instead.
As shown in figure 4, there are the matrix entries of configuration verifying function protection, even if if attached drawing 5 is in generator matrix and verification square
When mistake occurs for battle array entry, it can correct in time, avoid relevant error derived from error correcting code coding/decoding.
Error correcting code matrix storage/generation device of the two of the present invention, store or generate matrix entries when, while store or
Corresponding matrix entries check bit is generated, when the error correcting code matrix storage/generation device output matrix entry is to error correcting code operation
Output matrix entry check bit simultaneously leads to correlation derived from error correcting code coding/decoding with mistake occurs to avoid matrix entries
Mistake.As shown in fig. 6, error correcting code matrix storage/generation device while output matrix entry and matrix entries check bit so that compile
It avoids leading to relevant error derived from error correcting code coding because mistake occurs for matrix entries during code.
Above example is used for illustrative purposes only rather than limitation of the present invention, the technology people in relation to technical field
Member, without departing from the spirit and scope of the present invention, can also make various transformation or modification, therefore all equivalent
Technical solution should also belong to scope of the invention, should be limited by each claim.
Claims (5)
1. a kind of error correcting code generation and the guard method of check matrix, which is characterized in that generated in generator matrix and check matrix
With the check bit that adds entry during storage.
2. error correcting code generation according to claim 1 and the guard method of check matrix, which is characterized in that add in check bit
Mode be：The mode of verification or Hamming code is recycled based on check bit, corresponding entry check bit is added in each matrix entries.
3. error correcting code generation according to claim 2 and the guard method of check matrix, which is characterized in that when coding and decoding core
When mistake occurs for generator matrix and check matrix in operational process, coding and decoding core coordinates its entry check bit according to matrix entries
Operation is verified, carries out wrong detection and error correction.
4. a kind of error correcting code matrix storage/generation device, which is characterized in that when storing or generating matrix entries, store simultaneously
Or generate corresponding matrix entries check bit.
5. error correcting code matrix storage/generation device according to claim 4, which is characterized in that error correcting code matrix storage/
When generation device output matrix entry is to error correcting code operation simultaneously output matrix entry check bit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810049056.4A CN108170556A (en) | 2018-01-18 | 2018-01-18 | Error correcting code generates and the guard method of check matrix and matrix storage/generation device |
| PCT/CN2018/099737 WO2019140888A1 (en) | 2018-01-18 | 2018-08-09 | Protection method for error correcting code generator and check matrixes, and matrix storage/generation device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810049056.4A CN108170556A (en) | 2018-01-18 | 2018-01-18 | Error correcting code generates and the guard method of check matrix and matrix storage/generation device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108170556A true CN108170556A (en) | 2018-06-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810049056.4A Pending CN108170556A (en) | 2018-01-18 | 2018-01-18 | Error correcting code generates and the guard method of check matrix and matrix storage/generation device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108170556A (en) |
| WO (1) | WO2019140888A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019140888A1 (en) * | 2018-01-18 | 2019-07-25 | 江苏华存电子科技有限公司 | Protection method for error correcting code generator and check matrixes, and matrix storage/generation device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0989492A2 (en) * | 1998-09-24 | 2000-03-29 | Sun Microsystems, Inc. | Technique for correcting single-bit errors in caches with sub-block parity bits |
| CN101114834A (en) * | 2007-07-31 | 2008-01-30 | 北京航空航天大学 | Encoder device and encoding method for LDPC code |
| CN102088294A (en) * | 2010-09-29 | 2011-06-08 | 西安空间无线电技术研究所 | QC-LDPC (quasi-cyclic low-density parity-check codes) coder and coding method |
| CN103151078A (en) * | 2013-03-19 | 2013-06-12 | 中国科学院微电子研究所 | Memorizer Error detection and correction code generation method |
| CN103873069A (en) * | 2012-12-08 | 2014-06-18 | Lsi公司 | Low Density Parity Check Decoder With Miscorrection Handling |
| US20170255520A1 (en) * | 2016-03-02 | 2017-09-07 | Electronics And Telecommunications Research Institute | Cache memory device and operating method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101340192B (en) * | 2008-08-07 | 2010-09-01 | 北京创毅视讯科技有限公司 | Encoding method and apparatus for low density parity-check code |
| JP5509165B2 (en) * | 2011-08-24 | 2014-06-04 | 株式会社東芝 | Error correction coding apparatus, error correction decoding apparatus, nonvolatile semiconductor memory system, and parity check matrix generation method |
| CN108170556A (en) * | 2018-01-18 | 2018-06-15 | 江苏华存电子科技有限公司 | Error correcting code generates and the guard method of check matrix and matrix storage/generation device |
-
2018
- 2018-01-18 CN CN201810049056.4A patent/CN108170556A/en active Pending
- 2018-08-09 WO PCT/CN2018/099737 patent/WO2019140888A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0989492A2 (en) * | 1998-09-24 | 2000-03-29 | Sun Microsystems, Inc. | Technique for correcting single-bit errors in caches with sub-block parity bits |
| CN101114834A (en) * | 2007-07-31 | 2008-01-30 | 北京航空航天大学 | Encoder device and encoding method for LDPC code |
| CN102088294A (en) * | 2010-09-29 | 2011-06-08 | 西安空间无线电技术研究所 | QC-LDPC (quasi-cyclic low-density parity-check codes) coder and coding method |
| CN103873069A (en) * | 2012-12-08 | 2014-06-18 | Lsi公司 | Low Density Parity Check Decoder With Miscorrection Handling |
| CN103151078A (en) * | 2013-03-19 | 2013-06-12 | 中国科学院微电子研究所 | Memorizer Error detection and correction code generation method |
| US20170255520A1 (en) * | 2016-03-02 | 2017-09-07 | Electronics And Telecommunications Research Institute | Cache memory device and operating method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019140888A1 (en) * | 2018-01-18 | 2019-07-25 | 江苏华存电子科技有限公司 | Protection method for error correcting code generator and check matrixes, and matrix storage/generation device |
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| Publication number | Publication date |
|---|---|
| WO2019140888A1 (en) | 2019-07-25 |
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Application publication date: 20180615 |
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