WO2019140888A1 - Protection method for error correcting code generator and check matrixes, and matrix storage/generation device - Google Patents

Protection method for error correcting code generator and check matrixes, and matrix storage/generation device Download PDF

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WO2019140888A1
WO2019140888A1 PCT/CN2018/099737 CN2018099737W WO2019140888A1 WO 2019140888 A1 WO2019140888 A1 WO 2019140888A1 CN 2018099737 W CN2018099737 W CN 2018099737W WO 2019140888 A1 WO2019140888 A1 WO 2019140888A1
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matrix
check
entry
error correction
correction code
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PCT/CN2018/099737
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French (fr)
Chinese (zh)
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陈育鸣
李庭育
洪振洲
魏智汎
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江苏华存电子科技有限公司
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Publication of WO2019140888A1 publication Critical patent/WO2019140888A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/102—Error in check bits

Definitions

  • the present invention relates to the field of protection of the generation matrix and check matrix of error correction code check bits.
  • the generation matrix and check matrix of the error correction code check bits used in the data storage device system if the information transmission is incorrectly interfered or the stored storage element is incorrect, the correctness cannot be maintained, and the error correction code system cannot be normal. Operation. If the generator matrix entry is incorrect, the generated codeword check digit will be incorrect. If the check matrix entry generates an error, even if the codeword check digit is correctly generated, the verification cannot be completed correctly, or even the correct codeword information is verified as the wrong information. Therefore, it is extremely important to maintain the correctness of the entry information of the generator matrix and the check matrix.
  • One of the objects of the present invention is to provide a method for protecting an error correcting code generation and check matrix from or from erroneous interference to maintain the normal operation of the error correcting code system.
  • Another object of the present invention is to provide an error correction code matrix storage/generation apparatus that stores or generates a corresponding matrix entry check bit while storing or generating a matrix entry.
  • the error correction code generation and check matrix protection method of one of the present invention adds an entry check bit when generating and storing the generation matrix and the check matrix.
  • the check digit is added by adding a corresponding entry check digit to each matrix entry based on the manner of check bit cyclic check or Hamming code.
  • the codec core when an error occurs in the generation matrix and the check matrix during the operation of the codec core, the codec core performs error detection and error correction according to the matrix entry and the check operation of the entry check digit.
  • the present invention additionally adds an entry check bit in the generation and storage of the matrix to protect the generation matrix and the check matrix, and maintain the correctness of the information.
  • the correct operation of the error correction code system ensures that the check digit generation process and the verification process operate correctly to reduce or prevent it from being disturbed, and to maintain the correct function of the error correction code system and the correctness of the test results.
  • the error correcting code matrix storage/generating apparatus of the second aspect of the present invention simultaneously stores or generates a corresponding matrix entry check bit when storing or generating a matrix entry.
  • the error correction code matrix storage/generating device outputs a matrix entry to the matrix error check bit when the error correction code operation is performed.
  • the present invention provides an error correction code matrix storage/generating apparatus for storing or generating a matrix entry check bit while storing or generating a matrix entry, in order to avoid error of the matrix entry, resulting in error correction code encoding/decoding. Derived related errors.
  • Figure 1 is a diagram showing the normal encoding/decoding state when the check function protection is not configured
  • Figure 2 is a diagram of an encoding/decoding state when generating a matrix entry error
  • Figure 3 is a diagram of the encoding/decoding state when the check matrix entry is incorrect
  • FIG. 4 is a diagram of a normal encoding/decoding state when the configuration check function is protected
  • Figure 5 is a diagram of an encoding/decoding state when the generation matrix and the check matrix entry are incorrect;
  • Fig. 6 is a diagram showing an output state of an error correction code matrix storing/generating device.
  • the method for protecting error correction code generation and check matrix is directed to the defect that the generation matrix and the check matrix do not use check bits and other methods for protection, and the checksum loop check or Han is used.
  • the entry check bits corresponding to each matrix entry are added to both the generation matrix and the check matrix generation and storage.
  • the generation of the matrix entry error causes the codeword check bit generated by the error correction code to be erroneous, thereby causing the verified data to follow the error.
  • the check matrix entry is incorrect. Even if the correct codeword check digit is generated, the check matrix entry error will result in the incorrect data being verified.
  • FIG. 4 there is a matrix entry configured with the check function protection, even if an error occurs in the generation matrix and the check matrix entry as shown in FIG. 5, it can be corrected in time, and the error related to the error correction code encoding/decoding is avoided. .
  • the error correcting code matrix storage/generating apparatus of the second aspect of the present invention simultaneously stores or generates a corresponding matrix entry check bit when storing or generating a matrix entry, the error correcting code matrix storing/generating device output matrix entry to the error correcting code
  • the matrix entry check bits are simultaneously output during the operation to avoid errors associated with the error correction code encoding/decoding caused by errors in the matrix entries.
  • the error correction code matrix storage/generating means simultaneously outputs the matrix entries and the matrix entry check bits so that the associated errors caused by the error correction code encoding due to errors in the matrix entries are avoided during encoding.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Error Detection And Correction (AREA)
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Abstract

A protection method for error correcting code generator and check matrixes, and an error correcting code matrix storage/generation device. According to the method, entry check bits are added during both generation and storage of a generator matrix and a check matrix. According to the device, corresponding matrix entry check bits are stored or generated while matrix entries are stored or generated. Error interference is avoided or lowered to maintain the normal operation of an error correcting code system.

Description

纠错码生成与校验矩阵的保护方法及矩阵存储/产生装置Error correction code generation and check matrix protection method and matrix storage/generation device 技术领域Technical field
本发明涉及纠错码校验位的生成矩阵与校验矩阵的保护领域。The present invention relates to the field of protection of the generation matrix and check matrix of error correction code check bits.
背景技术Background technique
用于数据储存装置系统的纠错码校验位之生成矩阵与校验矩阵，其信息传递倘若受错误干扰或储存的存储元件错误而导致其正确性无法维持，必致使纠错码系统无法正常运作。若是生成矩阵条目错误，会导致产生的码字校验位不正确。若是校验矩阵条目产生错误，就算码字校验位产生正确，也无法正确完成校验，甚或将正确的码字信息校验成错误的信息。故维持生成矩阵与校验矩阵的条目信息正确性极其重要。The generation matrix and check matrix of the error correction code check bits used in the data storage device system, if the information transmission is incorrectly interfered or the stored storage element is incorrect, the correctness cannot be maintained, and the error correction code system cannot be normal. Operation. If the generator matrix entry is incorrect, the generated codeword check digit will be incorrect. If the check matrix entry generates an error, even if the codeword check digit is correctly generated, the verification cannot be completed correctly, or even the correct codeword information is verified as the wrong information. Therefore, it is extremely important to maintain the correctness of the entry information of the generator matrix and the check matrix.
发明内容Summary of the invention
本发明的目的之一在于提供纠错码生成与校验矩阵的保护方法，使其不受或降低错误干扰以维持纠错码系统正常运作。One of the objects of the present invention is to provide a method for protecting an error correcting code generation and check matrix from or from erroneous interference to maintain the normal operation of the error correcting code system.
本发明的目的之二在于提供纠错码矩阵存储/产生装置，在存储或产生矩阵条目的同时存储或产生对应的矩阵条目校验位。Another object of the present invention is to provide an error correction code matrix storage/generation apparatus that stores or generates a corresponding matrix entry check bit while storing or generating a matrix entry.
实现上述目的的技术方案是：The technical solution to achieve the above objectives is:
本发明之一的纠错码生成与校验矩阵的保护方法，在生成矩阵和校验矩阵产生与存储时均加入条目校验位。The error correction code generation and check matrix protection method of one of the present invention adds an entry check bit when generating and storing the generation matrix and the check matrix.
优选的，加入校验位的方式为：基于校验位循环核对或汉明码的方式，对每个矩阵条目加入对应的条目校验位。Preferably, the check digit is added by adding a corresponding entry check digit to each matrix entry based on the manner of check bit cyclic check or Hamming code.
优选的，当编译码核运行过程中生成矩阵和校验矩阵发生错误时，编译码核依照矩阵条目配合其条目校验位的校验运算，进行错误检出与错误校正。Preferably, when an error occurs in the generation matrix and the check matrix during the operation of the codec core, the codec core performs error detection and error correction according to the matrix entry and the check operation of the entry check digit.
根据上述技术方案，本发明通过在矩阵产生与储存时均额外加入条目校验位,用以保护生成矩阵与校验矩阵，维持其信息正确性。使其得以正确运作确保纠错码 系统之校验位产生流程与校验流程得以正确运行，以减低或使其不受错误干扰，维持纠错码系统功能正常与效验结果的正确性。According to the above technical solution, the present invention additionally adds an entry check bit in the generation and storage of the matrix to protect the generation matrix and the check matrix, and maintain the correctness of the information. The correct operation of the error correction code system ensures that the check digit generation process and the verification process operate correctly to reduce or prevent it from being disturbed, and to maintain the correct function of the error correction code system and the correctness of the test results.
本发明之二的纠错码矩阵存储/产生装置，在存储或产生矩阵条目时，同时存储或产生对应的矩阵条目校验位。The error correcting code matrix storage/generating apparatus of the second aspect of the present invention simultaneously stores or generates a corresponding matrix entry check bit when storing or generating a matrix entry.
优选的，该纠错码矩阵存储/产生装置输出矩阵条目给纠错码运算时同时输出矩阵条目校验位。Preferably, the error correction code matrix storage/generating device outputs a matrix entry to the matrix error check bit when the error correction code operation is performed.
根据上述技术方案，本发明提供纠错码矩阵存储/产生装置，在存储或产生矩阵条目的同时存储或产生对应的矩阵条目校验位，用以避免矩阵条目发生错误导致纠错码编码/解码衍生的相关错误。According to the above technical solution, the present invention provides an error correction code matrix storage/generating apparatus for storing or generating a matrix entry check bit while storing or generating a matrix entry, in order to avoid error of the matrix entry, resulting in error correction code encoding/decoding. Derived related errors.
附图说明DRAWINGS
图1是没有配置校验功能保护时正常编码/解码状态图；Figure 1 is a diagram showing the normal encoding/decoding state when the check function protection is not configured;
图2是生成矩阵条目错误时编码/解码状态图；Figure 2 is a diagram of an encoding/decoding state when generating a matrix entry error;
图3是校验矩阵条目错误时编码/解码状态图；Figure 3 is a diagram of the encoding/decoding state when the check matrix entry is incorrect;
图4是配置校验功能保护时正常编码/解码状态图；4 is a diagram of a normal encoding/decoding state when the configuration check function is protected;
图5是生成矩阵和校验矩阵条目错误时编码/解码状态图；Figure 5 is a diagram of an encoding/decoding state when the generation matrix and the check matrix entry are incorrect;
图6是纠错码矩阵存储/产生装置的输出状态图。Fig. 6 is a diagram showing an output state of an error correction code matrix storing/generating device.
具体实施方式Detailed ways
下面将结合附图对本发明作进一步说明。The invention will now be further described with reference to the accompanying drawings.
本发明之一的纠错码生成与校验矩阵的保护方法，针对现行技术对于生成矩阵与校验矩阵并无使用校验位及其他方式进行保护的缺陷，使用基于校验位循环核对或汉明码的方式，在生成矩阵和校验矩阵产生与存储时均加入对应于每个矩阵条目的条目校验位。当编译码核运行过程中因不明原因致使生成矩阵和校验矩阵发生错误时，编译码核依照矩阵条目配合其条目校验位的校验运算，进行错误检出与错误校正。使其得以正确运作确保纠错码系统之校验位产生流程与校验流程得以正确运行，以减低或使其不受错误干扰，维持纠错码系统功能正常与效验结果的正确性。The method for protecting error correction code generation and check matrix according to one aspect of the present invention is directed to the defect that the generation matrix and the check matrix do not use check bits and other methods for protection, and the checksum loop check or Han is used. In the clear way, the entry check bits corresponding to each matrix entry are added to both the generation matrix and the check matrix generation and storage. When an error occurs in the generator matrix and the check matrix due to unknown reasons during the running of the codec core, the codec core performs error detection and error correction according to the check operation of the matrix entry and its entry check digit. It is properly operated to ensure that the check digit generation process and verification process of the error correction code system are correctly operated to reduce or prevent it from being disturbed, and to maintain the correct function of the error correction code system and the correctness of the test result.
如图1所示，为普通没有配置校验功能保护的矩阵条目。As shown in Figure 1, it is a matrix entry that is not configured with the check function protection.
如图2所示，生成矩阵条目错误导致纠错码生成的码字校验位错误，从而导致 校验出的资料跟着错误。As shown in Fig. 2, the generation of the matrix entry error causes the codeword check bit generated by the error correction code to be erroneous, thereby causing the verified data to follow the error.
如图3所示，校验矩阵条目错误，即使生成正确的码字校验位后,校验矩阵条目错误却导致反而校验出错误的资料。As shown in Figure 3, the check matrix entry is incorrect. Even if the correct codeword check digit is generated, the check matrix entry error will result in the incorrect data being verified.
如图4所示，有配置校验功能保护的矩阵条目，即便如附图5在生成矩阵与校验矩阵条目发生错误时，都能够及时纠正，避免了纠错码编码/解码衍生的相关错误。As shown in FIG. 4, there is a matrix entry configured with the check function protection, even if an error occurs in the generation matrix and the check matrix entry as shown in FIG. 5, it can be corrected in time, and the error related to the error correction code encoding/decoding is avoided. .
本发明之二的纠错码矩阵存储/产生装置，在存储或产生矩阵条目时，同时存储或产生对应的矩阵条目校验位，该纠错码矩阵存储/产生装置输出矩阵条目给纠错码运算时同时输出矩阵条目校验位，用以避免矩阵条目发生错误导致纠错码编码/解码衍生的相关错误。如图6所示，纠错码矩阵存储/产生装置同时输出矩阵条目和矩阵条目校验位，使得编码时避免因矩阵条目发生错误导致纠错码编码衍生的相关错误。The error correcting code matrix storage/generating apparatus of the second aspect of the present invention simultaneously stores or generates a corresponding matrix entry check bit when storing or generating a matrix entry, the error correcting code matrix storing/generating device output matrix entry to the error correcting code The matrix entry check bits are simultaneously output during the operation to avoid errors associated with the error correction code encoding/decoding caused by errors in the matrix entries. As shown in FIG. 6, the error correction code matrix storage/generating means simultaneously outputs the matrix entries and the matrix entry check bits so that the associated errors caused by the error correction code encoding due to errors in the matrix entries are avoided during encoding.
以上实施例仅供说明本发明之用，而非对本发明的限制，有关技术领域的技术人员，在不脱离本发明的精神和范围的情况下，还可以作出各种变换或变型，因此所有等同的技术方案也应该属于本发明的范畴，应由各权利要求所限定。The above embodiments are merely illustrative of the invention, and are not intended to limit the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. The technical solution should also fall within the scope of the invention and should be defined by the claims.

Claims (5)

  1. 一种纠错码生成与校验矩阵的保护方法，其特征在于，在生成矩阵和校验矩阵产生与存储时均加入条目校验位。A method for protecting an error correction code generation and a check matrix, characterized in that an entry check bit is added when both the generation matrix and the check matrix are generated and stored.
  2. 根据权利要求1所述的纠错码生成与校验矩阵的保护方法,其特征在于，加入校验位的方式为：基于校验位循环核对或汉明码的方式，对每个矩阵条目加入对应的条目校验位。The method for protecting an error correction code generation and check matrix according to claim 1, wherein the method of adding a parity bit is: adding a correspondence to each matrix entry based on a check bit cycle check or a Hamming code manner. The entry check digit.
  3. 根据权利要求2所述的纠错码生成与校验矩阵的保护方法,其特征在于，当编译码核运行过程中生成矩阵和校验矩阵发生错误时，编译码核依照矩阵条目配合其条目校验位的校验运算，进行错误检出与错误校正。The method for protecting an error correction code generation and check matrix according to claim 2, wherein when the generation matrix and the check matrix are in error during the operation of the codec core, the codec core matches the entry of the entry according to the matrix entry. The check operation of the check position performs error detection and error correction.
  4. 一种纠错码矩阵存储/产生装置，其特征在于，在存储或产生矩阵条目时，同时存储或产生对应的矩阵条目校验位。An error correction code matrix storage/generation apparatus characterized in that, when a matrix entry is stored or generated, a corresponding matrix entry check bit is simultaneously stored or generated.
  5. 根据权利要求4所述的纠错码矩阵存储/产生装置，其特征在于，该纠错码矩阵存储/产生装置输出矩阵条目给纠错码运算时同时输出矩阵条目校验位。The error correction code matrix storage/generation apparatus according to claim 4, wherein the error correction code matrix storing/generating means outputs a matrix entry to simultaneously output a matrix entry check bit when the error correction code is operated.
PCT/CN2018/099737 2018-01-18 2018-08-09 Protection method for error correcting code generator and check matrixes, and matrix storage/generation device WO2019140888A1 (en)

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