CN105575439B - Method for correcting failure of storage unit and memory - Google Patents
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- 238000010586 diagram Methods 0.000 description 5
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
Abstract
The application discloses a method for correcting memory cell failure, which is applied to a memory and comprises the following steps: the memory stores a first set of data; when error bits occur in the first data set, error correction is carried out on the error bits through checking the check codes of the first data set; if the error correction of the error bit by checking the check code of the first data set fails, determining a second data set in the memory, wherein the first data set and the second data set have a preset incidence relation and the second data set contains the error bit; the error bits are corrected by checking the check code of the second set of data. Therefore, even if a plurality of error bits appear in one data set, and the check code of the data set cannot correct the errors, the error bits can be corrected one by the other check code of the data set which also contains the error bits, and the success rate of error correction is improved.
Description
Technical Field
The present disclosure relates to the field of storage, and in particular, to a method for correcting a memory cell failure and a memory.
Background
The realization of any system needs the support of hardware equipment, the common equipment in the hardware equipment is a chip with a storage function, the chip needs to perform a writing process when the chip needs to store received data, and when the data in the chip needs to be output, the data stored in the chip is output and read. However, during the writing process or the reading process, the writing error and the reading error which may be caused cannot be avoided. The two situations are embodied as a write error or a read error, one is bit (bit) hard failure, and the other is bit soft failure, where the bit hard failure refers to that a certain position in a hardware device memory in a chip for storing a bit is damaged by hardware, so that the position can only store one bit, for example, only a bit of "1", and the bit to be written into "0" is also stored as "1". Bit soft fail refers to bit errors due to data transmission due to fluctuation jumps during writing or reading of memory in the chip. Bit hard failures can only be corrected by repairing a hardware memory, while bit soft failures can be corrected by designing an error correction method, and the error correction method proposed at present mainly aims at the situation of bit soft failures.
The Error correction and detection schemes adopted in the current chip with the storage function are all Error Checking and Correction (ECC), the ECC schemes are all linear storage, the problems of power consumption and area are considered, the schemes can only correct single bit in read-write data, if multi-bit failure or errors caused in reading and writing are met, the ECC scheme used at present can not correct errors, and the Error correction success rate is low.
Disclosure of Invention
The application provides a method for correcting the failure of a storage unit, which can improve the success rate of correcting the failure of the storage unit in a memory and also provides a related memory.
In a first aspect, a method for correcting memory cell failures is provided, which is applied to a memory,
n storage units are arranged in the memory, each storage unit is used for storing a bit number, and the bit numbers stored by the M storage units form a first data set;
when the number of writing bits or the number of reading bits is carried out on the M storage units, namely when the first data set is written into or read from the M storage units, correspondingly generating check codes for checking the first data set in the M storage units; detecting whether error bits exist in the M storage units or not through the check code, and performing first error correction on the error bits through the check code when the error bits exist in the first data set;
if the first error correction fails, determining a second data set which has an association relation with the first data set, wherein the second data set is composed of bit numbers stored by Y storage units, the second data set contains the error bits, and the association relation between the first data set and the second data set can be realized by one association bit; and if the second data set has a corresponding check code for checking the second data set, the error bits can be corrected by checking the check code of the second data set. Therefore, even if a plurality of error bits appear in one data set, and the check code of the data set cannot correct the errors, the error bits can be corrected one by the other check code of the data set which also contains the error bits, and the success rate of error correction is improved.
In a possible implementation manner, the check code for checking the first data set and the check code for checking the second data set are both independently generated by the chip of the memory.
By means of circuit design of the chip of the memory, when the memory writes or reads data in the storage unit, the corresponding check code is automatically generated, and therefore the check code is generated without calculation generation of a scheduling check code function through a processor, generation efficiency of the check code is improved, and error checking and correcting efficiency of the check code is also improved.
In another possible implementation manner, the check code for checking the first data set is independently generated by a chip of the memory, and the check code for checking the second data set is generated by the processor by calling a check code function.
In order to enable the produced memory to be suitable for the error correction method provided by the application, the check code of the second data set can be generated by calling a check code function through the processor for calculation, namely, the chip of the memory does not need to be changed, and the compatibility of the product is improved.
A second aspect provides a memory storing a first set of data and a second set of data, the memory comprising an error correction unit and a determination unit;
the error correction unit is configured to: when error bits occur in the first data set, correcting the error bits by checking a check code of the first data set;
the determination unit is configured to: if the error bits cannot be corrected by checking the check code of the first data set, determining a second data set in the memory, wherein the first data set and the second data set have a preset association relationship, and the second data set contains the error bits;
the error correction unit is further configured to: and correcting the error bits by checking the check code of the second data set.
In another possible implementation manner, the memory includes an I/O interface, a controller, a cache, and a storage medium, the I/O interface is connected to the controller, the controller is connected to the cache, and the cache is connected to the storage medium; the storage medium has a first data set and a second data set stored therein, and the controller is configured to implement the following method:
when error bits occur in a first data set in the storage medium, correcting the error bits through checking a check code of the first data set;
if the error bits cannot be corrected by checking the check code of the first data set, determining a second data set in the storage medium, wherein the first data set and the second data set have a preset association relationship, and the second data set contains the error bits;
and correcting the error bits by checking the check code of the second data set.
Drawings
FIG. 1 is a schematic diagram of a method for error correction of memory cell failures according to the present application;
FIG. 2 is a schematic diagram of an association relationship between a first data set and a second data set in the present application;
FIG. 3 is another schematic diagram illustrating an association relationship between a first data set and a second data set in the present application;
FIG. 4 is a schematic diagram of a memory device according to the present application;
FIG. 5 is a schematic diagram of another memory device of the present application.
Detailed Description
The application provides a method for correcting the failure of a storage unit and a storage, which are used for improving the success rate of correcting the failure of the storage unit in the storage.
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, the present application provides a method for correcting a memory cell failure, applied to a memory, including the following steps:
101. the memory stores a first set of data; when error bits occur in the first data set, correcting the error bits by checking a check code of the first data set;
the data stored in the memory is stored in the form of bits of a binary number, one bit having the appearance of a "0" or a "1", and an ordered series of bits representing the particular contents of the data. The storage of bits by the memory is performed by linear storage, and a data set can be formed for a segment of linearly stored bits. Since an error may occur in a bit when the bit is stored, so that the data content has an error, a check code for checking the data set needs to be generated in the memory.
The check code has error checking and correcting capabilities, the check code used for checking the first data set is generated in the memory, and when the error bits in the first data set are detected, the error bits can be corrected by checking the check code of the first data set, so that the error bits are changed into correct bits.
102. If the error correction of the error bits by checking the check code of the first data set fails, determining a second data set in the memory, wherein the first data set and the second data set have a preset association relationship, and the second data set contains the error bits;
because the current check code error correction scheme can only carry out one-bit error correction and two-bit error checking on a section of linear bits, when two or more error bits appear in a section of linear bits, the current check code scheme can not carry out error correction and can not ensure that errors can be detected. Therefore, when the check code for checking the first data set corrects the first data set, a failure in correcting the first data set may occur. In order to correct two or more error bits occurring in the first data set, a two-dimensional error correction method is provided, in which a second data set associated with the first data set is determined, and the second data set includes the error bits. As shown in fig. 2, if the storage logic of the memory is regarded as a storage plane, and the first data set is a row in the storage plane, and the second data set can be a column in the storage plane, the first data set and the second data set have an association, so that there are bits that coincide with each other in the first data set and the second data set. When two or more error bits occur within the first data set, then a second data set in the column in which the error bits are located may be determined.
103. Correcting the error bits by checking a check code of the second data set;
as shown in fig. 2, the second data set, that is, the columns in fig. 2 also have corresponding check codes to perform error correction and error checking on the second data set, and when the check codes for checking the first data set fail to perform error correction, error bits are corrected by checking the check codes for checking the second data set, so that error correction is performed on two or more error bits occurring in one data set, and the accuracy of data is improved.
When the check code for checking the second data set fails to correct the error bits, it indicates that another one or more error bits also occur in the second data set, in this case, the two-dimensional error correction method provided in the present application may also be used to correct the error bits occurring in the second data set, that is, determine another data set to which the another error bits belong, correct the error bits by correcting the another data set, and after the error correction of the another error bits is successful, correct the error bits by checking the check code for checking the second data set, so that the error bits occurring in the multiple data sets can be corrected.
For example, referring to FIG. 3, the storage logic in the memory is set as a plane, the first data set includes 1 to 8 rows, and the second data set includes 1 to 8 columns. If the first error bit 301 appears in the 1 st row, the first error bit 301 is corrected by the check code corresponding to the 1 st row; for the second error bit 302 and the third error bit 303 appearing in the 2 nd row, the second error bit 302 is corrected by the check code corresponding to the 2 nd column; correcting the third error bit 303 by using the check code corresponding to the 4 th column, and correcting the fourth error bit 304 by using the check code corresponding to the 3 rd row if the fourth error bit 304 also appears in the 4 th column, and correcting the third error bit 303 by using the check code corresponding to the 4 th column after the correction is successful; in another possible implementation manner, after the second error bit 302 is successfully corrected by the check code corresponding to the 2 nd column, the third error bit 303 may also be corrected by the check code corresponding to the 2 nd row. Therefore, the two error bits appearing in the 2 nd row are successfully corrected, the error correction capability of the stored data is improved, and the accuracy of the memory for storing the data is also improved.
In a possible implementation manner, the check code for checking the first data set and the check code for checking the second data set are both independently generated by a chip of the memory.
In order to improve the rate of generating the check codes, the check codes of the first data set are independently generated by chips of the memory, that is, the check codes corresponding to all rows in the storage surface are independently generated by the chips of the memory; the same is true for the check code of the second data set. Therefore, the check codes of the rows and the columns are calculated and generated without scheduling a check code function by the processor, the rate of generating the check codes is improved, and the efficiency of checking the data set is improved.
In another possible implementation manner, the check code for checking the first data set is independently generated by a chip of the memory, and the check code for checking the second data set is generated by a processor by calling a check code function.
In the existing memory, when a manufacturer generates the memory, the chip on which the memory is fixed can only independently generate the check codes of the first data set, that is, can only independently generate the check codes of all rows through the chip of the memory, or can only independently generate the check codes of all columns through the chip of the memory, so that the manufactured memory is suitable for the two-dimensional error correction method provided by the application, the check codes of the second data set can be generated by calling a check code function through a processor, that is, the chip of the memory does not need to be changed.
In another possible implementation manner, the check code is a hamming code.
Since hamming code verification is a commonly used verification code with a high success rate of error correction and error checking in the prior art, in order to improve the success rate of error correction of the two-dimensional error correction method provided by the application, the verification code adopted by the application can also be realized by the hamming code.
Referring to fig. 4, the present application provides a memory 400, wherein the memory 400 stores a first data set and a second data set, and the memory comprises an error correction unit 401 and a determination unit 402;
the error correction unit 401 is configured to: when error bits occur in the first data set, correcting the error bits by checking a check code of the first data set;
the details are described with reference to 101.
The determining unit 402 is configured to: if the error bits cannot be corrected by checking the check code of the first data set, determining a second data set in the memory, wherein the first data set and the second data set have a preset association relationship, and the second data set contains the error bits;
the details are described with reference to 102.
The error correction unit 401 is further configured to: correcting the error bits by checking a check code of the second data set;
the details are described with reference to 103.
In one possible implementation, the number of the error bits is two or more.
In a possible implementation manner, the check code for checking the first data set and the check code for checking the second data set are both independently generated by a chip of the memory.
In a possible implementation manner, the check code for checking the first data set is independently generated by a chip of the memory, and the check code for checking the second data set is generated by a processor by calling a check code function.
In a possible implementation manner, the check code is a hamming code.
Referring to fig. 5, the present application provides a memory 500, where the memory 500 includes n I/O interfaces 501, a controller 502, a cache 503, and a storage medium 504, where the I/O interfaces 501 are connected to the controller 502, the controller 502 is connected to the cache 503, and the cache 503 is connected to the storage medium 504; the storage medium 504 has a first data set and a second data set stored therein, and the controller 502 is configured to implement the following method:
when an error bit occurs in a first data set in the storage medium 504, correcting the error bit by checking a check code of the first data set;
if the error bits cannot be corrected by checking the check code of the first data set, determining a second data set in the storage medium 504, where the first data set and the second data set have a preset association relationship, and the second data set includes the error bits;
and correcting the error bits by checking the check code of the second data set.
The memory 500 may include a volatile memory (RAM), such as a random-access memory (RAM); the memory may also include a non-volatile memory (english: non-volatile memory), such as a flash memory (english: flash memory), a hard disk (english: hard disk drive, abbreviation: HDD), or a solid-state drive (english: SSD); the memory 500 may also comprise a combination of memories of the kind described above.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (11)
1. A method for correcting memory cell failure, applied to a memory, the method comprising:
the memory stores a first set of data;
when error bits occur in the first data set, correcting the error bits by checking a check code of the first data set;
if the error correction of the error bits by checking the check code of the first data set fails, determining a second data set in the memory, wherein the first data set and the second data set have a preset association relationship, and the second data set contains the error bits;
correcting the error bits by checking a check code of the second data set;
if the error correction of the error bits by checking the check code of the second data set fails, determining that other error bits exist in the second data set;
determining a further set of data to which the further erroneous bits belong;
correcting the further erroneous bits by checking a check code of the further data set;
and after the error correction of the other error bits is successful, correcting the error bits again through the check code for checking the second data set.
2. The method of claim 1, wherein the number of the error bits is two or more.
3. The method of claim 1 or 2, wherein the check code for checking the first set of data and the check code for checking the second set of data are both generated independently from a chip of the memory.
4. The method of claim 1 or 2, wherein the check code for checking the first data set is generated independently by a chip of the memory, and the check code for checking the second data set is generated by a processor by calling a check code function.
5. The method of claim 1, wherein the check code to check the first set of data, the check code to check the second set of data, and the check code to check the additional set of data are Error Checking and Correcting (ECC) codes.
6. A memory, wherein the memory stores a first data set and a second data set, the memory comprises an error correction unit and a determination unit;
the error correction unit is configured to: when error bits occur in the first data set, correcting the error bits by checking a check code of the first data set;
the determination unit is configured to: if the error bits cannot be corrected by checking the check code of the first data set, determining a second data set in the memory, wherein the first data set and the second data set have a preset association relationship, and the second data set contains the error bits;
the error correction unit is further configured to: correcting the error bits by checking a check code of the second data set;
the determination unit is further configured to: if the error correction of the error bits by checking the check code of the second data set fails, determining that other error bits exist in the second data set;
determining a further set of data to which the further erroneous bits belong;
the error correction unit is further configured to: correcting the further erroneous bits by checking a check code of the further data set;
and after the error correction of the other error bits is successful, correcting the error bits again through the check code for checking the second data set.
7. The memory according to claim 6, wherein the number of the error bits is two or more.
8. The memory according to claim 6 or 7, wherein the check code for checking the first data set and the check code for checking the second data set are both independently generated by a chip of the memory.
9. The memory according to claim 6 or 7, wherein the check code for checking the first data set is independently generated by a chip of the memory, and the check code for checking the second data set is generated by a processor by calling a check code function.
10. The memory of claim 6, wherein the check code for checking the first set of data, the check code for checking the second set of data, and the check code for checking the additional set of data are Hamming codes.
11. A memory, comprising an I/O interface, a controller, a cache, and a storage medium, wherein the I/O interface is connected to the controller, the controller is connected to the cache, and the cache is connected to the storage medium; the storage medium has a first data set and a second data set stored therein, and the controller is configured to implement the following method:
when error bits occur in a first data set in the storage medium, correcting the error bits through checking a check code of the first data set;
if the error bits cannot be corrected by checking the check code of the first data set, determining a second data set in the storage medium, wherein the first data set and the second data set have a preset association relationship, and the second data set contains the error bits;
correcting the error bits by checking a check code of the second data set;
if the error correction of the error bits by checking the check code of the second data set fails, determining that other error bits exist in the second data set;
determining a further set of data to which the further erroneous bits belong;
correcting the further erroneous bits by checking a check code of the further data set;
and after the error correction of the other error bits is successful, correcting the error bits again through the check code for checking the second data set.
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| CN1165906C (en) * | 1998-02-25 | 2004-09-08 | 松下电器产业株式会社 | Error correction apparatus |
| CN101060015A (en) * | 2007-05-23 | 2007-10-24 | 北京芯技佳易微电子科技有限公司 | A multi-bit flash memory and its error detection and remedy method |
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Denomination of invention: A method for error correction of memory unit failure and memory Effective date of registration: 20210830 Granted publication date: 20200428 Pledgee: China Everbright Bank Taiyuan branch Pledgor: Shanxi Changhe Technology Co.,Ltd. Registration number: Y2021140000032 |
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Date of cancellation: 20221008 Granted publication date: 20200428 Pledgee: China Everbright Bank Taiyuan branch Pledgor: Shanxi Changhe Technology Co.,Ltd. Registration number: Y2021140000032 |
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Denomination of invention: A method of memory unit failure correction and memory Effective date of registration: 20230112 Granted publication date: 20200428 Pledgee: China Everbright Bank Taiyuan branch Pledgor: Shanxi Changhe Technology Co.,Ltd. Registration number: Y2023140000004 |
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Address after: 030000 room 707, block a, Gaoxin Guozhi building, No. 3, Dongyi second lane, Taiyuan Xuefu Park, Shanxi comprehensive reform demonstration zone, Taiyuan City, Shanxi Province Patentee after: Changhe Information Co.,Ltd. Address before: Room 707, block a, Gaoxin Guozhi building, No.3, Dongyi second lane, Taiyuan Xuefu Park, Taiyuan comprehensive reform demonstration zone, Shanxi Province 030000 Patentee before: Shanxi Changhe Technology Co.,Ltd. |
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Granted publication date: 20200428 Pledgee: China Everbright Bank Taiyuan branch Pledgor: Shanxi Changhe Technology Co.,Ltd. Registration number: Y2023140000004 |
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