CN101060015A - A multi-bit flash memory and its error detection and remedy method - Google Patents
A multi-bit flash memory and its error detection and remedy method Download PDFInfo
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Abstract
The invention provides a method for checking and correcting the error of a multi-bit flash and a relative multi-bit flash, wherein the multi-bit flash comprises a memory unit array composed of a plurality of memory units, a read/write control module and an error check and correct module with one-bit correct function. The memory unit array is used to store the first data and relative correct data, the nearby memory states of the memory unit are differential with one bit data, the error check and correct module can obtain the first data and relative correct data from the read/write control module, to use the correct data to correct and output the first data. The inventive method and device can recognize signal of multi-bit flash easily, with reliability of data stored in multi-bit flash, to improve density and yield of memory and save cost.
Description
Technical field
The present invention relates to a kind of multi-bit flash memory, the method for particularly a kind of multi-bit flash memory and error detection and correction thereof.
Background technology
Nonvolatile memory (NVM) device is generally metal-oxide-semiconductor, and this metal-oxide-semiconductor comprises that also an insulated body isolates from the floating boom of other parts (FLOATING GATE) except the source electrode, drain electrode and the gate pole that have general metal-oxide-semiconductor.
In floating gate type memory, floating boom is used to stored charge, still can keep under the situation of non-transformer supply.
In the process of and development scaled at storer, the density of data storage and every cost are the principal elements that promotes development.Present most of storage unit all is bistable, and promptly they deposit 0 or 1.If can deposit plural state in a unit, storage density will significantly increase so.
Multi-bit flash memory can be preserved long numeric data on a storage unit, thereby has improved the density of device.And the multidigit information of storing in the multi-bit flash memory relies on datum or electric current to differentiate to draw, and read operation can be regarded the signal that the unit is produced as and do mould-number (A/D) conversion.
The operation necessary condition of multi-bit flash memory is that the level distribution of each information correspondence is enough good, and is promptly at regular intervals between each threshold voltage distribution, do not overlap, and could utilize datum with block of information at different levels separately like this.
Yet, present manufacturing process can not reach the on all four effect of each storage unit, everywhere the threshold value Vth of transistor under same bias voltage is not quite similar on chip, because always there is the difference on the device, through adding up the threshold distribution situation that can draw under same bias voltage.
Threshold distribution can be represented the different logical value of whole storer, the fundamental prerequisite that must satisfy is that the threshold distribution of two states can be distinguished, as shown in Figure 1, promptly there is residual quantity Δ Vth in the main region of two threshold distribution, could distinguish the state of canned data like this by reference voltage.
Yet, it is long inevitable that tail appears in distribution, as shown in Figure 2, threshold value is in that the transistor of dash area belongs to bad point among the figure, can't be as the transistor that is in main distributed areas (part that does not comprise shade in the zone that curve and coordinate transverse axis are limited among Fig. 2) according to the reference voltage canned data that judges rightly.
Therefore in order to guarantee the yield of flash memory products, must adopt certain measure to repair the sense data of the bad point in the multi-bit flash memory.
Summary of the invention
The method that the purpose of this invention is to provide a kind of multi-bit flash memory and error detection and correction thereof, the sense data of repairing the bad point in the multi-bit flash memory.
To achieve these goals, the invention provides a kind of multi-bit flash memory, comprise memory cell array, read-write control module of forming by a plurality of storage unit and error-detecting and correction module with 1 bit data error correction, wherein:
Described memory cell array is used to store first data and corresponding check data thereof;
The different one digit number certificate of information between the adjacent memory states of described storage unit;
Described error-detecting and correcting after module is used for obtaining first data and corresponding check data from the read-write control module utilizes described checking data that first data are carried out error-detecting and corrected back output.
Above-mentioned multi-bit flash memory, wherein, the store status of described storage unit is defined by Gray code.
Above-mentioned multi-bit flash memory, wherein, described error-detecting and correction module specifically comprise:
Sense data receives submodule, be used for from the read-write control module receive first data and with corresponding first checking data of first data;
The decoding submodule is used for obtaining syndrome according to encode once more back resulting new checking data and first checking data of first data, and described syndrome is sent to the error correction submodule;
The error correction submodule, be used for judging according to syndrome whether first data make mistakes, and when makeing mistakes, correct data is sent to the IO interface sub-module after correcting mistake in described first data according to syndrome, otherwise directly described first data are sent to the IO interface sub-module;
The IO interface sub-module is used for sending to the outside after the data that receive the transmission of error correction submodule; The coding submodule after being used for receiving external data by the IO interface sub-module, sends to the read-write control module after data are encoded.
Above-mentioned multi-bit flash memory, wherein, described read-write control module comprises charge detection circuit, after being used for judging the store status of storage unit according to the electric current that flows through reference unit and the electric current that flows through storage unit, according to the corresponding data of the definition output of store status to error-detecting and correction module.
In order better to realize above-mentioned purpose, the present invention also provides a kind of multi-bit flash memory, comprises a plurality of storage areas, and each described storage area includes storage unit subarray, read-write control module and error-detecting and corrects module, wherein:
The storage unit subarray of being made up of storage unit is used to store first data and corresponding checking data;
The different one digit number certificate of information between the adjacent memory states of described storage unit;
Described error-detecting and correcting after module is used for obtaining first data and corresponding check data from the read-write control module utilizes described checking data that first data are carried out error-detecting and corrected back output.
Above-mentioned multi-bit flash memory, wherein, the store status of described storage unit is defined by Gray code.
Above-mentioned multi-bit flash memory, wherein, described error-detecting and correction module specifically comprise:
Sense data receives submodule, be used for from the read-write control module receive first data and with corresponding first checking data of first data;
The decoding submodule is used for obtaining syndrome according to encode once more back resulting new checking data and first checking data of first data, and described syndrome is sent to the error correction submodule;
The error correction submodule, be used for judging according to syndrome whether first data make mistakes, and when makeing mistakes, correct data is sent to the IO interface sub-module after correcting mistake in described first data according to syndrome, otherwise directly described first data are sent to the IO interface sub-module;
The IO interface sub-module is used for sending to the outside after the data that receive the transmission of error correction submodule;
The coding submodule after being used for receiving external data by the IO interface sub-module, sends to the read-write control module after data are encoded.
Above-mentioned multi-bit flash memory, wherein, described read-write control module comprises charge detection circuit, after being used for judging the store status of storage unit according to the electric current that flows through reference unit and the electric current that flows through storage unit, according to the corresponding data of the definition output of store status to error-detecting and correction module.
In order better to realize above-mentioned purpose, the present invention also provides a kind of method of error detection and correction of multi-bit flash memory, multi-bit flash memory comprises the storage unit that is used to store first data and corresponding check data thereof, the different one digit number certificate of information between the adjacent memory states of described storage unit, described method comprises:
Steps A is obtained first data and corresponding check data from storage unit;
Step B, error-detecting and correction module with 1 bit data error correction utilize described checking data that first data are carried out error-detecting and corrected back output.
Above-mentioned method, wherein, the store status of described storage unit is defined by Gray code.
Above-mentioned method, wherein, described step B specifically comprises:
Step B1, receive first data and with corresponding first checking data of first data;
Step B2 obtains syndrome according to encode once more back resulting new checking data and first checking data of first data;
Step B3 judges according to syndrome whether first data make mistakes, and when makeing mistakes, and correct data is sent to the outside after correcting mistake in described first data according to syndrome, otherwise directly described first data is sent outside.
Above-mentioned method, wherein, described steps A is specially: after judging the store status of storage unit according to electric current that flows through reference unit and the electric current that flows through storage unit, obtain corresponding data according to the definition of store status.
Method and apparatus of the present invention, the different one digit number of information of the adjacent memory states by define storage units according to after, utilize detection and the correction of ECC circuit realization to misdata, solved the difficult problem that gets of the signal identification that exists in the multi-bit flash memory well, the reliability that keeps the multi-bit flash memory data preferably, thereby improve the density and the yield of storer, save cost.
Description of drawings
Fig. 1 is the desired threshold distribution schematic diagram of 2 bit flash memories;
Fig. 2 the long synoptic diagram of tail occurs for the flash memory threshold distribution;
Fig. 3 is the structural representation of multi-bit flash memory of the present invention;
Fig. 4 is error-detecting of the present invention and corrects the structural representation of module;
Fig. 5 is the structural representation of the charge detection circuit in the read-write control module;
Fig. 6 is the structural representation of subregional flash memory of the present invention.
Embodiment
In the method for multi-bit flash memory of the present invention and error detection and correction thereof, in the store status of multi-bit flash memory storage unit, the only different one digit number certificate of adjacent states, simultaneously, the ECC that employing can only be carried out the error correction of one digit number certificate realizes storing the error detection and correction of data.
In multi-bit flash memory, because the tolerance limit of adjacent states is dwindled, distributing tail length occurs unavoidably, so the mistake of the information of the adjacent two states of the easiest appearance.For multi-bit flash memory, when adjacent states information makes a mistake, many times need to correct above the data of dibit could recover correct information (as 01 and 10, three bit flash memories of dibit 011 and 100 etc.), and the ECC circuit can't be realized the correction to the multidigit dislocation.
As for 2 bit flash memories, 2 dislocations have appearred though the ECC circuit can detect (01 and 10), and the ECC circuit only can be corrected 1 bit-errors, so whole data still can't be recovered.
Therefore, in the multi-bit flash memory of the present invention, only different 1 bit data of the data of the adjacent memory states of storage unit by such setting, can adopt the ECC circuit to realize detecting and error correction.
In specific embodiments of the invention, describe for convenient, defined one first data, its expression is stored in the data that do not comprise checking data in the storage unit.
As shown in Figure 3, multi-bit flash memory of the present invention specifically comprises memory cell array, read-write control module and error-detecting and correction module, wherein:
Memory cell array is used to store first data and corresponding check data thereof, comprise a plurality of storage unit, owing to be multi-bit flash memory, therefore storage unit comprises 4 or 4 above store statuss, comprise 4 store statuss during as 2 bit flash memories, 3 bit flash memories then comprise 8 store statuss, and the different one digit number certificate of the information between the adjacent memory states;
The read-write control module is used in response to read write command, behind the location of the storage unit in the memory cell array, carries out corresponding read-write operation;
Error-detecting and correction module, for carrying out the ECC circuit of 1 bit data error correction, be used for from read-write after control module obtains first data and check bit, after utilizing described check bit that data are carried out error-detecting and correction, export correct data, after also being used for simultaneously external data encoded according to the sign indicating number matrix and generating check bit, the data behind the coding and check bit are sent to the read-write control module carry out write operation.
Be that 2 bit floating boom transistors are that example is further elaborated with storage unit below.
For 2 bit floating boom transistors, in the present invention, according to the threshold voltage pairing information that distributes from small to large be: 00,01,11,10.
Error-detecting of the present invention and correction module comprise that specifically sense data receives submodule 41, decoding submodule 42 and error correction submodule 43, IO interface sub-module 44 and coding submodule 45 as shown in Figure 4, wherein:
Sense data receives submodule 41, be used for from the read-write control module receive first data and with the corresponding checking data of first data, and the described checking data and first data sent to decoding submodule 42, first data are sent to error correction submodule 43;
Decoding submodule 42 after being used for obtaining new checking data according to first data, obtains syndrome according to the new checking data and first checking data, and described syndrome is sent to error correction submodule 43;
In specific embodiments of the invention, error correcting code adopts Hamming code (Hamming Code), as extended hamming code and best strange weighted code etc.
Be that example further specifies with 2 bit flash memories below.
2 Bit datas are 00,01,10,11 according to traditional coded sequence, and according to coding of the present invention, it adopts Gray code to encode, and then the coded sequence of 2 Bit datas is: 00,10,11,01; Or 01,11,10,00; Or variety of way such as 00,01,11,10.
According to above-mentioned coded system, when adjacent states information makes a mistake, because it only has 1 to make a mistake, therefore the present invention is provided with error-detecting and corrects module in flash memory, can misdata that utilize reference voltage to judge be detected and correct by this error-detecting and correction module.
Utilize in the read-write control module of the present invention when read operation, can store m=2 in order to read one
nThe unit of individual level then needs m-1 reference current, gets final product output data after judging the relation between the zone of the electric current flow through storage unit and reference current qualification then.
Be example with 2 bit flash memories below, describe reading process that it specifically comprises following step in conjunction with the structural representation of charge detection circuit shown in Figure 5:
Obtain the electric current (reference current 1, reference current 2, reference current 3, memory cell current) that flows through 3 reference units and storage unit, be inversely proportional to its threshold voltage, therefore also can discern by comparing electric current owing to flow through the electric current of each unit;
Utilize comparator circuit (comparator circuit 1, comparator circuit 2 and the comparator circuit 3) relation of memory cell current and 3 reference currents relatively respectively, and the output logic level;
Can judge storage unit drops on which rank of (being the store status of storage unit) in the level Four level after the output result decoding of logical circuit according to comparator circuit, then determine 2 Bit datas, and export these 2 Bit datas of determining to error-detecting and correction module, its corresponding relation is as shown in the table, and (memory cell current is I1,3 reference currents are respectively I2, I3, I4, and I2＞I3＞I4):
| The relation of memory cell current and reference current | Corresponding data |
| I1＞I2＞I3＞I4 | 00 |
| I2＞I1＞I3＞I4 | 01 |
| I2＞I3＞I1＞I4 | 11 |
| I2＞I3＞I4＞I1 | 10 |
As can be seen from the above table, according to the comparative result of memory cell current and reference current and the corresponding relation between the storage data, the electric current that logical circuit can be judged storage unit according to the output result of comparator circuit is arranged in of 4 zones that 3 reference currents separate, promptly can judge the store status of storage unit, and then determine corresponding two bits information.
In conjunction with shown in Figure 4, after the reading of data, wherein first data and corresponding check data are sent to sense data reception submodule, and the checking data and first data are sent to the decoding submodule, simultaneously first data are sent to the error correction submodule by receiving submodule;
Decoding is after submodule obtains new checking data according to first data, obtains syndrome after utilizing the new checking data and the first checking data mould 2 to add;
The error correction submodule judges according to syndrome whether first data make mistakes, and when makeing mistakes, and corrects after the mistake in described first data correct data by the output of IO interface sub-module according to syndrome.
By above-mentioned description as can be seen, the present invention utilizes coding to combine with ECC, can Corrections Division at the data message of distribution tail end, difficult with the distribute signal identification that brings of improvement threshold.
For single investigation object, there is not the notion of distribution.The state differentiation of a single-transistor need reference voltage is between them and just can distinguishes.From this point of view, if all there is separately reference voltage each normal unit on the entire chip, (except the unit of damage) can wrongly not take place then.
Simultaneously, from the manufacturing process of flash memory, the characteristic between the storage unit of closing on more is approaching more, and therefore the threshold distribution of being separated by between the nearer storage unit must be littler than the difference between the threshold distribution of the storage unit far away of being separated by.
Based on above 2 points, another multi-bit flash memory of proposition of the present invention comprises a plurality of storage areas as shown in Figure 6, and each storage area all comprises storage unit subarray, charge detection circuit and ECC module, wherein:
The storage unit subarray is made up of storage unit, be used to preserve first data and corresponding check data thereof, storage unit in the storage unit subarray comprises 4 or 4 above store statuss, comprise 4 store statuss during as 2 bit flash memories, 3 bit flash memories then comprise 8 store statuss, and the different one digit number certificate of the information between the adjacent memory states.
As shown in Figure 6, after the nearer storage unit of will being separated by is divided into same storage unit subarray, because the threshold distribution between the storage unit in the storage unit subarray is more approaching, therefore the threshold distribution of the storage unit in the storage unit subarray is more concentrated with respect to the threshold distribution of all storage unit, and then after according to the threshold distribution situation of each storage unit subarray corresponding reference voltage being set respectively, this reference voltage can be judged the store status of storage unit more accurately.
Division for storage area can comprise following mode:
Physical location according to storage unit is divided situation as shown in Figure 6.
Number for storage area can be adjusted according to the quantity of storage unit and the area of memory device.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (12)
1. a multi-bit flash memory comprises memory cell array and the read-write control module be made up of a plurality of storage unit, it is characterized in that, also comprise having error-detecting and the correction module of one digit number according to error correction, wherein:
Described memory cell array is used to store first data and corresponding check data thereof;
The different one digit number certificate of information between the adjacent memory states of described storage unit;
Described error-detecting and correcting after module is used for obtaining first data and corresponding check data from the read-write control module utilizes described checking data that first data are carried out error-detecting and corrected back output.
2. multi-bit flash memory according to claim 1 is characterized in that the store status of described storage unit is defined by Gray code.
3. multi-bit flash memory according to claim 2 is characterized in that, described error-detecting and correction module specifically comprise:
Sense data receives submodule, be used for from the read-write control module receive first data and with corresponding first checking data of first data;
The decoding submodule after being used for obtaining new checking data according to first data, obtains syndrome according to the new checking data and first checking data, and described syndrome is sent to the error correction submodule;
The error correction submodule, be used for judging according to syndrome whether first data make mistakes, and when makeing mistakes, correct data is sent to the IO interface sub-module after correcting mistake in described first data according to syndrome, otherwise directly described first data are sent to the IO interface sub-module;
The IO interface sub-module is used for sending to the outside after the data that receive the transmission of error correction submodule;
The coding submodule after being used for receiving external data by the IO interface sub-module, sends to the read-write control module after data are encoded.
4. multi-bit flash memory according to claim 2, it is characterized in that, described read-write control module comprises charge detection circuit, after being used for judging the store status of storage unit according to the electric current that flows through reference unit and the electric current that flows through storage unit, according to the corresponding data of the definition output of store status to error-detecting and correction module.
5. a multi-bit flash memory is characterized in that, comprises a plurality of storage areas, and each described storage area includes storage unit subarray, read-write control module and error-detecting and corrects module, wherein:
The storage unit subarray of being made up of storage unit is used to store first data and corresponding checking data;
The different one digit number certificate of information between the adjacent memory states of described storage unit;
Described error-detecting and correcting after module is used for obtaining first data and corresponding check data from the read-write control module utilizes described checking data that first data are carried out error-detecting and corrected back output.
6. multi-bit flash memory according to claim 5 is characterized in that the store status of described storage unit is defined by Gray code.
7. multi-bit flash memory according to claim 6 is characterized in that, described error-detecting and correction module specifically comprise:
Sense data receives submodule, be used for from the read-write control module receive first data and with corresponding first checking data of first data;
The decoding submodule after being used for obtaining new checking data according to first data, obtains syndrome according to the new checking data and first checking data, and described syndrome is sent to the error correction submodule;
The error correction submodule, be used for judging according to syndrome whether first data make mistakes, if make mistakes, correct data is sent to the IO interface sub-module after then correcting mistake in described first data, otherwise directly described first data are sent to the IO interface sub-module according to syndrome;
The IO interface sub-module is used for sending to the outside after the data that receive the transmission of error correction submodule;
The coding submodule after being used for receiving external data by the IO interface sub-module, sends to the read-write control module after data are encoded.
8. multi-bit flash memory according to claim 6, it is characterized in that, described read-write control module comprises charge detection circuit, after being used for judging the store status of storage unit according to the electric current that flows through reference unit and the electric current that flows through storage unit, according to the corresponding data of the definition output of store status to error-detecting and correction module.
9. the method for the error detection and correction of a multi-bit flash memory, it is characterized in that, multi-bit flash memory comprises the storage unit that is used to store first data and corresponding check data thereof, the different one digit number certificate of the information between the adjacent memory states of described storage unit, and described method comprises:
Steps A is obtained first data and corresponding check data from storage unit;
Step B has one digit number and utilizes described checking data that first data are carried out error-detecting and corrected back output according to the error-detecting and the correction module of error correction.
10. method according to claim 9 is characterized in that the store status of described storage unit is defined by Gray code.
11. method according to claim 10 is characterized in that, described step B specifically comprises:
Step B1, receive first data and with corresponding first checking data of first data;
Step B2, obtain new checking data according to first data after, obtain syndrome according to the new checking data and first checking data;
Step B3 judges according to syndrome whether first data make mistakes, if make mistakes, correct data is sent to the outside after correcting mistake in described first data according to syndrome, otherwise directly described first data is sent outside.
12. method according to claim 10 is characterized in that, described steps A is specially: after judging the store status of storage unit according to electric current that flows through reference unit and the electric current that flows through storage unit, obtain corresponding data according to the definition of store status.
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| CN117116332A (en) * | 2023-09-07 | 2023-11-24 | 上海合芯数字科技有限公司 | Multi-bit error processing method, device, server and storage medium |
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