KR20090086523A - Nonvolatile memory with error correction based on the likehood the error may occur - Google Patents

Abstract

In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output. decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme. The likelihood is derived by comparing a measured memory cell voltage with more than one reference voltages. ® KIPO & WIPO 2009

Description

Non-volatile memory whose error is corrected based on the probability that an error can occur {NONVOLATILE MEMORY WITH ERROR CORRECTION BASED ON THE LIKEHOOD THE ERROR MAY OCCUR}

The present invention relates to a nonvolatile memory system and a method for operating the nonvolatile memory system.

Nonvolatile memory systems are used in many fields. Some nonvolatile memory systems are embedded in larger systems, such as personal computers. Other nonvolatile memory systems are removably coupled to the host system and can be compatible between different host systems. Examples of such removable memory systems include memory cards and USB flash drives. Electronic circuit cards, including nonvolatile memory cards, have been commercially implemented in accordance with a number of well-known specifications. Memory cards are used with personal computers, mobile phones, personal digital assistants (PDAs), digital still cameras, digital movie cameras, portable audio players, and other host electronic devices for storing large amounts of data. do. Such cards typically include a reprogrammable nonvolatile semiconductor memory cell array with a controller that controls the operation of the memory cell array and interfaces with the host to which the card is connected. Multiple cards of the same type may be compatible in host card slots designed to accept these types of cards. However, the development of many electronic card specifications has produced various types of cards that are somewhat incompatible with each other. Cards manufactured according to one specification are typically not usable by hosts designed to operate with cards of another specification. Memory card specifications include PC Card, CompactFlash ^TM Card (CF ^TM Card), SmartMedia ^TM , Multimedia Card (MMC ^TM ), Secure Digital (SD) Card, Mini SD ^TM Card, Subscriber Identity Module (SIM), Memory Stick ^TM ), memory stick duo card and microSD / TransFlash ^™ memory module specifications. There are several USB flash drive products available commercially from SanDisk under the trade name "Cruzer®". USB flash drives are typically larger and different types than the memory card described above.

Data stored in a nonvolatile memory system may contain incorrect bits when reading data. Traditional methods for reconstructing collapsed data include the application of Error Correction Codes (ECCs). Simple error correction codes encode data by storing additional parity bits, which sets the bits of the parity group to the required logical values when the data is written to the memory system. If there is an error in the data during storage, the bits of the parity group may change. When reading data from the memory system, the bits of the parity group are calculated once more by the ECC. Parity calculated due to data decay may not meet the required parity conditions, and ECC can detect the decay.

ECCs can have at least two functions: error detection and error correction. The ability for each of these functions is typically measured in a number of bits that can be sensed when they are wrong and then corrected. The sensing capability can be equal to or better than the calibration capability. A typical ECC can detect more error bits than can be corrected. The set of data bits and parity bits is sometimes called a word. An initial example is the (7,4) Hamming code, which has the ability to detect up to two errors per word (7 bits in the example of the present invention) and corrects one error in this 7 bit word. Have the ability to do so.

More complex ECCs can correct for more than a single error per word, but the data is more complex to reconstruct. A common practice is to recover data by some acceptable small probability of incorrect recovery. However, by increasing the number of errors, the probability of reliable data recovery is also rapidly reduced or the cost associated with additional hardware and / or performance becomes too high.

In a semiconductor memory device including EEPROM systems, data may be represented by threshold voltages of transistors. Typically, different digital data storage values correspond to different voltage ranges. For some reason, an error occurs if the voltage levels are shifted from their programmed ranges before or during the read operation. Errors can be detected by the ECC and in some cases these errors can be corrected.

A nonvolatile memory array is coupled to the decoder such that an encoded data read from the memory array is used to calculate probability values associated with the bits stored in the memory array. An example of such a decoder is a soft-input soft-output (SISO) decoder. Encoded data can be analyzed by high resolution, which provides an indication of the probability associated with the data bits, but is not merely a logical value of the data bits. For example, if binary data is encoded at + 1 / -1 volts in memory, the actual voltage reading can be used by the ECC decoder instead of just the sign. Probability values may be derived from readings or other sources. Probability values may be provided to the SISO decoder as soft-input. The output of the SISO decoder can be converted to hard-output by the converter. Hard-output represents the corrected data. In some cases, the SISO decoder may perform calculations in multiple iterations until some predetermined condition is met.

In non-volatile memory, high analytical readout can be achieved by selecting appropriate voltages for the individual read steps, so that higher density reads occur for some portion of the particular threshold voltage function than occurs elsewhere. Do it. This provides further analysis of the region of interest, for example if the threshold voltage function has significant overlap.

In nonvolatile memory, the demodulator may convert voltages from the memory array into probability values. If more than one bit is stored in a cell, individual probability values may be obtained for each bit. These probability values can be used as soft-input for the SISO decoder.

1 illustrates the probability functions of threshold voltages of cells programmed to a logic 1 state and a logic 0 state in a nonvolatile memory that includes a voltage V _D used to distinguish between logic 1 and logic 0 states.

2 shows components of a memory system including a memory array, modulator / demodulator circuits, and encoder / decoder circuits.

3 shows a probability function of read threshold voltages of cells programmed to a logic 1 state and a logic 0 state showing threshold voltage values.

4 shows components of a memory system including a memory array, modulator / demodulator circuits and encoder / decoder circuits, and a demodulator providing probability values to a decoder.

5 illustrates a NAND string coupled to a sensitive amplifier for reading the state of a memory cell.

FIG. 6A illustrates the probability functions of read threshold voltages of cells programmed to a logic 1 state and a logic 0 state comprising three threshold voltages. FIG.

FIG. 6B shows the probability functions of the read threshold voltages of cells programmed to 4 states and shows the threshold voltages from which cells are read. FIG.

7 shows individual probability values for both the first bit and the second bit as a function of the threshold voltage in a memory storing two bits per cell.

8 shows an encoder / decoder unit having a soft-input soft-output (SISO) decoder.

9 illustrates an example encoding scheme in which input data is arranged in a square matrix and parity bits are calculated for each row and column.

FIG. 10 shows a special example of a signal that is not dependent on noise that causes errors in data that cannot be corrected using a hard-input decoder but can be corrected using a SISO decoder.

11 shows parity bits with input data, input data arranged in rows and columns, parity bits calculated for each row and column.

FIG. 12 illustrates components of a memory system including an encoder providing the encoding shown in FIG. 11 and a demodulator providing low probability values to a SISO decoder.

FIG. 13A illustrates a first horizontal iteration performed by the SISO decoder of FIG. 12. FIG.

FIG. 13B illustrates a first vertical iteration performed by the SISO decoder of FIG. 12.

FIG. 13C illustrates a second horizontal iteration performed by the SISO decoder of FIG. 12. FIG.

FIG. 13D illustrates a second vertical iteration performed by the SISO decoder of FIG. 12.

14 illustrates a low density parity check (LDPC) parity check matrix used in a SISO decoder.

FIG. 15 illustrates an encoder / decoder with connected encoders and connected decoders.

For many nonvolatile memories, reading data from the memory array can have errors. That is, the individual bits of input data programmed into the memory array may be read later as present with different logic values. 1 shows the relationship between a physical parameter (threshold voltage, V _T ) representing a memory cell state and logic values to which a memory cell is to be programmed. In the example of the invention, only two states are stored in the cell. Thus, the cell stores one bit of data. Cells programmed to a logic zero state generally have a higher threshold voltage than cells in a logic one (unprogrammed) state. In an alternative scheme, the logical one state is the unprogrammed state of the memory cell. The vertical axis of FIG. 1 represents the probability of reading a cell at any particular threshold voltage based on the expected threshold voltage distribution. The first probability function is shown for cells programmed to logic one and for cells programmed to logic zero. However, these functions have some degree of overlap between them. The distinguishing voltage V _D is used for reading these cells. Cells with threshold voltages below V _D will be considered as state 1, while cells with threshold voltages above V _D will be considered as state 0. As shown in FIG. 1, this is not always correct. Because of the overlap between the functions, there is a non-zero probability that a memory cell programmed into a logic 1 state will be read as having a threshold voltage greater than V _D and therefore be read as being in a logic 0 state. Similarly, there is a non-zero probability that a memory cell programmed to a logical zero state will be read as having a logical one state.

Overlapping between functions occurs for a number of reasons, including physical defects in the memory array and interference due to cells programmed by later programming or read operations in the memory array. Overlapping can also occur due to a lack of general ability to maintain large numbers of cells within a very tight threshold voltage range. Certain programming techniques may allow the functions of narrow (with smaller specification deviations) threshold voltages. However, this programming can take more time. In some memory systems, more than one bit is stored in a memory cell. In general, it is desirable to store as many bits as possible in a memory cell. In order to efficiently use the available threshold voltages, the functions for adjacent states may exist so that they overlap considerably.

Nonvolatile memory systems commonly utilize ECC methods to overcome errors that occur in data read from the memory array. These methods typically calculate some additional ECC bits from the input data to be stored in the memory array, depending on the encoding system. Other ECC schemes can place input data in output data in more complex ways. ECC bits may generally be stored with the input data or stored separately. The input data and ECC bits are later read from the nonvolatile memory array and the decoder checks for any errors using both the data and the ECC bits. In some cases, these ECC bits may also be used to identify the bit in which an error exists. The wrong bit is then corrected by changing the state of the asset ("0" to "1" or "1" to "0"). Attaching ECC bits to data bits is not the only way to encode data before storing the bits in non-volatile memory. For example, data bits may be encoded according to a scheme that provides the following conversions: 00 to 1111, 01 to 1100, 10 to 0011, and 11 to 0000.

2 illustrates an example of input data stored in the memory system 200. The input data is primarily received by the ECC unit 201 including the encoder 203. The input data may be host data to be stored in the memory system 200 or data generated by the memory controller. The encoder 203 then calculates ECC bits 1111 from the input data bits using the encoding scheme. One example of an encoding scheme may be parity bits for selected groups of data bits.

Then both the input data bits and the ECC bits are sent to a modulation / demodulation unit 205 that includes a modulator 207. The modulator 207 converts the digital data transmitted by the ECC unit 201 into a form recorded in the memory array 209. In one scheme, digital data is converted into a plurality of threshold voltage values in a plurality of memory cells. Thus, various circuits used to convert digital data to threshold voltages stored in memory cells can be considered to form a modulator. In the example of FIG. 2, each memory cell can hold one bit of data. Thus, each memory cell may have a threshold voltage in one of two ranges representing a logic "1" state and a logic "0" state, as shown in FIG. Memory cells storing logic "1" state are small threshold voltage (than V _D <memory cells storing logic "0" state, while having a V _D) are larger threshold voltage than V _D has the (> V _D) . The cells can be programmed and proved to be nominal threshold voltages greater than V _D to ensure that there is at least some desired separation between the cells that were initially programmed into the two logic states.

Data may be stored in memory array 209 for a period of time. During this time, various events may occur to change the threshold voltages of the memory cells. In particular, operations including programming and reading may be applied to word lines and bit lines in a way that affects other previously programmed cells. Such disturbances are especially common when the area of devices is reduced such that the interaction between adjacent cells is meaningful. Charge can also be lost over a long period of time. Such data retention failures can also cause the data to be changed upon reading. As a result of these changes, the data bits may be a read output with states that are different from the initially programmed data bits. Also in the embodiment of Figure 2, one of the input data 211 it is read as having a small threshold voltage (<V _D) than V _D as it is written to the beginning to have a larger threshold voltage (> V _D) than V _D.

The threshold voltages of the memory cells are converted into bits of data by demodulator 213 in modulation / demodulation unit 205. This is the inverse of the process performed by the modulator. Demodulator 213 may include sensitive amplifiers that read a voltage or current from a memory cell in memory array 209 and derive the state of the cell from the read. In the Figure 2 example, the small threshold voltage (than V _D <memory cell having a V _D) provides a demodulated output of the "1" and the larger threshold voltage than V _D is "0 memory cell having a (> V _D) Provides demodulated output. This provides the output sequence 11011111 shown. The second bit 208 of this sequence is an error as a result of being stored in the memory array 209.

The output of demodulator 213 is sent to decoder 215 in ECC unit 201. The decoder 215 determines from the data bits and the ECC bits what errors exist. If a small number of errors are within the correction capability of the code, the errors are corrected. If a large number of errors are present, they can be identified but not corrected if they are within the sensing capability of the code. If multiple errors exceed the detection capability of the code, the errors may not be detected or result in incorrect correction. In the example of FIG. 2, the error in the second bit is detected and corrected. This provides an output 1001 from the same decoder 215 as the input sequence. Decoding of the memory system 200 is considered as hard-input hard-output decoding because the decoder 215 receives only data bits representing input data bits and ECC bits, and the decoder 215 receives input data bits. Output a corrected sequence of data bits corresponding to the data (or fail to provide an output if a number of errors are too high).

3 and 4 illustrate an alternative memory system for the memory system 200. 3 shows functions similar to those of FIG. 1 with threshold voltages below V _D representing logic _D 0 and voltages above V _D representing logic 1. Instead of showing a single voltage V _D that divides the threshold voltages into two different ranges, the threshold voltages are represented herein by actual voltage numbers. The function corresponding to logic "1" is at the center of zero volts or more and the function corresponding to logic "0" is at the center of "0" volts or less.

4 shows a memory system 421 using a data storage process similar to that of memory system 200 (using the same input data bits and ECC bits) with different read processes. In particular, instead of simply determining whether the threshold voltage is above or below a particular value, the memory system 421 reads the threshold voltages as shown in FIG. It will be appreciated that the actual threshold voltage does not necessarily need to be read. Other means of cell operation may be used to store and retrieve data (eg, current sensing). Voltage sensing is used only as an example. In general, the threshold voltage refers to the gate voltage at which the transistor is turned on. 4 shows a read generation that provides more detailed information than the above example. This can be considered a readout with a higher analysis (and an analysis that analyzes states than those used for programming) than the analysis of FIG. In the above example, errors occur in the read data. In this specification, the reads corresponding to the second and third bits are an error. The second and third bits, but logic "0" was stored so as to have a smaller threshold voltage than V _D to the cell by programming as cells with a threshold voltage of a high (V _D = 0) 0.05 volts and 0.10 volts than V _D Is read.

The low voltages read from memory array 423 of FIG. 4 by a series of read operations are sent to demodulator 425 in modulation / demodulation circuit 427. The low voltages have finite analysis indicated by the analysis of the analog-to-digital conversion. In this specification, the raw data is converted into probability data. In particular, each cell read is converted to a probability that the corresponding bit is one or zero. A series of reads (0.75, 0.05, 0.10, 0.15, 1.25, 1.0, 3.0, and 0.5 volts) from the memory array not only indicate the state of the cell, but can also be used to provide a degree of certainty about that state. . This can be expressed as the probability that the memory cell is programmed by a particular bit. Thus, readings close to zero volts may provide low probability values, while readings farther from zero volts provide higher probability values. The probability values shown are log likelihood ratios (described in more detail below). This provides negative values for the cells in the logical zero state and positive values for the cells in the logical one state, and the magnitude of the number represents the probability that the state is correctly identified. The second and third probability values 0.1, 0.2 represent a logic "1". The second and third values represent very low probabilities.

The probability values are sent to the decoder 429 in the ECC unit 431 (in some cases, obtaining the probability values from the row values can be considered as being performed at the decoder). Decoder 429 performs decoding operations on the probability values. Such a decoder can be considered as a soft-input decoder. In general, soft-input refers to an input that contains some quality information related to the data to be decoded. The additional information provided as soft-input generally allows the decoder to obtain a better result. The decoder may perform decoding calculations using soft-input to provide probability values calculated as output. This is considered as a soft-output and this decoder is considered as a soft-input soft-output (SISO) decoder. This output can then be used again as input to the SISO decoder to repeat decoding and improve the results. The SISO decoder can form part of a larger decoder that provides hard output to other units. SISO decoders generally provide good performance and in some cases may provide better performance than is possible by hard-input hard-output decoding. In particular, for the same amount of overhead (multiple ECC bits), the SISO decoder can provide greater error correction capability. In order to use the SISO decoder efficiently, an appropriate encoding / decoding scheme can be implemented and the demodulation is free of excessive complexity and efficient acquisition of soft-input without requiring excessive time to read data from the memory array. Apply.

In one embodiment, soft-input for the SISO decoder is provided by reading data in a non-volatile memory array by analysis that analyzes a number of states more than were used in memory programming. Thus, data can be written by programming the memory cell into one of two threshold voltage ranges and then read by analyzing three or more threshold voltage ranges. Typically, the multiple threshold voltages used in the readout may be several multiple multiple threshold voltage ranges (eg, twice) used in programming. But this is not always the case.

The encoder / decoder circuit (ECC unit) can be configured as a dedicated circuit or this function can be performed by firmware in the controller. Typically, a controller is an application specific integrated circuit (ASIC) with circuits designed for specific functions such as ECC and also having firmware to manage controller operations. Thus, the encoder / decoder may be formed by a combination of hardware and firmware in the memory controller. Modulator / demodulator circuits may reside on top of a memory chip, controller chip, individual chip, or some combination. In general, modulator circuits may include at least some components over a memory chip (such as peripheral circuits connected to a memory array). Although FIG. 4 shows the threshold voltages being read with high analysis (analog read), the degree of analysis selected may depend on a number of factors including the type of nonvolatile memory used.

5 shows a string 541 of a NAND flash memory array performing a read operation. A NAND flash memory is collectively composed of strings of memory cells that are connected and separated sequentially by selecting transistors in a group called blocks, the basic unit of erase. To read the selected cell, the other cells of the string are turned on hard so that the current flowing through the string depends on the selected cell. Appropriate bias voltages are located above the gates of the string select transistors 543 and 545 at each end of the string 541 (typically one end is connected to ground) and the one or more voltages sequentially over the selected cell. It is applied to the word line to be extended. For a cell holding one bit of data, only a single voltage may be needed. For cells that hold more than one bit (multi-level cells, or MLC), the voltage sequence typically consists of sequentially increasing voltage steps or binary search patterns. Each step corresponds to a distinct voltage. A cell storing two bits needs four states, and a cell storing three bits needs an eight state and the like. A sensitive amplifier 547 attached to the bit line determines when the cell switches on and the word line voltage causing this switching represents the threshold voltage range of the cell. Analysis of the read operation depends on a number of voltage steps provided. For example, a single bit read may require 25 microseconds to complete the sensitive operation, whereas a 2-bit read to the same memory may complete 75 sensitive seconds to complete three sensitive operations to fully analyze 4 states. Need. More voltage steps provide higher analysis but this requires more time. Less voltage steps increase speed but provide poor analysis. Typically, read operations are performed by the same analysis used to perform the program operations. Thus, if the program operation programs and verifies a cell in one of four states, the read operation has sufficient analysis to analyze the four threshold voltage ranges. This may require three voltage steps for a cell with four probability states. Various structures of NAND flash memory systems and methods of NAND flash memory systems are described in US Pat. Nos. 7,888,621, 7,092,290 and 6,983,428.

FIG. 6A shows an example of a single-bit memory cell read by high analysis that analyzes more than a number of states used in memory programming. As mentioned above, the horizontal axis represents the threshold voltage V _T and the vertical axis represents the probability of a cell having such a threshold voltage for a given programmed state. In the example of FIG. 1, a single read was performed to determine if the cell was programmed to one of two states. In contrast, three reads are performed herein to determine if a cell is in one of four read threshold voltage ranges 651-654. Thus, the cell is programmed by one of two threshold voltage ranges (corresponding to two logic states) and later analyzed by identifying the cell as being in one of four threshold voltage ranges (four read states). Is read.

The voltages V ₁ , V ₂ , V ₃ selected to perform the reads ensure that the four threshold voltage ranges 651-654 are not the same size and the reads are in two functions (logic 1 and logic 2). Is concentrated near the overlapping). _One read (at the differential voltage V ₂₎ is similar to _the read of FIG. 1 and indicates what state (0 or 1) is present and a memory cell is present. The other two reads (at V ₁ and V ₃ ) are within the threshold voltage ranges of logic 0 and logic 1 but are not concentrated in these threshold voltage ranges. Instead, these reads are placed closer to V ₂ . The four read threshold voltage ranges 651-654 provide an indication of the probability that a particular read bit is corrected. Thus, for logic 0, readings below V ₁ (threshold voltage range 651) have a high correction probability, while readings between V ₁ and V ₂ (threshold voltage range 652) are less likely to be corrected. For logic 1, readings between V ₂ and V ₃ (threshold voltage range 653) have a relatively low correction probability, while readings below V ₃ (threshold voltage range 654) have a higher correction probability. It can be seen that the readout has an analysis that analyzes a larger number of states than was used in programming that allowed the read operation to obtain probability information on the data being read.

6B shows an example of a 2-bit MLC memory cell in which there is a read with high analysis that analyzes more states than a number of programmed states. 6B shows a series of read operations being performed by increasing the analysis. During READ 1, the threshold voltage of the cell is analyzed in one of four states corresponding to a threshold voltage higher than V _1, less than, V between ₁ and V _2, between V ₂ and V _3, and V _3. This first read analyzes the same number of states as used for programming. Second read READ 2 is performed to provide higher analysis. READ 2 sets a programmed state such as "10" to the center of the threshold voltage function (between V ₅ and V ₆ ) and the two outer parts of the threshold voltage function (between V ₁ and V _5, between V ₆ and V ₂ ). Analyze into three read states corresponding to one). The third read, READ 3, is again performed to provide a higher analysis. READ 3 analyzes the read states of READ 2 so that the outer parts are further analyzed. In the example of the invention, the read states corresponding to the cores are not further analyzed. Read operations may be performed in the order of READ 1, READ 2, READ 3 or in any other order. Alternatively, individual read steps may be performed in several different orders so that they are combined in a single read operation. For example, the read steps may be performed by starting from the lowest threshold voltage and sequentially increasing in accordance with the threshold voltage. The read steps of READ 1, READ 2, and READ 3 are arranged in a pattern with a higher density of read operations of the outer portions of the threshold voltage function in a specially programmed state that is higher for the center. This provides information about the outer parts of more threshold voltage functions than the center of these functions. This is because a cell with a threshold voltage at the center of the threshold voltage function for a particular state can be assumed to have a high probability of being in that state (close to the zero probability of being present in other states) so that analysis is no longer required. to be. Other parts of a particular function can be nested with neighboring functions. More information about this overlap region (where the probability values change) would be desirable.

The foregoing detailed description relates to particular techniques for reading NAND flash memory cells. In some memories, a single read step may provide information regarding the programmed level of the memory cell. For example, in some NOR flash memories, the state of the memory cell is read by measuring current through the cell under certain bias conditions. In such a memory, a current mirror can be used to replicate the current from the cell, which can then be compared with several reference currents. Thus, high analysis reads can be performed in a single step.

7 shows how probability values for individual bits can be derived from threshold voltage information from a cell storing more than 1 bit of data. In this case, individual probability values are assigned to each bit. FIG. 7 shows the probability function for the four states 11, 10, 00, 01 of FIG. 6. 7 also shows the probability over all four threshold voltage ranges for the first bit (leftmost bit). The probability here is shown as the probability that a particular bit is "1". The probability may also be given as the probability that the bit is "0". A probability level of zero is shown. This is the level at which the same probability of 1 or 0 exists. Below the zero level, there is a greater probability of zero. Since both states of left "11" and "10" have "1" as the first bit, the probability about the left side of this graph is high (> 0). Since both states of the right "00" and "01" have "0" as the first bit, the probability about the left side of this graph is low (<0). 7 also shows the probability over all four threshold voltage ranges for the second bit (rightmost bit). This probability is high at the end of the threshold voltage range and low at the middle. Thus, the probability values for two bits are very different patterns. 7 shows a threshold voltage V1 providing a first bit probability P1 and a second bit probability P2. Here, P1 is large because it is not close to the threshold voltage associated with the state where threshold voltage V1 has "0" as the first bit. However, P2 is small because V1 is close to the threshold voltage range for the "10" state. This indicates that while this bit may be 1, the probability is slightly higher than the probability that it is 0. 7 shows that the probability may be very different for different bits stored in the same cell. Although the read operation represents a threshold voltage that exists within the region of overlap between threshold voltage ranges of neighboring states and thus increases the risk of false readings, the individual bits are present between the two states where the overlap generally has both individual bits. It can have a very high probability value. Thus, it may be beneficial to determine the probability based on the bit-bit instead of based on the cell-cell. The demodulator may provide low probability values based on reads from the memory array using the correlation between the threshold voltage and the individual bit probability values as shown in FIG. 7. If the read operation identifies a threshold voltage range for the cell, the probability values for each bit may be associated with each of these ranges. Probability values may be derived from various information, such as characteristics of memory cell behavior for a given technique, or the experience of a given memory device. In some cases, the probability values may change at different stages over the lifetime of the device.

Probability can be expressed in other ways. One common way to express probabilities for binary data is the Log Likelihood Ratio (LLR). The LLR associated with a particular bit is the log of the ratio of the probability that the bit is "1" to the probability that the bit is "0" for the particular read x. therefore:

는 비트가 "1"인 확률이고,

는 비트가 "0"인 확률이다. LLR은 비록 다른 시스템들이 또한 사용될 수 있다고 하더라도 확률을 표현하기 편리한 방법이다. 메모리로부터 판독들로부터 확률을 획득하기 위해, 몇몇 변환 또는 복조가 일반적으로 수행된다. 이러한 복조를 수행하기 위한 하나의 편리한 방법은 임계 전압(또는 메모리 내 몇몇 측정된 파라미터)과 하나 이상의 비트들의 확률 값들 간의 관계를 표로 만드는 룩업 테이블을 사용하는 것이다. 판독 동작의 분석이 메모리 셀의 임계 전압 범위를 N 판독 상태들로 구분하는 경우, 셀은 R 비트들을 저장하고, 테이블은 확률이 각각의 판독 상태에 대해 각각의 비트를 위해 제공되도록 N×R 에트리들을 가질 수 있다. 이러한 방법에 있어서, 높은 분석 판독은 메모리내에 저장된 데이터에 관해 확률 정보를 제공할 수 있다. 이러한 로우 확률 데이터는 디코더로의 소프트-입력으로서 디코더에 제공될 수 있다.here

Is the probability that the bit is "1",

Is the probability that the bit is "0". LLR is a convenient way to express probability, although other systems can also be used. In order to obtain a probability from readings from memory, some transformation or demodulation is generally performed. One convenient way to perform this demodulation is to use a lookup table that tabulates the relationship between the threshold voltage (or some measured parameter in memory) and the probability values of one or more bits. If the analysis of the read operation divides the threshold voltage range of the memory cell into N read states, the cell stores the R bits, and the table stores the N × R attributes so that a probability is provided for each bit for each read state. You can have a ladle. In this way, high analytical readings can provide probability information about the data stored in memory. Such low probability data may be provided to the decoder as a soft-input to the decoder.

8 shows soft-input data as described above being supplied to a decoder system 861 including a SISO decoder 863. SISO decoders generally accept low probability data and perform ECC calculations on the low probability data to provide the calculated probability data. The calculated probability data can be considered as soft-output. In many cases, this soft-output is provided as an input to the SISO decoder to allow a second decoding iteration to be performed. The SISO decoder may perform successive iterations until at least one predetermined condition is achieved. For example, the predetermined condition may be that all bits have a probability greater than a predetermined minimum value. The predetermined condition may also be the sum of the probability values, such as the mean probability value. The predetermined condition may be the convergence of the results from one iteration to the next (ie, repeat the iteration until there is some improvement from further iterations). The predetermined condition may be that a predetermined number of iterations are completed. Combinations of these conditions can also be used. Decoding is performed using an encoded pattern in the data that is the result of the encoding performed by the encoder 865 on the data before the data is stored. Encoder 865 and decoder system 865 are both considered parts of ECC unit 867, and ECC unit 867 may be implemented within a memory system such as memory system 421 (ECC unit 867). Is an example of a unit that can be used as the ECC unit 431). Various encoding schemes can be used with the SISO decoder. Decoder 861 may also include a hard-soft converter 864 to convert the soft-output from SISO decoder 865 to hard output.

In some cases, SISO decoding may provide better error correction for the same amount of overhead data than hard-input hard-output decoding does. 9 illustrates an example encoding scheme that may be used in an SISO decoder such as SISO decoder 863. Data entries D ₁₁ -D ₃₃ are arranged in rows and columns with parity bits calculated for each row and column. For example, P ₁ is calculated from the row containing entries D ₁₁ , D ₁₂ and D ₁₃ . Similarly, P ₂ is calculated from the row containing entries D ₂₁ , D ₂₂ and D ₂₃ . P ₄ is calculated from the column containing entries D ₁₁ , D ₂₁ and D ₂₃ .

FIG. 10 shows the result when the encoded data as shown in FIG. 9 is later decoded in both the hard-input hard-output decoder and the SISO decoder. In this embodiment, the two logical states of the binary system are represented by -1 and +1 instead of 0 and 1, respectively. It will be appreciated that any suitable indication may be used and this indication is merely for convenience of this example. For soft numbers, the sign indicates whether the bit is necessarily 0 or 1 and the magnitude of the number indicates the probability that it is a correct value.

Signal 101 is shown as a group of bits including data bits and parity bits calculated according to the encoding scheme of FIG. 9. The signal is generally the output of an encoder with appropriate circuits for calculating parity bits. The signal can then be provided to a modulator that provides the appropriate voltages to the memory cells for programming the memory cells into states for writing signal data.

Noise 103 is shown to affect two data bits in the example of the present invention. Noise is not limited to data bits and may also affect parity bits. Noise may be the result of some physical characteristics of particular cells or of disturbances that occur in memory when one cell is affected by operations performed on other cells in the array. In the example of the invention, the noise is considered to be further and thus the data read from the memory reflects the signal data plus noise, which becomes the input data for decoding. However, noise can have a positive or negative effect on the reading.

Input 105 is raw data obtained from a demodulator connected to a memory. For example, if the read operation is performed by high analysis, the input data may be generated in this form such that the bits of the signal or parity data are represented as 0.1 instead of 1 or 0. This can be considered a probability value having a positive value representing 1 and a negative value representing 0, where the indicated state is the magnitude of the value representing the correct probability. Input 105 is considered a soft-input, where input 105 simply contains a zero or one value.

Hard-Input For a hard-output decoder, input 105 is converted to hard input 107 by replacing all positive values with +1 and replacing all negative values with -1. In a system that uses one's complement logic to represent soft-input probability values, the most significant bit represents a sign and can be used as a means of conversion. Hard-Input Hard-Output Decoder may attempt to correct data using this hard input. However, parity calculations represent an error in each of the second and third matrices and an error in each of the second and third columns. There is no unique solution in this situation because D22 and D33 may be errors or alternatively D32 and D23 may be errors. The hard-input hard-output decoder cannot determine which of these solutions is correct. Thus, the hard-input hard-output decoder cannot correct data in this situation.

In the first SISO decoding step, soft-input correction data 109 is generated for the first row from the input. Each entry of the soft-input correction data 109 is calculated from the sign of the product of the other entries in the same matrix and the size of the minimum entry in the matrix (calculation of probability values is described in more detail below). This provides an indication of which of the other entries in the matrix should be and can be a calculated probability or a non-essential probability (as opposed to the inherent possibility of the input). The soft-input correction data 109 is then added to the input 105 to obtain the first matrix-repeated soft-output 111. Thus, the first matrix-repeat soft-output 111 combines intrinsic probability values with non-essential probability values. The soft-output reflects both the intrinsic probability information from the row data and the non-essential probability information derived from other entries in the same row sharing the same parity bit. Looking at the sign of the soft-output 113 at the time of converting the soft-output to the hard-output, we see that the data is fully corrected. Thus, soft-input soft-output decoding can correct this data, which cannot be a hard-input hard-output decoder. Moreover, the soft-input soft-output decoder can make this correction in one iteration using only matrix parity calculations. If the correction has not been completed, further calculations may be performed using thermal parity calculations. If this first column-repeat did not provide full correction, the second matrix-repeat may be performed. Thus, the SISO can continue working towards a solution where the hard-input decoder stops without finding a solution.

A second example is shown in FIG. As in the above example, parity bits are calculated for both matrices and columns of input data (in the example of the invention, only two input data per matrix or column). Where the parity bits are calculated to be a modulo two of the input data bits of the matrix or column.

12 shows input data received by encoder 121 in ECC unit 123 that calculates parity bits and adds them to the data. In this case, four bits of parity data are added to four bits of input data. Thus, the input data and parity bits form encoded signal data that is sent to modulator 125. The modulator 125 programs the individual memory cells in accordance with the signal data. In this case, two bits are stored in the memory cell of the memory array 126 so that eight bits of the signal data are stored in four cells having respective threshold voltage levels V1-V4. The memory cells are then read as having threshold voltage ranges V1'-V4 '. Read threshold voltage ranges are modulated in demodulator 127 to provide low probability data (1.5, 1.0, 0.2, 0.3, 2.5, 2.0, 6.0, 1.0). This can be obtained using a lookup table or something else. In some cases, providing a low probability is considered as a function in the decoder, but for the present case it is considered as occurring in demodulator 127. Although low probability values are obtained for each bit and the bits are stored in the same cell, they may have different low probability values. In the example of the present invention, demodulator 127 provides the probability values as log probability ratio values, although the probability may also be represented in other formats. The low probability values are positive for all data entries indicating that if a hard-output was obtained directly from these entries, all data entries would be considered to be 1 at the time (providing 2 errors). However, by using the SISO decoder 129 in the ECC unit 123, the data can be completely corrected. 13A-13D illustrate how the SISO decoder 129 corrects input data. Decoder 129 is a special example of a SISO decoder that can be used in a memory system such as memory system 421 (decoder 129 can be used as decoder 429).

FIG. 13A shows a first horizontal iteration using low parity bits 131 to obtain first calculated probability values 133 from matrix probability values 132. In this case, LLRs are added to obtain calculated probability values 133. In the example of the present invention it can be seen that the sum of the two LLRs is given by the product of the signs of the two LLRs multiplied by the smaller LLR value and (-1).

는 LLR 추가(addition)를 나타낸다. 엔트리들에 이러한 LLR 추가를 적용함으로써 도시된 계산된 확률 값들을 제공한다. 예를 들어, 엔트리 D₁₁에 대응하는 계산 확률은 0.1

2.5

-0.1이며, 엔트리 D₁₂에 대응하는 계산된 확률은 1.5

2.5

-1.5이다. 그 다음, 계산된(비본질적인) 확률 값들(133)은 로우(본질적인) 확률 값들(132)에 추가되어 제 1 수평 반복으로부터 출력 확률 값들(135)을 획득한다. 따라서, 엔트리 D11에 대응하는 출력 확률 값은 로우 확률값 1.5 + 계산된 확률값 -0.1이며, 1.4가 된다. 알 수 있는 바와 같이, 상단 행렬(1.4, -1.4)의 출력 확률 값들(135)은 올바른 비트들이 1과 0을 나타내는 상대적으로 높은 확률 값들을 나타낸다. 그러나 하단 행렬(-0.1, 0.1)의 확률 값들(135)은 비트들이 각각 0과 1인 낮은 확률 값들을 나타낸다. 이들 확률 값들은 올바른 입력 비트들을 나타낸다. 그러나 이러한 낮은 확률 값들은 이 시점에서 디코딩을 종료하기에 충분하다고 간주되지 않을 것이다. 따라서, 추가적인 반복들이 수행될 수 있다.here,

Denotes an LLR addition. Applying this LLR addition to the entries provides the calculated probability values shown. For example, the calculation probability corresponding to entry D ₁₁ is 0.1

2.5

-0.1 and the calculated probability corresponding to entry D ₁₂ is 1.5

2.5

-1.5. The calculated (non-essential) probability values 133 are then added to the low (essential) probability values 132 to obtain output probability values 135 from the first horizontal iteration. Therefore, the output probability value corresponding to the entry D11 is the low probability value 1.5 + the calculated probability value -0.1 and becomes 1.4. As can be seen, the output probability values 135 of the top matrices 1.4, -1.4 represent relatively high probability values where the correct bits represent ones and zeros. However, the probability values 135 of the bottom matrix (-0.1, 0.1) represent low probability values with bits 0 and 1, respectively. These probability values represent the correct input bits. However, these low probability values will not be considered sufficient to end decoding at this point. Thus, additional iterations may be performed.

13B shows output probability values 135 from a first horizontal iteration that depends on the first vertical iteration using column parity bits 137. The calculated probability values 139 of the first vertical iteration are calculated in the same way as before, this time being used with the columns using the column parity entries 137. Thus, D11 is obtained from the LLR sum of D12 and P3 (-0.1 and 6.0, which is 0.1). D12 is obtained from the LLR sum of D11 and P3 (1.4 and 6.0, which is -1.4). In this way, the calculated probability values 139 are obtained for each entry. The calculated (non-essential) probability values 139 are then added to the input probability values 135 (output probability values of the first horizontal iteration) to obtain output probability values 141 of the first vertical iteration. The output probability values 141 obtained from the first vertical iterations (1.5, -1.5, -1.5, 1.1) may be considered sufficient to end decoding at this point. However, more decoding iterations may be performed, depending on the predetermined condition needed to end decoding.

13C shows the second horizontal iteration being performed. Probability values 139 calculated from the first vertical iteration are added to the low probability values 132 to obtain input values 143. The input values 143 are then used together with the matrix parity entries 131 as before to obtain second horizontally calculated probability values 145. Second horizontal probability values 145 are then added to input values 132 to obtain output probability values 147 of the second horizontal iteration. The output probability values 147 of the second horizontal iteration do not provide an overall improvement in the probability values from the output of the first vertical iteration.

13D shows the second vertical iteration being performed. Output values 147 from the second horizontal iteration are used as input values during this iteration. The column parity entries 137 are used with the input values to obtain probability values 149 calculated as before. The calculated probability values 149 are then added to the input probability values 147 to obtain output probability values 151. The output values 151 from the second vertical iteration are shown to be improved compared to the output values 141 from the first vertical iteration. Thus, it can be seen that additional iterations can provide further improvement in the data.

Iterative decoding may be a cycle through iterations until some predetermined condition is met. For example, the predetermined condition may be that each probability value in the output set of probability values exceeds some minimum probability value. Alternatively, the predetermined condition may be several parameters derived from one or more probability values, such as minimum or average probability. The predetermined condition may simply be that certain iterations are performed. In some cases (discussed later), output probability values are subject to other operations that indicate whether additional SISO iterations are performed or not.

13A-13D may consider an example of a technique known as turbo coding. Horizontal and vertical parity bits provide two alternative encoding schemes that can be decoded separately. By using the output from one decoding scheme as input for the other with two such decoding schemes, turbo coding generally provides high error correction capability.

Efficient decoding depends on having an appropriate encoding / decoding scheme. Various schemes are known to encode data in a suitable way for continuous decoding in a SISO decoder. Encoding / decoding schemes include turbo codes, product codes, BCH codes, Reed-Solomon codes, convolution codes (see US patent applications Ser. Nos. 11 / 383,401 and 11 / 383,405), hamming codes, and Includes but is not limited to Low Density Parity Check (LDPC) codes.

LDPC codes are codes with a parity check matrix that meet certain requirements and result in a poor parity check matrix. This means that each parity check is performed over a relatively small number of bits. An example of a parity check matrix H for an LDPC code is shown in FIG. 14. The conditions for LDPC codes are: (1) The number of 1s in each matrix is the same and the number is less than the total number of entries in the matrix. (2) The number of 1s in each column is the same and the number is less than the total number of entries in the column. (3) Typically, the number of 1s in any two rows is not greater than 1 (typically the number of 1s can only be 0 or 1). Irregular LDPC codes allow some variation in the number of 1s in columns and matrices. Looking at H, each matrix has three 1s out of all seven entries in the matrix so that condition (1) is met. Each column has three 1s out of all seven entries in the column so that condition (2) is met. Typically, two columns have more than one 1 so that condition (3) is not satisfied. For example, the first, second and fourth columns all have 1 as the top entry, but typically none of these columns have the other 1. Thus, matrix H defines the LDPC code. The code consists of all the code words that satisfy the matrix H. This means that seven different parity check conditions (defined by seven matrices) must be met. Each parity check condition examines three entries in a word. For example, the first matrix indicates that the first, second and fourth entries should have a sum modulo 2 of zero.

Data can be encoded according to the LDPC code by calculating certain parity bits to form a codeword. Therefore, the codeword of the parity check matrix H may be formed of three parity bits calculated from four data bits and four data bits. Each parity bit is calculated from a relatively small number of data bits, so the encoding can be relatively simple, even a large number of entries are encoded as a block.

An LDPC code suitable for memory applications uses a word of about 4,000-8,000 bits (1-2 sectors, where the sector is 512 bytes). For example, encoding according to the LDPC code may add about 12% to unencoded data. The number of 1s in a matrix of parity check matrix, such as this code, may be about 32 of about 4,000, so that even if the word is large, the parity calculations are not excessively long. Thus, parity bits can be calculated relatively easily during encoding, and parity can also be checked relatively easily during decoding. LDPC codes can be used with hard-input hard-output decoding or SISO decoding. As shown above, SISO decoding can sometimes improve performance over hard-input hard-output decoding. The low probability values may be supplied to the SISO decoder as LLRs or in some other form. LDPC may use the SISO decoder in an iterative manner. The entry is common to several parity groups so that calculated probability values obtained from one group provide improved data for another parity group. These calculations may be performed repeatedly until some predetermined condition is met.

LDPC decoding can sometimes give poor results when the number of errors is very small. Correction errors below a certain number make it difficult to produce an "error floor". One solution to this problem is to combine LDPC decoding with some other form of decoding. A hard-input hard-output decoder or some similar algebraic code using BCH may be added to the LDPC decoder. Thus, after the LDPC decoder reduces the number of errors to a slightly lower level, the BCH decoder decodes the remaining errors. Decoders that operate continuously in this way are referred to as "chained." Concatenated encoding is also performed before the data is stored in the memory array in this case.

15 shows an example of concatenated encoding and decoding in an ECC unit 155 that includes an encoding system 157 and a decoding system 159. Data is first encoded by encoder A, which is received by ECC unit 155 and encoded according to encoding scheme A. The encoded data is then primarily encoded at encoder B, which is encoded according to the encoding scheme B. In the example of the present invention, encoding scheme A is a BCH encoding scheme that adds parity bits to input data, which in one example increases the amount of data by about 4%. Encoding scheme B is an LDPC encoding scheme that adds additional parity bits to the encoded data from encoder A, which in the example of the present invention adds an additional 12% to the data. The double encoded data is then transferred to a modulation / demodulation unit and programmed into a nonvolatile memory array. The dually encoded data is then read from the memory array and demodulated to provide soft-input to decoder B. Decoder B decodes the data using encoding scheme B. Similarly, decoder A uses encoding scheme A. Decoder B of the example of the present invention is a SISO decoder that performs one or more decoding iterations on double encoded data. When some predetermined condition is met, decoder B sends the output data to decoder A. The output data from decoder B generally does not include entries for parity bits added by encoder B. These entries have already been used by decoder B and are no longer needed. The output of decoder B is a soft-output. This soft output may be converted to hard-data in a soft-hard converter 161 that removes probability information and converts the data into binary information. This hard data is then provided as hard-input to decoder A, which performs hard-input, hard-output decoding. The hard-output from the hard-output second decoder is then sent from the ECC unit 155 as corrected data.

In one embodiment, the predetermined condition for terminating repetitive decoding at decoder B is that decoder A indicates that the data is good. After the iteration at decoder B is complete, the soft-output can be converted to hard data and provided to decoder A as hard-input. Decoder A then tries to decode the data. If decoder A cannot decode the data, decoder B performs at least one additional iteration. If decoder A can decode the data, no further iterations are needed at decoder B. Thus, in the example of the present invention, decoder A provides feedback 163 to decoder B to indicate when decoder B terminates.

Although the example of FIG. 15 addresses a chain of hard-input hard-outputs, other combinations may also be used. Two or more SISO decoders may be used in succession and two or more hard-input hard-output decoders may also be used.

In the above examples, soft-input is obtained by reading data with a higher analysis than that used to program the data. In other examples, other information may be used to derive soft-input data. Any quality information additionally provided to simply determine 1 or 0 for the data bits stored in the memory can be used to provide soft-input. In some memory designs, the count is maintained the number of times the block has been erased. The physical nature of the memory can change in a predictable way, such as eliminating count increments and making certain errors more frequent. The erase count can be used to obtain probability data for which this pattern is known. Other factors known to affect the programmed data in a predictable manner can also be used to obtain probability information. In this way, data can be read from the memory array by the same analysis used to program the data and continue to be used to provide soft-input. Various sources of probability information can be combined. Thus, probability information from read data with high analysis can be combined with probability data from other sources. Thus, soft-input is not limited to probability information obtained directly by reading the memory array.

The various examples described above are referred to as flash memory. However, various other nonvolatile memories are currently in use and the techniques described herein may be applied to any suitable nonvolatile memory systems. These memory systems are memory systems based on ferroelectric storage (FRAM or FeRAM), memory systems based on magnetoresistive storage (MRAM), and memory based on phase change (PRAM or "OUM" for "Ovonic Unified Memory". ), But is not limited thereto.

All patents, patent applications, papers, textbooks, specifications, other publications, documents, and references herein are incorporated by reference in their entirety for all purposes. There will be any discrepancies or conflicts in the definition or use of terms between all cited publications, documents and the text of the present document, or in the use of the term in the document of the present invention.

Although various embodiments of the invention have been described with respect to certain preferred embodiments, it is understood that the invention is protected within the scope of the appended claims.

As described above, the present invention is used to provide a nonvolatile memory system and a method for operating the nonvolatile memory system.

Claims (46)

A method for decoding data encoded according to a predetermined scheme and stored in a nonvolatile memory array, the method comprising: Reading the encoded data from the nonvolatile memory array to obtain a plurality of bits; Obtaining probability information about the plurality of bits; And Calculating output probability values calculated from the plurality of bits and the probability information using the predetermined scheme. Including a data decoding method. 2. The method of claim 1, wherein obtaining probability information about the plurality of bits comprises encoding the encoded data by analysis to analyze more read states than the plurality of program states used to program the encoded data. And reading the data. The method of claim 1, wherein calculating the output probability values occurs in a first iteration, and then the output probability values are used to calculate additional output probability values using the predetermined scheme in at least one additional iteration. Data decoding method. 4. The method of claim 3, wherein the additional probability values are calculated at additional iterations until a predetermined condition is met. The method of claim 1, wherein the output probability values are used to obtain hard data provided to a hard-input hard-output decoder. A method for storing and retrieving data in a nonvolatile memory array, the method comprising Receiving a plurality of input data bits to be stored in the nonvolatile memory array; Calculating a plurality of redundant data bits from the plurality of input data bits; Storing the plurality of redundant data bits in the plurality of cells individually programmed to one of the plurality of input data bits and the n states in the nonvolatile memory array; Subsequently reading the plurality of cells to obtain raw data, the reading step comprising analyzing more than n states per cell; Calculating a plurality of row probability values corresponding to input data bits and redundant data bits from the row data; A first plurality from a respective one of a first plurality of calculated probability values calculated from the plurality of row probability values, at least one row probability value corresponding to an input data bit and at least one row probability value corresponding to a redundant data bit Calculating the calculated probability values of; And Calculating a plurality of output data from the first plurality of calculated probability values Including, data storage and retrieval methods. 7. The method of claim 6, wherein calculating the plurality of output data bits comprises calculating a second plurality of calculated probability values from the first plurality of calculated probability values. 8. The method of claim 7, wherein the first plurality of calculated probability values and the second plurality of calculated probability values are calculated according to the steps in a turbo code that repeatedly calculates a plurality of probability values until predetermined conditions are met. Data storage and retrieval methods. 7. The method of claim 6, wherein the plurality of redundant data bits are generated by a Low Density Parity Check (LDPC) encoder. 7. The method of claim 6, further comprising performing a hard-input hard-output error correction code (ECC) on the plurality of output data bits. 12. The method of claim 10, comprising calculating a second plurality of probability values from the first plurality of probability values if the plurality of errors is greater than a threshold number that is the ECC operation. 11. The method of claim 10, comprising correcting errors in the plurality of output data bits if the ECC operation indicates a number of errors that are below the threshold. A method for reading and storing data in a nonvolatile memory array that stores at least two data of data per memory cell, the method comprising: Receiving a plurality of input data bits to be stored in the nonvolatile memory array; Calculating a plurality of redundant data bits from the plurality of input data bits; Storing the plurality of input data bits and the plurality of redundant data bits in a plurality of cells in the non-volatile memory, wherein the plurality of cells are in one of a first plurality of program states representing at least two bits per cell. Individually programmed; Thereafter, reading the plurality of cells to obtain row data, the reading step comprising: analyzing a second plurality of read states that are greater than the first number; And Subsequently, calculating an individual value of the plurality of row probability values corresponding to a plurality of row probability values, a single input data bit, or a single redundant data bit from the row data. Comprising, the method of reading and storing data. 14. The method of claim 13, wherein the plurality of row probability values are derived from a lookup table that individually correlates probabilities for each bit stored in a memory cell having row data from the memory cell. 14. The method of claim 13, wherein the plurality of input data bits and the plurality of redundant data bits are stored by programming the plurality of cells into threshold voltage ranges that individually represent two or more bits. 16. The method of claim 15, wherein the threshold voltage ranges are mapped to bits according to a gray code. 16. The method of claim 15, wherein the threshold voltage ranges are mapped to bits according to a binary encoding scheme. 14. The method of claim 13, wherein the reading is achieved by comparing the voltage from the cell with a predetermined pattern of reference voltages having higher density reference voltages outside of the threshold voltage range of a program state than at the center of the threshold voltage range. Method of reading and storing data. 14. The method of claim 13, wherein a plurality of calculated probability values are derived from the plurality of row probability values, at least one row probability value corresponding to an input data bit and at least one row probability value corresponding to a redundant data bit. And calculating a probability value that has been determined. 14. The method of claim 13, wherein a plurality of output data bits are calculated from the plurality of row probability values in accordance with a soft-input soft-output correction code. 21. The method of claim 20, wherein the error correction code is a turbo code. 21. The method of claim 20, wherein the error correction code is an LDPC code. A method for reading data from a nonvolatile memory array in which data is stored in memory cells that are programmed to threshold voltage ranges that individually correspond to memory cell states. A plurality of reads performed according to a predetermined pattern that provides a memory cell programmed to a threshold voltage range to provide higher density read operations for the first portion of the threshold voltage range than for the second portion of the threshold voltage range. Performing the operations; Deriving from said plurality of read operations at least one probability value representing a probability of a programmed bit in said memory cell having a particular logic state. And a data reading method. 24. The method of claim 23, wherein at least one probability value is derived from the plurality of read operations using a lookup table that provides individual probability values for each bit stored in a memory cell. 24. The method of claim 23, wherein a probability value providing a soft-input for a soft-input soft-output decoder is obtained for each bit stored in the plurality of memory cells. 27. The method of claim 25, further comprising passing output information from the soft-input soft-output decoder to a hard-input hard-output decoder that further performs error correction. A nonvolatile memory system, A memory array including a plurality of data and a plurality of parity bits calculated from the plurality of data bits in accordance with an encoding scheme; Read the plurality of cells and derive low probability values corresponding to the plurality of data bits and the plurality of parity bits; And A decoder for calculating output probability values using the row probability values and the encoding scheme. And a non-volatile memory system. 28. The non- volatile memory system of claim 27, wherein the demodulator analyzes a plurality of read states per cell that are greater than the plurality of program states used to program the plurality of cells. 28. The non- volatile memory system of claim 27, wherein the decoder then calculates additional probability values from the output probability values using the encoding scheme. 30. The non- volatile memory system of claim 29, wherein the decoder calculates additional probability values in two or more iterations performed until a predetermined condition is met. 31. The non- volatile memory system of claim 30, further comprising a hard-input hard-output decoder. 28. The non- volatile memory system of claim 27, wherein the encoding scheme uses turbo coding. 28. The non- volatile memory system of claim 27, wherein the encoding scheme uses low density parity check (LDPC) codes. 28. The non- volatile memory system of claim 27, further comprising a converter that converts a soft input into a hard output. A nonvolatile memory system, A nonvolatile memory array for storing two or more bits in a separate memory cell; A demodulator that derives an individual probability value for each of the two or more bits stored in the respective memory cell. And a non-volatile memory system. 36. The non- volatile memory system of claim 35, further comprising a lookup table used to obtain the respective probability values for the two or more respective bits. 36. The non- volatile memory system of claim 35, wherein the two or more bits comprise at least one parity bit added according to an encoding scheme. 36. The non- volatile memory system of claim 35, wherein the demodulator derives the individual probability values by reading the individual memory cell by analysis identifying more of the plurality of program states of the individual memory cell. 36. The non- volatile memory system of claim 35, further comprising a soft-input soft-output decoder that receives the individual probability values as input and calculates output probability values from the individual probability values. 36. The non- volatile memory system of claim 35, wherein the demodulator reads the individual memory cell using a predetermined pattern of read operations having at least one region of higher density and region of lower density. A nonvolatile memory system, An array of nonvolatile memory cells individually programmed into one of two or more threshold voltage ranges representing two or more states; Analyze the individual cell threshold voltage with the identified one of the two or more threshold voltage ranges, and determine a higher density of read operations for the first portion of the identified threshold voltage range than for the second portion of the identified threshold voltage range. Providing a demodulator that derives probability values from the read operations for the first and second portions further analyzing the respective cell threshold voltage within the identified threshold voltage range. And a non-volatile memory system. 42. The non- volatile memory system of claim 41, further comprising a soft-input soft-output decoder that receives the probability values as input. 43. The non- volatile memory system of claim 42, wherein the soft-input soft-output decoder calculates output probability values in multiple iterations until a predetermined condition is met. 44. The non- volatile memory system of claim 43, further comprising a soft-hard converter that converts the output probability values into hard output values when the predetermined condition is met. 44. The non- volatile memory system of claim 43, further comprising a hard-input hard-output decoder that determines when the predetermined conditions of receiving the output probability values from the soft-input soft-output decoder are met. 42. The non- volatile memory cell of claim 41, wherein the nonvolatile memory cells are individually programmed with four or more threshold voltage ranges representing the demodulator deriving four or more states and probable values for each of the two or more bits to store two or more bits. Nonvolatile memory system.

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