TWI385512B - Method of storing data and decoding data stored in a nonvolatile semiconductor memory array, nonvolatile semiconductor and flash memory systems, and method of managing data in flash memory - Google Patents

Description

Method for storing data and decoding stored data in a non-volatile semiconductor memory array, non-volatile semiconductor and flash memory system, and method for managing data in flash memory

This invention relates to non-volatile memory systems and to methods of operating non-volatile memory systems.

Non-volatile memory systems are used in a variety of applications. Some non-volatile memory systems are embedded in a larger system, such as a personal computer. Other non-volatile memory systems are removably connected to a host system and can be interchanged between different host systems. Examples of such removable memory systems include memory cards and USB flash drives. Electronic circuit cards including non-volatile memory cards have been implemented commercially in accordance with a number of well-known standards. Memory cards are used with personal computers, mobile phones, personal digital assistants (PDAs), digital still cameras, digital cameras, portable audio players, and other host electronic devices to store large amounts of data. Such cards typically include a reprogrammable non-volatile semiconductor memory cell array and a controller that controls and supports the operation of the memory cell array and interfaces with a host to which the card is connected. Several cards of the same type can be interchanged in a host card slot designed to accept this type of card. However, the development of many electronic card standards has produced different types of cards that are incompatible with each other to varying degrees. Cards manufactured in accordance with a standard are generally not available for use with a host designed to operate with another standard card. Memory card standards include PC cards, CompactFlash ^TM card (CF ^TM card), SmartMedia ^TM card, MultiMediaCard (MMC ^TM), secure digital (SD) card, miniSD ^TM card, subscriber identity module ^{(SIM), Memory Stick TM,} Memory Stick Duo card and microSD/TransFlash ^TM memory module standard. A number of USB flash drives with the trademark "Cruzer®" from SanDisk are commercially available. USB flash drives are typically larger and different in shape from the memory cards described above.

The data stored in a non-volatile memory system when reading data may contain error bits. Traditional methods of reconstructing corrupted data include applying an error correction code (ECC). When writing data into the memory system, a simple error correction code encodes the data by storing additional parity bits that set the parity of the bit group to a desired logical value. If the data is incorrect during storage, the parity of the bit group may change. After reading the data from the memory system, the isomorphism of the bit group is again calculated by the ECC. Because the data is corrupted, the calculated parity may not match the required co-location conditions, and the ECC can detect the damage.

The ECC can have at least two functions: debug and error correction. The capabilities of the various functions of these functions are typically measured in terms of the number of bits that can be detected as erroneous and subsequently corrected. The detection capability can be the same or greater than the correction capability. The number of error bits detectable by a typical ECC is higher than the number of error bits it can correct. A collection of data bits and parity bits is sometimes referred to as a word. An early example is the (7, 4) Hamming code, which is capable of detecting up to two errors per word (7 bits in this example) and is able to correct an error in the seven-bit word.

More complex ECC can correct more than one single error per word, but reconstructing data becomes more complex in computation. Conventions restore data at a probability that a small error recovery is acceptable. However, as the number of errors continues to increase, the chances of reliable data recovery are rapidly decreasing or additional hardware and/or performance phases. The associated costs become extremely high.

In a semiconductor memory device, including an EEPROM system, the data can be represented as the threshold voltage of the transistor. In general, different digital data storage values correspond to different voltage ranges. If for some reason the voltage level deviates from its preferred range during a read operation, an error will occur. This error can be detected by ECC and can be corrected in some cases.

An exemplary method of storing data in a non-volatile semiconductor memory array includes encoding a first portion of one of the data according to a first encoding scheme to obtain a first plurality of encoded data bits; Stored data bits are stored in a plurality of cells of the memory array, each of the plurality of cells including at least one of the first plurality of encoded data bits; and a second plurality of data bits Stored in a plurality of cells having the first plurality of encoded data bits, each of the plurality of cells including at least one of the second plurality of data bits, the second plurality of data bits not being based The first coding scheme is encoded.

Another exemplary method of decoding data stored in a non-volatile semiconductor memory array includes reading data stored in a plurality of cells, each cell of the plurality of cells including at least a first data bit and a a second data bit; using the read result to generate a plurality of first corrected data values corresponding to the plurality of first data bits, wherein the plurality of first corrected data values are obtained by the plurality of first data bits ECC correction of the element is generated; and subsequently using the read result and also using the plurality of first corrected data values to generate a plurality of second corrected data corresponding to the plurality of second data bits value.

An exemplary non-volatile semiconductor memory system includes: a memory array including a plurality of memory cells, each of which individually holds a first data bit of a first page and a second data of a second page a bit; and an ECC encoder that encodes the data of the first page according to a first encoding scheme before storing the plurality of cells without encoding the second encoding according to the first encoding scheme before storing the plurality of cells Page information.

Another exemplary non-volatile semiconductor memory system includes: a flash memory array that stores data in a plurality of cells, and a cell stores at least a first data bit and a first page of a first data page a second data bit; and an ECC decoding system that first decodes the first data page and then decodes the second data page using the decoded result of the first data page.

In many non-volatile memories, reading data from a memory array may be wrong. That is, individual bits of input data that are programmed into a memory array may be read later at a different logic value. Figure 1 shows the relationship between a physical parameter (threshold voltage V _T ) indicating the state of a memory cell and a logical value that the memory cell may be stylized. In this example, only two states are stored in the cell. Thus, the unit stores a data bit. A unit that is programmed to a logic 0 state typically has a threshold voltage that is higher than the unit in a logic 1 (unprogrammed) state. In an alternative, the logic 1 state is the unprogrammed state of the memory cells. The vertical axis of Figure 1 indicates the probability of reading a cell at any particular threshold voltage based on the desired threshold voltage distribution. A first probability function is displayed for cells stylized to logic 1 and a second probability function is displayed for cells stylized to logic 0. However, these functions have some degree of overlap between them. A different voltage V _D is used in reading such a unit. A cell having a threshold voltage below V _D is considered to be in state 1, and those cells having a threshold voltage above V _D are considered to be in state 0. As shown in Figure 1, this may not always be correct. Because of the overlap between functions, there is a non-zero probability that a memory cell that is programmed to a logic 1 state will read as having a threshold voltage greater than V _D and will be read as being in a logic 0 state. . Similarly, there is a non-zero probability that a memory cell that is stylized to a logic 0 state will be read as having a logic one state.

The overlap between functions occurs for a number of reasons, including physical defects in the memory array and subsequent stylization or read operations within the memory array that interfere with the programmed unit. Overlap may also occur due to the inability to maintain a large number of cells within a very tight threshold voltage range. Specific stylization techniques allow the function of the threshold voltage to be narrowed (with a smaller standard deviation). However, such stylization can take more time. In some memory systems, more than one bit is stored in a memory unit. In general, it is desirable to store as many bits as possible within a memory unit. In order to efficiently use the available threshold voltage range, the functions for adjacent states can be made to overlap significantly.

Non-volatile memory systems commonly employ ECC methods to overcome errors that occur in reading data from a memory array. Such methods generally rely on an encoding system to calculate from an input data to be stored in a memory array. Some extra ECC bits. Other ECC schemes can map input data to output data in a more sophisticated manner. These ECC bits are typically stored with the input data but can be stored separately. The input data is later read from the non-volatile memory along with the ECC bits and a decoder uses both the data and the ECC bits to check for any errors. In some cases, such ECC bits can also be used to identify an error bit. The error bit is then corrected by changing its state (from "0" to "1" or from "1" to "0"). Attaching an ECC bit to a data bit is not the only way to encode the data before storing it in a non-volatile memory. For example, the data bits can be encoded according to a scheme that provides the following transformations: 00 to 1111, 01 to 1100, 10 to 0011, and 11 to 0000.

FIG. 2 shows an example of input data stored in a memory system 200. The input data is first received by an ECC unit 201, which includes an encoder 203. The input data may be host material to be stored in the memory system 200 or may be data generated by a memory controller. The example of Figure 2 shows four input data bits 1001. Encoder 203 then calculates an ECC bit from the input data bits using an encoding scheme (1111). An example of a coding scheme is to generate ECC bits for the co-located bits of the selected data bit group.

Then, the input data bits and the ECC bits are transmitted to a modulation/demodulation unit 205, which includes a modulator 207. The modulator 207 converts the digital data transmitted by the ECC unit 201 into a form that is written into a memory array 209. In one aspect, the digital data is converted into a plurality of threshold voltage values in a plurality of memory cells. Thus, various circuits for converting digital data into one of the memory cells to store the threshold voltage can be considered to form a modulator. In the example of Figure 2, each memory cell can hold a data bit. Thus, each memory cell can have a threshold voltage in one of two ranges, one range representing a logical "1" state and the other range representing a logic "0" state, as shown in FIG. A memory cell storing a logic "1" state has a threshold voltage less than one of V _D (<V _D ) and a memory cell storing a logic "0" state having a threshold voltage greater than V _D (>V _D ). The unit can be programmed and verified to a nominal threshold voltage above V _D to at least initially ensure that there is a preferred spacing between units programmed to the two logic states.

The data can be stored in the memory array 209 for a certain period of time. During this time, various events may occur that cause a threshold voltage change in the memory cell. In particular, operations involving stylization and reading may require voltages to be applied to word lines and bit lines in a manner that affects one of the other previously stylized units. Such interference is especially prevalent in situations where the size of the device is reduced such that the interaction between adjacent units is more pronounced. The charge may also be lost over a longer period of time. Failure to maintain such data can also cause the data to change as it is read. Due to such changes, it is possible to read the data bits with a different state than the originally programmed data bits. In the example of FIG. 2, an input data bit 211 is read to have a threshold less than V _D (<V _D ), which initially has a threshold greater than V _D (>V _D ) when written. value.

The threshold voltage of the memory cell is converted into a data bit by one of the demodulation transformers 213 in the modulation/demodulation transformer unit 205. This is the reverse of the program executed by the modulator. The demodulation transformer 213 can include a sense amplifier that reads a voltage or current from one of the memory cells in the memory array 209 and derives the state of the cell from the read. In the example of FIG. 2, a memory cell having a threshold voltage less than V _D (<V _D ) provides a demodulated output "1" and a threshold voltage greater than V _D (>V _D ). The memory unit provides a demodulated output "0". This provides the output sequence 11011111 shown. The second bit 208 of this sequence is erroneous due to being stored in the memory array 209.

The output of the demodulator 213 is transmitted to one of the decoders 215 in the ECC unit 201. The decoder 215 determines whether there are any errors by the data bit and the ECC bit. If there is a small amount of error within the corrective ability of the code, the errors are corrected. If there are a large number of errors, they can be identified but not corrected if they are within the detection capabilities of the code. If the number of errors exceeds the detection capability of the code, the error cannot be detected or an error correction may be caused. In the example of Figure 2, the errors in the second bit are detected and corrected. This slave decoder 215 provides an output (1001) which is identical to the input sequence. The decoding of the memory system 200 is considered hard input hard output decoding because the decoder 215 receives only the data bits representing the input data bits and ECC bits, and the decoder 215 outputs a sequence of corrected data bits. Corresponds to the input data bit (or an output cannot be provided if the number of errors is too high).

3 and 4 show an alternative memory system for memory system 200. Figure 3 shows a similar function to the functions of Figure 1, where V _D =0 and the threshold voltage below V _D represents a logic 0 and the voltage above V _D represents a logic 1. Instead of displaying a single voltage V _{D ,} the threshold voltage is divided into two different ranges, where the threshold voltages are indicated by the actual number of voltages. The function corresponding to logic "1" is centered above 0 volts, while the function corresponding to logic "0" is centered below 0 volts.

4 shows a memory system 421 that uses a data storage procedure similar to the data storage program of the memory system 200 (using the same input data bits and ECC bits) with a different read procedure. Specifically, instead of simply determining whether a threshold voltage is above or below a certain value, the memory system 421 reads the threshold voltage as shown in FIG. It will be understood that it is not necessary to read the actual threshold voltage. Other unit operated components can be used to store and retrieve data (eg, current sensing). Voltage sensing is only used as an example. In general, the threshold voltage refers to a gate voltage at which a transistor is turned on. Figure 4 shows that a read occurs, which provides more detailed information than the previous examples. This can be seen as a read that has a higher resolution than the read of Figure 2 (and a resolution that exceeds the resolution for the stylized state). As in the previous example, the error occurred in the read data. Here, the reading corresponding to the second bit and the third bit is erroneous. The second and third byte logic "0" is stored by staging a cell to have a threshold voltage less than V _D , but the cells are read to have a threshold voltage of 0.05 volts and 0.10 volts. , which is higher than V _D (V _D =0 volts).

The original voltage read from the memory array 423 of FIG. 4 by a series of read operations is transferred to one of the modulation/demodulation unit 427 demodulation transformers 425. The raw voltages have a finite resolution as indicated by the resolution of the analog to digital conversion. Here, the original data is converted into probability data. In particular, the probability of converting each unit reading into a corresponding bit system of one or zero. The series of readings from the memory array (0.75, 0.05, 0.10, 0.15, 1.25, 1.0, 3.0, and 0.5 volts) not only indicate the unit State, and can also be used to provide a certain degree of certainty about the state. This can be expressed as a probability of staging a memory cell using a particular bit. Thus, readings near 0 volts provide a low probability value, while the farther away from 0 volts provides a higher probability value. The probability values shown are log probability ratios (explained in detail below). This provides a negative number for a unit in a logic 0 state and a positive value for a unit in a logic 1 state, the digital value indicating the probability of correctly identifying the state. The second probability value and the third probability value (0.1, 0.2) indicate a logical "1". The second and third values indicate a relatively low probability.

The probability value is passed to one of the decoders 429 in an ECC unit 431 (in some cases, obtaining the probability value from the original value can be considered to be performed within the decoder). The ECC unit 431 also includes an encoder 432. The decoder 429 performs a decoding operation on the probability value. This decoder can be viewed as a soft input decoder. In general, soft input refers to an input that includes some quality information about the data to be decoded. Providing additional information as a soft input generally allows a decoder to achieve better results. A decoder can perform a decoding calculation using a soft input to provide a calculated probability value as an output. This is considered a soft output and this decoder is considered a soft input soft output (SISO) decoder. This output can then be used again as input to the SISO decoder to repeat the decoding and improve the results. A SISO decoder can form part of a larger decoder that provides a hard output to another unit. SISO decoders generally provide better performance and in some cases provide better performance than hard input hard output decoding. In particular, for the same amount of additional items (the number of ECC bits), a SISO decoder can provide greater error correction capabilities. In order to efficiently use a SISO decoder, an appropriate encoding/decoding scheme can be implemented. And the demodulation system is adapted to efficiently obtain a soft input without undue complexity and without undue time for reading data from the memory array.

In one embodiment, a soft input for a SISO decoder is provided by reading data in a non-volatile memory array using a resolution that is used to program the memory. The state of the body is a greater number of states. Thus, data can be written by staging a memory cell to one of two threshold voltage ranges and then read by parsing three or more threshold voltage ranges. In general, the number of threshold voltage ranges for reading will be a multiple of the number of programmed threshold voltage ranges (eg, up to two times). However, this is not always the case.

An ECC unit can be formed as a dedicated circuit or this function can be performed by a firmware in a controller. In general, a controller is an application specific integrated circuit (ASIC) that has circuitry designed for a particular function (eg, ECC) and also has firmware to manage controller operation. Thus, an encoder/decoder can be formed by a combination of hardware and firmware in the memory controller. Alternatively, an encoder/decoder (ECC unit) can be located on the memory chip. The modulation/demodulation transformer units may be on a memory wafer, on a controller wafer, on a separate wafer or some combination. In general, a modulation/demodulation unit will include at least some components of the memory chip (e.g., peripheral circuits connected to a memory array). Although Figure 4 indicates that the threshold voltage is read to a high resolution (an analog reading), the degree of resolution selected may depend on several factors, including the type of non-volatile memory used.

Figure 5 shows a more detailed view of ECC unit 431 (especially decoder 429). The decoder 429 includes a SISO decoder 532 and a soft and hard converter 534. The SISO decoder typically accepts raw probability data and performs an ECC calculation on the original probability data to provide computational probability data. The calculated probability data can be viewed as a soft output. In many cases, such a soft output is then provided as one of the inputs to the SISO decoder such that a second decoding iterative process is performed. A SISO decoder can perform a continuous iterative process until at least a predetermined condition is obtained. For example, a predetermined condition may be that all bits have a probability greater than a certain minimum. A predetermined condition may also be a set of one of the probability values (eg, an average probability value). A predetermined condition may converge from the result of a repetitive process to the next iterative process (i.e., the repetitive process is maintained until there is little improvement from the additional repetitive process). A predetermined condition may be to complete a predetermined number of iterations. A combination of these conditions can also be used. The decoding is performed using one of the code patterns in the material, which is the result of the encoding performed on the data by the encoder 432 prior to storing the data. Both encoder 432 and decoder 429 are considered part of ECC unit 431.

Efficient decoding depends on having an appropriate encoding/decoding scheme. Various schemes are known for encoding data in a manner suitable for subsequent decoding in a SISO decoder (e.g., SISO decoder 532). Encoding/decoding schemes include, but are not limited to, turbo codes, product codes, BCH codes, Reed-Solomon codes, and convolutional codes (see U.S. Patent Application Serial Nos. 11/383,401 and No. 11/383,405). Hamming code and low density parity check (LDPC) code. A detailed description of how LDPC codes and turbo codes can be used with SISO decoding is provided on September 28, 2006, entitled "Soft Input Soft Output Decoders for Non-Volatile Memory" and "Non-Volatile Memory The method of soft input soft output decoding is described in U.S. Patent Application Serial Nos. 11/536,286 and 11/536,327.

In some cases, statistics may be collected regarding corrections implemented by an ECC decoder. Such statistics can be used to adjust the operational parameters of a memory array. Non-volatile memory systems with adjusted operating parameters and methods for adjusting such parameters are described in U.S. Patent Application Serial Nos. 11/536,347 and 11/536,372, filed on Sep. 28, 2006.

In some memory arrays, individual memory cells maintain more than one data bit. Such multi-level cell (MLC) memory maps data bits to memory states. For example, in a flash memory, more than two data bits can be mapped to a memory state, each state having an assigned threshold voltage range. Figure 6 shows an example in which three data bits are stored in a memory unit. These three data bits require eight ( ²³ ) different memory states. In general, data is programmed into an MLC unit on a page-by-page basis, where each element in a unit comes from a different page. Thus, in Figure 6, the lowest bit 636 (least significant bit or LSB) is in one page, the middle bit 638 is in another page and the highest bit 640 (most significant bit or MSB) is in another page. in. The mapping of bit to memory states can be based on any convenient scheme.

Figure 7A shows an example of mapping the threshold voltage of a memory cell to sixteen different memory states S0 through S15 to store four data bits. Unlike the example of Figure 6, the bit map here is mapped to the memory state such that the LSB differs for neighboring states. Other bits are also different between adjacent states. In an example, the LSB is first decoded and used to decode higher bits. because The LSB of a particular memory state is different from its neighbors, so it is decided that the LSB helps resolve between adjacent states.

Figure 7B shows the difference voltage Vreadn between adjacent memory states S5 (1010) and S6 (1001). Additional read voltages V1 through V6 are used to provide additional resolution within memory states S5 and S6. Figure 7B shows four different threshold voltage readings A through D for four readings of the cell threshold voltage. Such readings can be used to provide a soft input for soft input decoding. Adjacent states S5 and S6 differ in both of the two least significant bits. Where a unit is read to have a particular threshold voltage, this indicates four bits. However, if there is an error in the read voltage such that the read voltage corresponds to another state, more than one bit (four in this example) may be erroneous and may require correction. In some cases, each page is separately subjected to ECC correction, and each error bit requires separation correction such that a single misread state may require four errors to be corrected separately.

In an alternative method of correcting stored data, the one-bit correction can provide information for subsequent corrections for other bits stored in the same unit. For example, a cell can be read to have a threshold voltage reading B that indicates the memory state S5 (1010) such that the LSB (first bit) will be zero and the next bit will be one. When an ECC correction is performed on the LSB (eg, performing a correction on a page containing the LSB), the ECC correction may indicate that the LEB is one. Given that B is close to Vreadn and the LSB is 1, the stylized state is likely to be S6 (1001). This indicates that the second bit may be 0 instead of 1. Thus, the result of the ECC correction performed on the LSB indicates one of the possible values of the second bit. Based on the threshold voltage of the cell alone, the second bit is erroneously determined to be one. Of course However, the ECC corrected LSB indicates that the second bit is likely to be zero. Additional information about the second bit can be provided to the ECC decoder that determines the second bit. This additional information may allow for decoding of a higher number of erroneous data or may allow for decoding with a smaller number of redundant bits. Similarly, the result of decoding the second bit can be used to decode a third bit and higher.

In an example, where a unit contains more than one data bit, a first bit (and other coded bits in other units) is first decoded and the result of the decoding is used to provide for at least one subsequent bit. One indication. In one arrangement, a high degree of certainty is used to correct a first bit and the result of the correction is used to determine additional bits in the unit. Different redundancy levels can be used to encode the data in different pages so that at least one page can be corrected even if it contains a large number of errors. Once a first page is corrected, the results can be used to correct additional pages stored in the same unit. These extra pages do not necessarily require the same redundancy level because the correction of the first data page provides additional information about the bits of the extra page. The scheme of Figures 7A and 7B shows that one of the bit-to-memory states is suitable for mapping such that decoding the LSB provides information for decoding higher bits.

Figure 8A shows the sixteen memory states S0 through S15 of Figure 7A mapped to four bits 842, 844, 846 and 848 of a memory cell. The four bits are 842, 844, 846, and 848 from four different pages (pages 0 through 3), respectively. The memory cell can be read by determining its threshold voltage using a particular resolution. For example, the threshold voltage can be within a threshold voltage range indicating that the memory state is S7. In some cases, some chance information A certain probability information is also obtained during the reading as described above. Information read from page 0 of the unit and other units is passed to an ECC decoder (e.g., a SISO decoder), wherein a first ECC operation produces corrected data bits corresponding to the LSBs of the units. For example, it can be determined that the LSB 842 is 1, so the state S7 is incorrect. This information can be used to decode higher bits 844, 846, and 848.

Since the LSB is 1, all memory states having a 0 as the LSB 842 can be eliminated from the decision to determine the second bit, as shown in Fig. 8B. This means that the remaining eight states (S0, S2, S4, S6, S8, S10, S12, S14) can be considered to have a larger tolerance than the initial sixteen states S0 to S15 (expandable mapping to the remaining state) The threshold voltage range is in the range that occupies the eliminated state). The threshold voltage of the cell can be compared to the extended threshold voltage range of the remaining state. This provides a higher chance of achieving a correct result due to increased tolerance. Thus, the threshold voltage reading of the previously indicated state S7 can now indicate state S8 because S7 is eliminated. A second ECC operation generates a corrected data bit for the bit of page 1. This second ECC operation benefits from the result of the first ECC operation on the bit of page 0 such that it may not require the same high redundancy level. In the example of FIG. 8B, the bit 844 of page 1 stored in the cell is determined to be 1 by ECC decoding. This is used to determine the next bit 846.

Figure 8C shows the remaining states (S0, S4, S8, S12) when it is determined that the two least significant bits 842 and 844 are one. Since the specific state is eliminated, the tolerance is increased for the remaining state. For example, a threshold voltage reading corresponding to S7 would indicate S8, assuming that S5 to S7 are eliminated at this point. Thus, solution The results of the two least significant bits 842 and 844 of the code provide information to help obtain the next bit 846. Decoding is performed based on the increased margin and 1 is obtained for bit 846 of page 2.

Fig. 8D shows the remaining state (S0, S8) when the bit 846 of the decision page 2 is set to 1. It can be seen that the remaining states (S0 to S8) have a wide tolerance which allows the MSB 848 to be determined at a higher probability. Next, the result of this decision is decoded to obtain a correction value for one of the MSBs 848. For example, where the threshold voltage indicates state S7, given the remaining state, S8 is the most likely state and MSB 848 is most likely to be zero.

The above examples may be implemented using soft input or hard input for this first ECC decoding operation. Subsequent ECC operations receive soft input because both the data received from reading the memory unit and the data from earlier ECC decoding are considered in the ECC decoding. In one example, a memory unit is read using a resolution that resolves the stylized memory state and is also parsed within the stylized memory states to provide for storage in the memory unit. The probability value of the bit. In this example, the probability value corresponding to the higher bit can be adjusted according to the result of decoding the lower bit. This provides another way to use the result of a first ECC decoding operation in a second ECC decoding operation. Adjusting the tolerance for the remaining state or adjusting the probability for the remaining bits is a different technique for incorporating the decision to decode a lower bit of information into a higher bit.

Figure 9A shows an example of a portion of a soft input memory system 950 that provides ECC correction for a subsequent page using ECC correction of a first page. A memory array 952 includes eight memory cells C0 to C7, each record The memory unit stores four data bits, one element from each of the four pages P0 to P3. The data stored in pages P0 to P3 is encoded prior to storage. In particular, the data in P0 is encoded so that it can be decoded separately.

A demodulation transformer 954 is coupled to the memory array and an output of the demodulation transformer is provided as an input 955 to an ECC decoder 956. The demodulation transformer 956 can include suitable read circuitry to determine the threshold voltage of the individual memory cells using at least sufficient resolution to identify a stylized memory state. The output of the demodulation transformer 954 is provided for a first ECC decoding module ECC0. The output of the demodulator 954 can be an indicator of a bit (hard input), a probability value (soft input), a threshold voltage, or other state of the memory cell. ECC0 decodes the data stored in page P0. This can be hard input hard output decoding or SISO decoding. In general, SISO decoding provides better results. Module ECC0 provides correction data P0', which may be a set of probability values or correction bits associated with the bits stored in page P0. The correction data P0' is used to provide a first output O/P ₀ from the ECC decoder 956, i.e., decoded data from page P0. The output O can be generated by performing a soft-to-hard transition (if P0' is a soft output) and also stripping any redundant data bits added as part of the encoded data before storing the data in the memory array 952. /P ₀ .

The calibration data P0' is provided as input to one of the second ECC modules ECC1, which decodes the data stored in the page P1. The module ECC1 receives the correction data P0' generated by ECC0 and also receives an input 958 from the demodulation transformer 954. Input 958 from the demodulation transformer 954 can be a set of probability values or based on reading a bit of the memory array 952. The combination of the corrected P0' data and the demodulation transformer input 958 can be considered to form a soft input to the module ECC1. For example, ECC0 provides a hard output with a bit of 1 on the suggestion page P1 but input 958 from the demodulation transformer 954 suggests that the bit is 0, which may be combined to provide a low of 1 or 0. Probability. Where both ECC0 and input 958 from the demodulation transformer 954 are suggested to be 1, these may be combined to a high probability of one. Where probability values are provided, they may be combined in a suitable manner (e.g., by an average probability value). The ECC module ECC1 performs decoding based on the combination of input from ECC0 and input 958 from the demodulation transformer 954 to provide correction data P1'. The correction data P1' can be used to provide an output O/P ₁ (decoded data from page P1) which removes one of the redundant data bits. The correction data P1' is also supplied to another ECC module (ECC2).

The ECC module ECC2 receives P1' and also receives input 960 from the demodulation transformer 954 and performs ECC decoding on the combination of such inputs to provide correction data P2' as previously described. The correction data P2' can be used to provide an output O/P ₂ (decoded data from page P2) which removes one of the redundant data bits from the hard output. Next, the calibration data P2' is passed to the ECC module ECC3, where it is combined with the input 962 from the demodulation transformer 954 to determine the calibration data P3', which corresponds to the data stored in page P3. The correction data P3' can be used to provide an output O/P ₃ (decoded data from page P3) which removes one of the redundant data bits.

The ECC modules ECC1 to ECC3 may be of any suitable type and may use similar coding schemes or different coding schemes. ECC1 can accept a hard input or a soft input and can use hard input hard output decoding, SISO decoding or other techniques To implement decoding. Each of the ECC modules ECC1 to ECC3 receives two inputs, each of which can be a soft input or a hard input. Even if both inputs are hard inputs, they can still be considered as providing a soft input in combination.

In other examples, pages can be encoded and decoded together. For example, a first page and a second page can be decoded together. Subsequently, a third page and a fourth page can be read and the results of decoding the first and second pages can be used to decode the third and fourth pages.

FIG. 9B shows a first example of an ECC module 964 that may be used for one of the ECC modules ECC1 through ECC3. Two inputs 966, 968 are provided to the ECC module 964, and one input 968 is provided by a demodulator to reflect data read from a memory array and another input provided by a previous ECC module. 968 decodes another material stored in the same memory unit. The two inputs 966, 968 are provided to a combination circuit 970 that produces a single output 972 based on the two inputs 966, 968. For example, an increased tolerance can be provided by a prior ECC module and a threshold voltage can be provided by a demodulation transformer. These are combined in the combining circuit 970 to provide a soft output. Where a demodulator provides a probability value, the probability values from the demodulation transformer and the previous ECC module can be combined to provide a combined value, that is, an average of the probability values. The hard input can be combined by assigning a high probability that the two hard inputs are the same and assigning a low probability to the difference between the two hard inputs. The combinational circuit 970 can use a lookup table or other suitable component to provide an output that depends on one of the two inputs. Next, the soft output 972 generated by the combining circuit is transmitted to a SISO decoder 974, which performs one or more iterative processes to determine the output probability value (or output bit, if performing soft to hard Conversion).

Figure 9C shows an alternative ECC module 976 having a combination circuit 978 that combines input 978 from one of the demodulators with input 980 from one of the other ECC modules to provide a soft output 982, such as As mentioned before. In this case, the soft output 982 is then converted to a hard output 984 by a soft to hard converter 986 (the largest possible bit is provided as the output). The hard output 984 is then provided to a hard input hard output (HIHO) decoder 988 that decodes the data to provide correction data. Alternatively, combining and soft to hard conversions can be performed together, for example using a lookup table that provides one of the hard output values for different input values (hard or soft).

The decoder module ECC0 receives only one input 955 (from the demodulation transformer), which can be a soft or a hard input and the decoder ECC0 can produce a soft or a hard output. For example, module ECC0 can be formed similar to decoder 429 of FIG. ECC0 to ECC3 can be as shown in FIG. 9B or FIG. 9C. The ECC modules ECC0 through ECC1 may be formed as separate circuits or may be formed as a single circuit configured to perform continuous ECC operations. In one example, the ECC modules are formed as part of a controller ASIC.

As described above, separate decoding steps can be used to decode different pages. The result of decoding a first page is provided to aid in decoding a second page. The result of decoding the second page can be provided to help decode a third page and the like. To achieve separate decoding of pages, each page can be encoded separately. By decoding the additional information provided by the first page, decoding of the second page can be performed using fewer redundant bits. According to an example, different numbers of ECC bits are provided for different pages. A large number of redundant bits can be provided for a first page to allow for a large number of errors positive. Because of the wider tolerance (or higher probability) associated with the bits of the second page due to decoding of the first page, a smaller amount of redundant bits can be provided for a second page. Different coding schemes with different degrees of redundancy can be used for different pages. In general, the addressable unit for a memory system is a segment. In one example, a segment is stored such that it extends over one page of an MLC memory. Different ECC schemes using a different number of redundant bits can be used for different pages of the same segment.

Figure 10 shows eight segments (segments 0 through 7) stored in a cell such that the individual cells contain four bits (bit 0 to bit 3) of a single segment. Sections 0 through 7 are stylized together as four pages corresponding to bits 0 through 3. Where the bit system is assigned to the memory state as shown in FIG. 7A, it can be expected that page 0 will be read as having a large number of errors, page 1 has fewer errors than page 0, and page 2 has fewer errors than page 1. Page 3 has fewer errors than page 2. This is because the greater the tolerance (or probability) for the higher the page. This means that the more error corrections may be needed for lower pages, especially page 0. The coding scheme used, including the amount of redundant data, can be selected accordingly. The term "page" is generally used to mean a stylized unit in a memory array. An MLC scheme can be used to store multiple pages in the same unit. In the particular example presented herein, all pages stored together in a group of cells are read together and no individual reads of one page are performed. Thus, the minimum read unit for this system can consist of multiple pages. It will be understood that the term "page" means a stylized group of bits that are in the same validity across a group of cells, rather than a group of bits that are read together as a unit in a particular memory system. .

Figure 11A shows an extension across four pages (pages 0 to 3) and includes two different encodings An example of a section 1190 of one of the scenarios. The data in pages 0 and 1 is encoded using an LDPC encoding scheme that produces redundant data bits 1192. This material can be decoded using SISO decoding, which allows for a large number of erroneous corrections. The data in pages 2 and 3 are not encoded using an LDPC code. However, the pages 2 through 3 are encoded using a BCH code that provides redundant data bits 1194. The BCH code can also be used to encode the data of pages 0 to 1, or the BCH code can be limited to pages 2 to 3. Where the BCH code covers pages 0 to 1, the data of pages 0 to 4 is first encoded according to the BCH code, and then the pages 0 to 1 are further encoded according to the LDPC code. Later, LDPC is first used to decode the data in pages 0 through 1, and then BCH is used to decode pages 0 through 4.

FIG. 11B shows another example of encoding a sector 1195 of page 0 based on only one LDPC code, so only page 0 contains redundant LDPC generation bits 1196. Higher pages 1 through 3 are encoded using a BCH code that uses the BCH to generate redundant bits 1198. The BCH code can be extended to cover page 0 in addition to pages 1 to 3, or can only cover pages 1 to 3. Thus, page 0 is encoded in accordance with an encoding scheme that is not used for one of the other pages.

Figure 11C shows another example of a different coding scheme for one of the pages 1 to 99 of each page 0 to 3. Generating redundant data ECC _A for page 0 according to a first coding scheme, generating redundant data ECC _B for page 1 according to a second coding scheme, and generating redundant data ECC _C for page 2 according to a third coding scheme and according to one The fourth coding scheme generates redundant data ECC _D for page 3. Page 0 has more redundant material ECC _A than the other pages, so that page 0 is first decoded and used to provide information for decoding other pages. The coding scheme for different pages may be of the same type (eg, all LDPC schemes) or different types (eg, LDPC and BCH schemes). The same type of scheme can be considered as different schemes when it uses different amounts of redundant data. In some cases, higher page encoding schemes can also cover lower pages. Thus, the ECCB can cover pages 0 and 1 such that the pages are decoded along with the second encoding scheme. The ECCC may cover pages 0 through 2 such that the pages are decoded together according to the third encoding scheme and the like. Such pages must also be coded together.

Although the examples of Figures 11A through 11C show that redundant data is separated from other data, in other aspects uncoded data can be mapped to encoded data in a more sophisticated manner as previously described. The number of extra bits used to encode the data compared to the uncoded material can be considered as the number of redundant bits, even where there are no detachably identified redundant bits. Header information 1101 is displayed on page 3 of the above example. However, header information can also be provided in other locations.

Figure 12 shows an example of a memory system 1203 using one of different coding schemes for different pages. In particular, the memory system displays an encoder 1205 that applies LDPC encoding to certain data and applies BCH encoding to other data (in other examples, BCH encoding is applied to all data and LDPC encoding is applied only to some Some information). The encoded data is then passed to a modulator 1207 which stores the data in a memory array 1208. In particular, the modulator 1207 stores the LDPC encoded data in a first page and stores the BCH encoded data in a higher page in the same memory unit. The modulator maps the data bits to the memory state according to a suitable scheme (such as the scheme of FIG. 7A), so that a first bit (one bit in the first page) is replaced from one memory state to the next. Memory status.

The data is read and extracted from the memory array by a demodulator 1209. It is supplied to a decoder 1211 which performs LDPC decoding on the material from page 0 and performs BCH decoding on the material from other pages. An output 1213 from LDPC decoder 1215 is provided to the BCH decoder 1217 such that the BCH decoder 1217 can use the correction by the LDPC decoder 1215 to assist in performing BCH decoding. There may also be some sort of output from a BCH decoding operation followed by a BCH decoding operation.

In some cases, the output from a BCH decoder is also fed back to the LDPC decoder for LDPC decoding. For example, LDPC decoding may be repeated decoding, which performs a number of iterative processes and then provides an output to the BCH decoder. If the BCH decoder is unable to correct the provided data, it can return a signal to the LDPC decoder to indicate that more iterative processes should be performed.

13 shows a memory system 1319 including an encoder 1321 that encodes a first data in a first encoder 1323 in accordance with a first encoding scheme and a second encoder 1325 in accordance with a second encoding scheme. The second data is encoded, and the first and second data are programmed by a modulator 1329 to share the cells in the memory array 1327. The data is read from the memory array 1327 by a demodulation transformer 1331 and decoded by the decoder 1333. According to the first scheme, the read data corresponding to the first data is decoded in a first decoder 1335, and the read data corresponding to the second data is decoded in a second decoder 1337 according to the second scheme. The output 1339 from the first decoder 1335 is provided to the second decoder 1337 such that the result of decoding the first data can be used to decode the second material. Similarly, an output 1341 from the second decoder 1337 is provided to the first decoder 1335 such that the second decoding can be performed. The result of the data is used to decode the first data. Thus, the first decoder 1335 interacts with the second decoder 1337 to collectively decode the material. The first and second coding schemes may be LDPC schemes, which in one example have different amounts of redundant data. In another example, the first coding scheme is an LDPC scheme and the second coding scheme is a BCH scheme.

The various examples above refer to flash memory. However, various other non-volatile memory are currently in use and the techniques described herein are applicable to any suitable non-volatile memory system. Such memory systems may include, but are not limited to, ferroelectric memory (FRAM or FeRAM) based memory systems, magnetoresistive memory (MRAM) based memory systems, and phase change based (PRAM or "OUM" ( "phase change memory")) memory.

All patents, patent applications, articles, books, descriptions, other publications, documents, and articles herein are hereby incorporated by reference in their entirety for all purposes. In the event of any inconsistency or conflict between the definition or use of a term between any incorporated publication, document or thing and the body of this document, the definition or use of that term in this document shall prevail.

While the invention has been described with respect to the preferred embodiments thereof, it will be understood that

200‧‧‧ memory system

201‧‧‧ECC unit

203‧‧‧Encoder

205‧‧‧Modulation/demodulation unit

207‧‧‧ modulator

208‧‧‧ second bit

209‧‧‧ memory array

211‧‧‧Input data bits

213‧‧‧Demodulation Transducer

215‧‧‧Decoder

421‧‧‧ memory system

423‧‧‧ memory array

425‧‧‧Demodulation Transducer

427‧‧‧Modulation/demodulation unit

429‧‧‧Decoder

431‧‧‧ECC unit

432‧‧‧Encoder

532‧‧SISO decoder

534‧‧‧Soft and hard converters

636‧‧‧ Lowest bit

638‧‧‧ intermediate bits

640‧‧‧ highest bit

842‧‧‧ bits/LSB

844‧‧‧ bits

846‧‧ ‧ bits

848‧‧‧ bits/MSB

950‧‧‧ memory system

952‧‧‧ memory array

954‧‧‧Demodulation Transducer

955‧‧‧Enter

956‧‧‧ECC decoder

958‧‧‧Enter

960‧‧‧Enter

962‧‧‧Enter

964‧‧‧ECC module

966‧‧‧Enter

968‧‧‧Enter

970‧‧‧Combined circuit

972‧‧‧ output

974‧‧‧SISO decoder

976‧‧‧ECC module

978‧‧‧Combined circuit

980‧‧‧Enter

982‧‧‧Soft output

984‧‧‧hard output

986‧‧‧Soft to hard converter

988‧‧‧hard input hard output (HIHO) decoder

Section 1190‧‧‧

1192‧‧‧Redundant data bits

1194‧‧‧Redundant data bits

Section 1195‧‧

1196‧‧‧Redundant LDPC generating bits

1198‧‧‧BCH generates redundant bits

Section 1199‧‧

1203‧‧‧Memory System

1205‧‧‧Encoder

1207‧‧‧ modulator

1208‧‧‧Memory array

1209‧‧‧Demodulation transformer

1211‧‧‧Decoder

1213‧‧‧ Output

1215‧‧‧LDPC decoder

1217‧‧‧BCH decoder

1319‧‧‧ memory system

1321‧‧‧Encoder

1323‧‧‧First encoder

1325‧‧‧Second encoder

1327‧‧‧Memory array

1329‧‧‧Transformer

1331‧‧‧Demodulation Transducer

1333‧‧‧Decoder

1335‧‧‧First decoder

1337‧‧‧Second decoder

1339‧‧‧ Output

1341‧‧‧ Output

Figure 1 shows the probability function of the threshold voltage of a unit programmed into a logic 1 state and a logic 0 state in a non-volatile memory, including a voltage V _D for distinguishing between a logic 1 and a logic 0 state.

Figure 2 shows a component of a memory system including a memory array, Modulator/demodulator circuit and encoder/decoder circuit.

Figure 3 shows the probability function of the read threshold voltage of a unit programmed to a logic 1 state and a logic 0 state, showing the threshold voltage value.

4 shows a component of a memory system including a memory array, a modulator/demodulator circuit, and an encoder/decoder circuit, a demodulator providing a probability value to a decoder.

Figure 5 shows an ECC unit with a soft input soft output (SISO) decoder.

Figure 6 shows the threshold voltage range for storing one of the three data bits and showing how the three bit fields map to eight memory states.

Figure 7A shows the threshold voltage range for storing one of the four data bits and showing how the three bit fields map to sixteen memory states such that the least significant bits of the adjacent states are different.

Figure 7B shows an example of a voltage used to read the memory cell of Figure 7A to provide a soft input for ECC decoding.

Figure 8A shows the sixteen memory states of a memory cell considered in determining a first bit (LSB).

Figure 8B shows the eight remaining memory states of the memory cells considered in determining a second bit, the other eight states being eliminated due to ECC decoding of the first bit.

Figure 8C shows the four remaining memory states of the memory cells considered in determining a third bit, the additional four states being eliminated due to ECC decoding of the second bit.

Figure 8D shows two of the memory cells considered in determining a fourth bit. The remaining memory state, the other two states are eliminated due to the ECC decoding of the third bit.

9A shows a portion of a memory system including an ECC decoder having one of four ECC modules for decoding four data pages, which is transmitted from the output of the decoded page to a subsequent decoding module, where it is used for decoding. A data page.

Figure 9B shows an example of a decoding module that can be used in the memory system of Figure 9A.

Figure 9C shows another example of a decoding module that can be used in the memory system of Figure 9A.

Figure 10 shows how a data section can be stored in a memory array such that one sector is stored using bits in each of the four pages.

Figure 11A shows an example of a section stored in four pages, two pages encoded using LDPC encoding and the other two pages encoded using BCH encoding.

Figure 11B shows an example of a section stored in four pages, one page encoded using LDPC encoding and the other three pages encoded using BCH encoding.

Figure 11C shows an example of a section stored in four pages, each page being encoded to have a different amount of redundant data.

Figure 12 shows a memory system having an encoder that encodes certain data in accordance with a BCH code and encodes other data using an LDPC code, the memory system having a decoder that decodes and provides LDPC encoded data. One of the LDPC decoding outputs is used to decode the BCH encoded material.

Figure 13 shows the encoding of different parts of the data stored in the same memory unit according to two different coding schemes before storing the data in memory. Another memory system of the segment, which is decoded using two decoders for the two schemes, and one output from each decoder is provided to the other decoder.

1319‧‧‧ memory system

1321‧‧‧Encoder

1323‧‧‧First encoder

1325‧‧‧Second encoder

1327‧‧‧Memory array

1329‧‧‧Transformer

1331‧‧‧Demodulation Transducer

1333‧‧‧Decoder

1335‧‧‧First decoder

1337‧‧‧Second decoder

1339‧‧‧ Output

1341‧‧‧ Output

Claims (43)

A method of storing data in a non-volatile semiconductor memory array, the method comprising: encoding a first portion of a data according to a first encoding scheme to obtain a first plurality of encoded data bits; The encoded data bits are stored in a plurality of cells of the memory array, each of the plurality of cells including at least one of the first plurality of encoded data bits; and storing the second plurality of data bits And in the plurality of cells having the same plurality of encoded data bits, each of the plurality of cells includes at least one of the second plurality of data bits and the first plurality of encoded data At least one of the bits, the second plurality of data bits are not encoded according to the first coding scheme. The method of claim 1, wherein the second plurality of data bits are encoded according to a second coding scheme. The method of claim 2, wherein the first coding scheme uses more redundant bits than the second coding scheme. The method of claim 1, wherein the first coding scheme is a low density parity check (LDPC) scheme. The method of claim 1, further comprising reading the plurality of memory cells and providing the read data to an ECC decoder. The method of claim 5, wherein the read data is provided to the ECC decoder as a soft input, which performs soft input soft output decoding. The method of claim 6, wherein the first plurality of encoded codes are first decoded The data bit and the decoded result of the first plurality of data bits are used to decode the second plurality of data bits. A method of decoding data stored in a non-volatile semiconductor memory array, comprising: reading data stored in a plurality of cells, each cell of the plurality of cells including at least one first data bit and a first Using the result of the reading to generate a plurality of first corrected data values corresponding to the plurality of first data bits, wherein the plurality of first corrected data values are obtained by the plurality of first corrected data values ECC correction of the data bit is generated; and subsequently using the result of the reading and also using the plurality of first corrected data values to generate a plurality of second corrected data values corresponding to the plurality of second data bits. The method of claim 8, wherein the plurality of second corrected data values are generated using soft input soft output decoding, and the plurality of first corrected data values provide portions of the soft input. The method of claim 8, wherein the plurality of second corrected data values are generated using a second encoding scheme that uses fewer redundant bits than the first encoding scheme. The method of claim 8, wherein the plurality of first data bits are formed as a unit to be programmed and read as a first page, and the plurality of second data bits are formed as a unit. And read one of the second pages. A method of decoding a material of claim 8, wherein the reading provides a first original probability value associated with the first data bit and providing the same The second original probability value associated with the two data bits. The method of claim 12, wherein the first raw probability values are provided as soft inputs for generating the plurality of first corrected data values and subsequently generating the second probability values, and the plurality of first corrected data The value is provided as a soft input for generating the plurality of second corrected data values. A method for managing data in a flash memory, comprising: encoding a first portion of a data according to a first encoding scheme, and storing the first portion of the encoded data in one of a plurality of cells Encoding a second portion of the data according to a second encoding scheme, and storing the second portion of the encoded data in a second page of the same plurality of cells; subsequently reading the same complex number Units for obtaining read data; decoding the read data according to the first encoding scheme to obtain a first portion of the data; and subsequently decoding the read data according to the second encoding scheme to obtain a second portion of the data The decoding according to the second coding scheme uses one of the decodings according to the first coding scheme. The method of claim 14, wherein the first coding scheme is a low density parity check (LDPC) scheme. The method of claim 14, wherein the second encoding scheme uses fewer redundant bits than the first encoding scheme. The method of claim 14, wherein the decoding according to the second scheme is soft input soft output decoding, which uses the decoding according to the first coding scheme The output is used as a soft input. The method of claim 14, wherein the plurality of cells further comprises at least a third page. The method of claim 14, wherein the host addressable section of the data comprises a first portion of the material and a second portion of the material. The method of claim 14, wherein the first portion of the data includes data for a first host addressable segment and further includes information for a second host addressable segment. The method of claim 14, further comprising encoding the first portion of the data along with the second portion of the data in accordance with the second encoding scheme prior to encoding the first portion of the material in accordance with the first encoding scheme. The method of claim 21, wherein the first portion of the data and the second portion of the data are decoded together in accordance with the decoding of the second encoding scheme. The method of claim 14, further comprising additional decoding in accordance with the first encoding scheme, the additional decoding output using one of the decodings in accordance with the second scheme. A non-volatile semiconductor memory system includes: a memory array including a plurality of memory cells, each of the plurality of memory cells individually holding a first data bit of a first page and a second data bit of a second page; and an ECC encoder that encodes the data of the first page according to a first encoding scheme before being stored in the same plurality of cells, and is not stored in The same information of the second page is previously encoded in the same plurality of units according to the first coding scheme. The flash memory system of claim 24, wherein the data of the second page is encoded according to a second encoding scheme. A flash memory system as claimed in claim 25, wherein the first encoding scheme uses more redundant bits than the second encoding scheme. The flash memory system of claim 24, wherein the first encoding scheme is a low density parity check (LDPC) scheme. The flash memory system of claim 24, further comprising: a read circuit that reads data from the plurality of memory cells; and an ECC decoder that decodes the read data. The flash memory system of claim 28, wherein the read data is provided as a soft input to the ECC decoder, which first decodes the data of the first page and outputs one of the decodings of the first page using The read data decodes the data of the second page together. The flash memory system of claim 24, wherein the first page includes data for a segment and the second page includes data for the segment. A non-volatile semiconductor memory system includes: a flash memory array storing data in a plurality of cells, and a cell storing at least a first data bit and a second of a first data page One of the data pages is a second data bit; and an ECC decoding system that first decodes the first data page and then decodes the second data page using the decoded result of the first data page. The non-volatile semiconductor memory system of claim 31, wherein the ECC decoding system comprises a soft input soft output decoder that uses the first page The results of the decoding and the data read from the plurality of cells serve as a soft input. The non-volatile semiconductor memory system of claim 31, wherein the data stored in the first page is encoded according to a first encoding scheme, and the data stored in the second page is not based on the first encoding scheme To code. The non-volatile semiconductor memory system of claim 33, wherein the data stored in the second page is encoded according to a second encoding scheme. The non-volatile semiconductor memory system of claim 31, further comprising a read circuit that reads the plurality of cells to provide a probability value for transmission to the ECC decoding system. A flash memory system, comprising: a flash memory array, wherein at least one first data page and one second data page are stored in a plurality of cells, each unit of the plurality of cells including the first page One of the first bit and the second bit of the second page; an encoder that encodes the data of the first page according to a first encoding scheme and encodes the first encoding according to a second encoding scheme Two pages of data; a read circuit that reads the plurality of cells and provides probability values associated with individual bits stored in the plurality of cells; and a soft input soft output ECC decoder that receives from The probability value of the read circuit is to decode the first data page, and the second data page is decoded using the decoded result of the first data page. The flash memory system of claim 36, wherein the first encoding scheme is a low density parity check (LDPC) scheme. A flash memory system as in claim 36, wherein the second encoding scheme uses fewer redundant bits than the first encoding scheme. A flash memory system as in claim 36, wherein the plurality of cells comprises at least a third page. In the flash memory system of claim 36, wherein a single host addressable section extends over the first page and the second page. The flash memory system of claim 36, wherein the encoder encodes the material of the first page in accordance with the second encoding scheme prior to encoding the material of the first page in accordance with the first encoding scheme. The flash memory system of claim 41, wherein the decoder uses the second encoding scheme to decode the second material page and the first material page together. The flash memory system of claim 36, wherein the soft input soft output ECC decoder decodes the first data page using the decoded result of the second data page.