TW200823666A - Soft-input soft-output decoder for nonvolatile memory - Google Patents

Abstract

In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Description

200823666 IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory system and a method of operating a non-volatile memory system. [Prior Art] Non-volatile memory systems are used in a variety of applications. Some non-volatile memory systems are embedded in a larger system, such as a personal computer. Other non-volatile memory systems are removably connected to a host system and can be interchanged between different host systems. Examples of such removable memory systems include memory cards and USB flash drives. Electronic circuit cards containing non-volatile memory cards have been commercially implemented in accordance with a number of well-known standards. Memory cards are used with personal computers, cellular phones, personal digital assistants (PDAs), digital still cameras, digital cameras, portable audio players, and other host electronics to store large amounts of data. Such a card typically includes a reprogrammable non-volatile 1x half-V body c memory cell array and a controller that controls and supports the operation of the memory cell array and interfaces with the card Host. Several cards of the same type can be interchanged in a host card slot designed to accommodate this type of card. However, the development of many electronic card standards has established different types of cards that are incompatible with each other to varying degrees. Cards manufactured according to a standard are generally not available for a host designed to operate with another standard card. The card standard includes PC card, CompactFlashTM card (CFTM card), SmartMediaTM card, multimedia card (MMCTM), secure digital (sd) card, miniSDTM card, user identity module (SIM), Memory StickTM, Memory. Stick Duo card and microSD/TransFlashTM memory module standard 124726.doc 200823666 A number of USB flash drives with the trademark "Certer8" from SanDisk are available on the market. USB flash drives are generally larger and different in shape from the above memory cards. Data stored in a non-volatile memory system may contain error bits when reading data. Traditional methods of reconstructing corrupted data include applying the error _ correction code (ECC). A simple error when writing data to a memory system • The weighted code encodes data by storing additional parity bits that set the parity of multiple bit groups to a desired logical value. If the data is incorrect during storage, the parity of multiple bit groups may change. When reading data from the memory system, the co-location of the bit group is again calculated by ecc. Because the data is corrupted, the calculated parity may not match the required parity condition' and the ECC can detect the damage. The ECC can have at least two functions: error detection and error correction. The capabilities of the various functions of these functions are generally measured by the number of bits that can be detected as erroneous and subsequently corrected. The detection capability can be the same or greater than the correction capability. • The typical ECC detectable error bit is reduced by more than the number of correctable error bits. A collection of data bits and parity bits is sometimes referred to as a character. An early example (7, 4) Hamming code that can detect up to two errors per character (in this case, 7 bits in the example) and can correct a mistake in such a seven-bit character. . More complex ECC can correct more than one error per character, but the reconstruction data becomes computationally complex. The convention is to reply to a message with a probability of receiving a small error. However, as the number of errors continues to increase, the chances of reliable data recovery are rapidly decreasing or the associated hardware and/or performance correlations become extremely high. In semiconductor memory devices, including EEPROM systems, the data can be used as a threshold voltage for the transistor. In general, different digital data storage values correspond to different voltage ranges. If for some reason, the voltage level deviates from its programmed range before or during the read operation, an error will occur. This error can be detected by the ECC and can be corrected in some cases. SUMMARY OF THE INVENTION A non-volatile memory array is coupled to a decoder such that encoded data from the delta-feet array is used to calculate a probability value associated with a bit stored in the memory array. Meta-associated. An example of such a decoder is a soft input soft output (SIS0) decoder. The encoded data can be read using a high resolution indicating the probability associated with a data bit, not only the logical value of the data bit. For example, in the case of encoding a binary material in a memory to +1/-1 volt, the Ecc decoder can use actual voltage reading instead of just symbols. Probability values can be derived from self-read values or other sources. The probability value can be provided as a soft input to an SIS〇 decoder. The output of the SISO decoder can be converted to a hard output by a converter. This hard output represents the correction value. In some cases, a SIS0 decoder may perform computations using multiple iterations until certain predetermined conditions are met. In a non-volatile memory, a high-resolution read can be achieved by selecting an appropriate voltage for an individual 5-step acquisition step such that a higher density occurs for one particular portion of a particular threshold voltage function than for another portion. Read to get. This is for extra resolution for areas of interest, such as where the threshold voltage function has significant overlap. 124726.doc 200823666 In a non-volatile domain towel, demodulation (4) can convert the voltage from the -memory = column into a probability value. In the case where more than one (4) is stored in the - unit, a separate probability value can be obtained for each element value. This probability value can be used as a soft input to a SISO decoder. [Embodiment] In many non-volatile memories, reading data from a memory array may be wrong. That is, individual bits of the wheeled data that are programmed into a memory array may be read later at a different logical value. Figure i shows the relationship between the physical parameter (premise ντ) indicating the state of a memory cell and the logical value that the memory cell may be stylized. In this example, only the two states are stored in the unit. Thus, the unit stores one bit of metadata. A unit that is programmed to a logic 0 state typically has a threshold voltage that is higher than the unit in a logic 1 (unprogrammed) state. In an alternative, the logic 1 state is the unprogrammed state of the memory cells. The vertical axis of Figure 1 indicates the probability of reading a cell at any particular threshold voltage based on the desired threshold voltage distribution. A first probability function is used to display units for programming to logic 1 and a second is used for programming to logic units. However, there is some degree of overlap between these functions. A different voltage VD is used in reading such a unit. A cell having a threshold voltage below Vd is considered to be in state 1, and such cells having a threshold voltage above VD are considered to be in state. As shown in Figure 1, this may not always be correct. Because of the overlap between functions, there is a non-zero probability that one of the memory cells is programmed to have a threshold voltage greater than vD, so it is read as a logic state. Similarly, there is a non-zero probability that 124726.doc -9-200823666 will be - stylized into a logical unit. The memory unit is read as having a logical j state. The overlap between functions occurs for a number of reasons, including physical defects in the memory array and the effects of stylized or read operations within the memory array on the programmed cells. Overlaps may also occur due to the inability to maintain a large number of cells in a very tight threshold voltage range. Specific stylization techniques allow the threshold voltage function to be narrowed (with a smaller standard deviation). However, such stylization can take more time. In some memory systems, more than one bit is stored in a memory unit. In general, it is desirable to store as many bits as possible within a memory cell. In order to use the available threshold voltage range efficiently, the functions for adjacent states may cause significant overlap. Non-volatile memory systems commonly employ ECC methods to overcome errors that occur in reading data from a memory array. Such methods generally rely on an encoding system to calculate certain additional ECC bits from input data to be stored in a memory array. Other ECC schemes can be used to map input data to output data in more complex ways. The (iv) c-bits are generally stored with the input data or can be stored separately. The input data and the ECC bit are read from the non-volatile memory and a σ, decoding, and the ECC bit are used to check whether the existence exists, and the ± 仃 仃 is wrong. In some cases, such ECC bits can also be used to identify the _屮-error bit. The error bit is then corrected by changing its state (from "0) to 11 or from "丨" to "〇"). Attaching the ECC bit to the slanting 仞-, "$ 枓 70 Asia and Africa is used to store data in the non-volatile memory before encoding. For example, the data can be encoded according to an I24726.doc 200823666 scheme. The bit, the scheme provides the following transformations: 〇〇 to ij, 01 to 1100, 10 to ooiuu to (10) (10).

Figure 2 shows an example of storing input data in a memory system 2 (10). The input data is first received by an ECC: unit 2〇1, which includes an encoder 203. The input data may be host data stored in the memory system 2 or may be data generated by a memory controller. The example of Figure 2 shows four input data bits 1001. Encoder 203 then uses an encoding scheme to calculate ECC bits (1 j 丨 i) from the input data bits. The coding scheme example produces ECC bits that are used for the co-located bits of the selected data bit group. The input data bits and the ECC bits are then sent to a modulation/demodulation variable 2 〇 5 ′ which includes a modulator. The meter converts the digital data transmitted by the C unit 201 into a form, and the digital data is written into a memory array 2〇9 in this form. In one embodiment, the digital data is converted into a plurality of threshold voltage values in a plurality of memory cells. Because of this, various circuits for converting digital data into a storage threshold voltage in the _memory unit can be regarded as forming-modulation (4). In the example of Figure 2, each memory cell holds _bit data. Therefore, each of the minds can have a threshold voltage in one of the two ranges. One range of hearts = reverse series 1 and the other range specifies a logical "〇" state, as shown in the figure 1 is shown. Storing a logic, 〗 〖, 铒 之 memory unit has a threshold voltage lower than Vd (<Vd), and left, puts a memory unit in the state of storage Has a threshold voltage of -large ^Vd(>Vd). The unit can be programmed and verified to a nominal threshold voltage above ^ to ensure that there is at least a preferred interval between the units that are stylized to the 124726.doc -11-200823666, etc.: logic state. The fund can be stored in the memory column 209 for a continuous period of time _ time period may occur

In particular, the operations involving stylization and reading may require the addition of power to the sub- and line lines to affect other previously stylized units. Such interference is particularly frequent in the case where the size of the device is reduced such that the interaction between adjacent units is more pronounced. The charge may also be lost over a longer period of time. Failure to maintain such data can also cause data to change as it is read. Since such a change 'is likely to read the data bit, it has a different state than the originally stylized data bit. In the example of Figure 2, an input data bit 2U is read to have a threshold less than Vd (<Vd), and initially its write has a threshold greater than VD (>VD). . The threshold voltages of the memory cells are converted into data bits by a demodulator 213 in the modulation/demodulation transform unit 205. This is a reversal of the program performed by the modulator. Demodulation transformer 213 can include a sense amplifier that reads a voltage or current from a memory cell within memory array 209 and derives the state of the cell from the capture. In the example of FIG. 2, a memory cell having a threshold voltage less than VD (<VD) provides a demodulated output πιπ and a memory having a threshold voltage greater than vD (>vD) The unit provides a demodulated output "〇. This provides the output sequence JJ 〇i J jii shown. The second bit 208 of this sequence is corrupted by being stored in the memory array 209. Demodulation 213 The output is sent to a decoder 215 in the ECC unit 201. The decoder 215 determines if there are any errors based on the data bit and the ECC bit. If there is a small error in the range of correction capabilities of the code 124726.doc - 12- 200823666 Mistakes, people are wrong. If there are a large number of errors, you can identify the error 1, the law correction, if the errors are within the ability of the coding system: Error: the number exceeds the detection of the drink Capability, it is impossible to make such a mistake = Ge may cause - error correction. In the example of Figure 2, the error in the second is measured and corrected. This provides an output from the decoder 215 (?01) # Equivalent to the input sequence. The decoding of the memory system is considered Input hard output Charm ', a solution of horses because the decoder 215 receives only the input represents

The bit, the bit and the data bit of the ECC bit, and the decoder 215 outputs a corrected post-poor bit sequence corresponding to the rounded data bit (or an output cannot be provided if the number of errors is too high). Figures 3 and 4 show an alternative memory system of the memory system. Figure 3 shows a function similar to the functions of Figure 1, where VD = 〇, 6_limit voltage below VD indicates logic 〇 and voltage above % indicates logic 1. Substituting f = single voltage ¥ 划分 divides the threshold voltage into two different ranges, where the threshold voltages are indicated by the actual voltage number. The function corresponding to the logic T is centered above G volts and corresponds to logic, and the function of τ is centered below 〇V. A memory system 421 is illustrated, which is similar to the memory system's shell/material storage program (using the same input data bits and ECC bits), and - does not read the program. In particular, instead of simple Determining whether a threshold voltage exceeds or falls below a certain value, the memory system 421 reads the threshold voltage as shown in Figure 3. It should be understood that the actual threshold voltage is not necessarily read. Other unit operating members may be used for storage. And to retrieve data (such as current sensing). The voltage sensing system is only used as an example. In general, the threshold voltage system 124726.doc -13 - 200823666 refers to a gate voltage of a transistor connected. Figure 4 shows a reading The occurrence occurs, which provides more detailed information than the previous example. This can be seen as a read that has a more south resolution than the read of Figure 2 (and a resolution that exceeds the resolution for the stylized state). In the previous example, the error occurred in the read data. Here, the readings corresponding to the second and third digits are incorrect. The second and third digits are logical "〇" Unit a unit to have a smaller than VD The voltage is stored, but the cells are read to have a threshold voltage of 0.05 volts and 〇·ι〇 volts, which is higher than Vd (Vd==〇伏特卜 is taken from the memory array 423 of FIG. 4 by the series of items. The original voltage read is sent to a demodulation transformer 425 within a modulation/demodulation transformer circuit. The original voltages have a finite resolution dominated by the resolution of the analog to digital conversion. Here, The raw data is converted into probability data. In particular, the probability of converting each unit reading into a corresponding bit system 1 or 0. The series of readings from the memory array (〇·75, 〇〇5, 〇1〇) , 〇·=, 1,25, ^, 3·0, and 0·5 volts) not only indicates the state of the unit, but can also be used to provide a degree of certainty about the unit. This can be expressed as a specific bit program used in the past. One probability of a memory cell is thus made. Thus, readings near 0 volts provide a lower probability value, while readings away from 0 volts provide a higher probability value. The probability values shown are log probability ratios (explained in detail below). This is provided for the unit in the -logic state The number provides a positive number for a unit in a logical 1 state, and the numerical size indicates the probability of correctly identifying the state. The second and third probability values (〇1, 〇·2) indicate logic "" The third value indicates a relatively low probability. The probability value is sent to a decoder (4) within the -ECC unit 431 124726.doc -14- 200823666 (in some cases, obtaining the probability value from the original value can be considered as Decoder 429 performs decoding operations on probability values. Such a decoder can be considered a soft input decoder. In general, soft input refers to an input that includes certain qualities about the data to be decoded. Information. Additional information used as a soft input generally results in a better result for a decoder. A decoder can perform a decoding calculation using a soft input to provide a calculated probability value as an output. This is considered a soft output and such a decoder is considered a soft input soft input.

Out (siso) decoder. This output can then be used again as input to the SIS〇 decoder to iterate the decoding and improve the results. An SIS 〇 decoder can form part of a larger decoder that provides a hard output to another single το. SISO decoders generally provide better performance and in some cases provide 2 hard input hard output decoding for better performance. In particular, for an additional burden of the same number 1 (number of ECC bits), a SIS〇 decoder can provide a larger split-layer positive target force. In order to use a decoder efficiently, it is also possible to adapt the field, flat code/decoding scheme and modulation system to efficiently obtain a soft input without excessive complexity and without excessive time for the memory array. Read the data. In a specific embodiment, the soft input 1 for the -SISO decoder is used to read data in a non-volatile memory array; the resolution is parsed compared to the past poetry. The state; the number of sorrows. It is possible to program a memory cell to a voltage limit and then analyze it by three

The voltage range comes to the fin & A w . In general, the threshold voltage for reading is used for several times the number of voltage limits for the program (eg, 3 124726.doc -15·200823666 times). However, this is not always the case. An encoder/decoder circuit (ECC unit) can be formed as a dedicated circuit or this function can be performed by a firmware within a controller. One 而 temple and $ ’ one control

on. In general, a modulation circuit will include at least some components on a memory chip (e.g., peripheral circuits connected to a memory array). Although Figure * indicates that the threshold voltage is read to a high resolution (a class of readouts, the degree of resolution chosen may depend on several factors, including the type of non-volatile memory used. An integrated circuit (ASIC) having circuitry designed for a particular function (such as ECC) and also having firmware to manage controller operation, = and an encoder/decoder can be controlled by a memory A combination of hardware and firmware is formed. The modulator/demodulator circuit may be on a memory chip i, on a controller wafer, on a separate wafer: a group: Figure 5 shows that one is undergoing One of the NAND flash memory arrays of the read operation is a string 541. A NAND flash memory system consists of a series of connected memory cell strings, and is formed by a selection transistor, collectively referred to as a block (ie, substantially erased) Unit group isolation. A reads the selected unit, the other units of the string are turned on, so that the current of the string is dependent on the selected unit. The appropriate bias voltage is placed at either end of the string 541 (generally One end of the condition is connected to the ground The string selects the gates of the electrical bodies 543, 545 and one or more voltages are sequentially applied to the word lines extending on the I unit. For a single unit that holds one bit of data, only one A single voltage. For a unit that maintains more than one bit (an align unit or MLC), a voltage sequence is generally composed of a sequential incremental voltage step P or a binary lookup pattern. Each step corresponds to a different power 124726.doc - 16 - 200823666

Pressure. A cell string storing two bits requires four states and one cell of three bits and eight states. A sense amplifier 547 attached to a bit line determines the time the cell is turned on and the word line voltage that caused the switching first refers to the threshold voltage range. The resolution of this read operation depends on the number of voltage steps provided. For example, a single bit read requires milliseconds to complete a sensing operation, while one bit reading for the same memory requires 75 milliseconds to complete three sensing operations to fully resolve the four states. More voltage steps provide a more south resolution, but this requires more time. Less voltage steps increase speed but provide worse resolution. In general, the read operation is performed using the same resolution as used to perform the stylized operation. Thus, if a stylized operation is programmed and the unit is verified to have four states, the refill operation has sufficient resolution to resolve the four threshold voltage ranges. This may require three voltage steps for a unit having four possible states. Various NAND flash § 己 体 system structures and methods of operating the nand flash memory system are described in U.S. Patents 7,888,621, 7,092,290 and 6,983,428. in. Figure 6A shows an example of a -single-bit memory cell that uses a higher resolution read that exceeds the state for programming the number of states of the memory. As previously mentioned, the horizontal axis indicates the threshold voltage (Vt) and the vertical axis indicates that the unit has the probability of having this threshold voltage for a particular programmed state. In the sample towel of ®1, f performs a single read to determine if a cell is programmed to be in a two-state. Below ^, three reads are performed here to determine if the cell is within the four read threshold voltage range of 65 丨 to 654. Thus the unit is programmed to one of the two threshold voltage ranges (corresponding to 124726.doc -17-200823666 two logic states) and later read using a resolution that identifies the unit as four Within one of the threshold voltage ranges (four read states), the voltages V!, v2, and v3 selected for reading are made such that the four threshold voltage ranges 651 to 654 are different in size and the reading system is concentrated in These two functions (for logic 1 and logic 〇) are placed near the overlap position. A read (at a different voltage V2) is similar to the reading of Figure 1 and indicates the state (〇 or 1) of the memory cell. The other two reads (at 乂1 and 卩3) are within the threshold voltage range of logic 〇 and logic 1, but are not centered within the threshold voltage range. Conversely, these reads are configured closer to V2. The four read threshold voltage ranges 65 1 through 654 indicate the probability that a particular read bit is correct. Thus, for a logic 〇, a reading below the threshold voltage range 651) has a higher correct probability' and a reading between ▽1 and 乂2 (the threshold voltage range 652) has a lower correct probability . For Logic 1, a reading between V2 and V3 (preceding voltage range 653) has a relatively low correct probability, while a reading that exceeds the threshold voltage range 654) has a higher correct probability. It can be seen that using a resolution that resolves a higher number of states than the number of states used by the stylization to perform a fetch allows a fetch operation to obtain probabilistic information about the data being read. Figure 6B shows an example of a two-bit Mlc memory cell that uses a high resolution for reading, which resolves more than the number of stylized states. Figure 6B shows that a series of read operations are being performed using incremental resolution. During the read 1, the threshold voltage of the unit is resolved into one of four sorrows, which corresponds to a less than vi, between Vi and V2, between v72 and V3 124726.doc -18 - 200823666 And a threshold voltage greater than Vs. This first read resolves the same number of states as the number of previously used stylized states. A second read read 2 is performed to provide a higher resolution. Read 2 resolves a stylized state (eg, "1〇) into three read states corresponding to a central portion of the threshold voltage function (between Vs and V6) and the threshold voltage function The second external part (one between % and Vs and the other between Vs and V2). A third read read 3 is executed to provide higher resolution. Read 3 parsing read 2 Reading the state so that the external portion is further parsed. In this example, the read state corresponding to the central portion is not further resolved. The read operations may take a read 丨, then 4 take 2, then take the order of 3 or Any other order is performed. Or the 'individual reading steps can be performed in some other order to combine them in a single one. For example, the reading step can start from the lowest threshold voltage and according to the threshold voltage. The reading steps are sequentially performed. The reading steps of reading 读取, reading 2, and reading 3 are arranged in a pattern, and the outer portion of the threshold voltage function for a particular stylized state corresponds to a central portion. The part has a higher read operation density. This provides more information about the outer portion of the threshold voltage function than the central portion of such a function. This is because a unit with a threshold voltage in a central portion of a threshold voltage function can be assumed for a particular state. There is a higher probability in this state (the probability in another state is close to zero), so no more resolution is needed. The outer part of a particular function may overlap an adjacent function. More on such overlapping areas is needed. Information (where the probability value changes). 3 The above description is about the specific technique used to read the N AND flash memory unit. Other reading techniques can also be used. In some memories, a 124726.doc -19- 200823666 The reading step can provide information about the stylized level of the body, for example, in the first name, one (10) of the flash memory, and the state of a memory unit in the memory. It can be read using: =: meta-measurement current. In this case, the ^ mirror is used to replicate the current from the cell, which can then be compared with several parallel reference currents. Thus, available - One step to perform a high-resolution read. When: *7' how to get from - store more than one bit of the data phase = information t guide the probability value of the individual bit. In this case, individual "Value system ^ is sent to you. Figure 7 shows the probability function for the four states 11 : 10, 〇〇, 01) of Figure 6. Figure 7 also shows a probability of spanning all four threshold voltage ranges for the first bit π (leftmost bit). Here, the probability system is displayed as a special bit, and the probability, the probability can also be provided according to a π system ''G'. The display-probability level has the same level of _ ̄ ^. There is a greater probability of 〇, because the two states on the left "11" and "ίο" have a τ as the first epoch, and the probability on the left side of the graph is higher (>0). The two states on the right "〇〇" and "〇1 " have one "." as the first bit, so on the side of the second: (four)). Figure 7 also shows The second bit (the rightmost bit) spans a probability of all four threshold voltage ranges. This probability is 杈咼 at either end of the threshold voltage range and is lower in the middle. Thus, for the two bits The probability value of the element has a very different pattern. Figure 7 shows a threshold voltage 乂1, which provides a first bit probability P1 and a second bit probability P2. Here 'P1 is larger because of the threshold voltage The VI is not close to a threshold voltage that has a "〇" as the state of the first bit. However, the P2 system is smaller because ¥1 is close to the state of 124726.doc -20 - 200823666 Limit voltage range. This indication is approximately (4) in this bit, and the probability is slightly higher than the probability that it is 0. Figure 7 shows that the probability of different bits stored in the same cell may be extremely unclear. Restricted electric dust in an overlapping area between the threshold voltage ranges of adjacent states And thus having an increased risk of misreading, a different bit can still have a very high probability value, wherein the overlap is between the two states of the individual bit at the same time and thus the more useful one by one bit The probability is determined non-unit by unit. The demodulation transformer can use the correlation between the threshold voltage and the individual bit probability values (such as the probability values shown in Figure 7) to provide the original based on the readings from the memory array. Probability value. In the case of "read operation identification" for a threshold voltage range of a unit, the probability value for each element may be associated with each such range. The probability 値 can be derived from various information (for example, for a given Determining the behavioral characteristics of a technical memory unit) or deriving from the experience of a particular memory device. In the case of _, WT, and push, the probability value can be changed at different stages during the life of a device. It can be expressed in different ways. The common way to express the binary data is the log-to-log probability ratio (llr). The (10) associated with a particular bit is for a particular reading X, the bit system "i" The logarithm of the ratio of the probability of the disk element system "0". Thus: LLR(x)=l〇g P{dQ\x) where = the handle is the bit system "i, and the probability is Ρ( “0μ) is the rate of the bit system, 〇”. The LLR is a convenient way to express the 农 农 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Obtain probability information in the reading of the body, generally 124726.doc

-2K 200823666 Perform some conversion or demodulation changes. A convenient way to perform such demodulation is to use a lookup table that maps the relationship between the threshold voltage (or a measured parameter in memory) and the probability value of one or more bits. In the case where the resolution of the read operation divides the threshold voltage range of a memory cell into N read states and the cell stores R bits, a table may have NXR items so that each read state is provided. A probability is used for each element. In this way, a high-resolution read can provide probabilistic information about the information stored in the memory. Such raw probability data can be provided to a decoder as one of the soft inputs of the decoding 1 §. Figure 8 shows that a soft input data such as that described above is supplied to a decoder system 861 that includes a SIS0 decoder 863. The SIS〇 decoder typically accepts the original probability data and performs an ECC calculation on the original probability data to provide a calculated probability data. The calculated probability data can be viewed as a soft output. In many cases, such a soft output is then provided as one of the inputs to the SIS 〇 decoder such that a second decoding iteration is performed. An SIS 〇 decoder can perform successive iterations until at least a predetermined condition is obtained. For example, a predetermined condition may be that all of the bits have a probability greater than a certain minimum. The predetermined condition may also be a total of a probability value (e.g., an intermediate probability value). A predetermined condition may converge from the outcome of an iteration to the next iteration (i.e., iteratively maintained until there is little improvement due to additional iterations). A predetermined condition may be to complete a predetermined number of iterations. Combinations of these conditions can also be used. The decoding is performed using a coding pattern within the data, which is the result of the encoding performed by the encoder 865 on the data before the data is stored. The encoder ^^ and the eliminator system 861 are simultaneously considered part of the ECC unit 867, which may be implemented in a memory system (such as the memory system 42 1) (ECC unit 867) One can be used as an example of a unit of the ECC unit 431). Various encoding schemes can be used with a SISO decoder. The decoder 861 also includes a hard and soft converter 864 for converting a soft output from the SISO decoder 865 into a hard output. In some cases, SISO decoding provides better error correction for the same amount of management data than hard input hard output decoding. Figure 9 shows an exemplary coding scheme that can be used with a SISO decoder (such as SIS 〇 decoder 863). The data item D"-D33 is configured in columns and rows, and the parity bits are calculated for each column and row. For example, P! is calculated from the inclusion of items Dn, 〇12, and D13. Similarly, p2 is calculated from the inclusion of items ΐ2ΐ, ;〇22 and 1>23. P4 calculates its own Dn, D21 and D23. Figure 1 shows the result of the later decoding of the encoded material as shown in Figure 9 in both a hard input hard output decoder and a SISO decoder. In this example, the two logical states of the one-ary system are expressed as +1 and not 〇, respectively. It will be appreciated that any suitable notation may be used and that this representation is only for convenience. For this example, for a soft number, the symbol indicates whether the bit is most likely to be 0 or 1 and the numerical size indicates the probability that this is the correct value. A signal 101 is shown as a one-bit group comprising data bits and co-located bits, which are calculated in accordance with the encoding scheme of FIG. The signal is typically an output of an encoder having appropriate circuitry to calculate the parity bits. The signal can be sent to a modulator that provides the appropriate voltage to the memory unit to program the memory cells to a state to record the signal data. 124726.doc -23- 200823666 In this example it is shown that the noise l〇3 is affecting the two data bits. The noise is not limited to data bits and may also affect the parity bits. The noise may be caused by some physical characteristics of a particular unit or interference that may occur in memory when a unit is affected by operations performed on other units in the array. In this example, the 'noise' is considered as additional, so that the data read from the memory unit reflects the signal data plus the noise, which then becomes the input data for the solution. However, noise may affect the read value either positively or negatively. Xin Input 105 is the original data obtained from a demodulator connected to a memory. For example, in the case where a read operation is performed using a high resolution, the input data is generated in such a form that the signal or the parity of the one-bit element is expressed as 0·1 instead of 1 or 〇. This can be viewed as a probability value with a positive value indicating 1 and a negative value indicating 0, the value size indicating the probability that the indicated state is correct. Input 105 can be considered a soft input because it includes multiple simple 〇 or 1 values. For a hard input hard output decoder, input 1〇5 is converted to hard input 107 by replacing all positive values with +1 and all negative values with -1. In a system in which a j-complement (1's complement) logic represents a soft input probability value, the most significant bit represents a symbol and can be used as a transforming component. The hard input hard output _ 胄 coder may attempt to use this hard input to correct the data. However, the parity meter - counts an error in each of the second and third columns and an _ error in each of the second = third rows. There are no unique answers in this situation, as d22 and d33 may go wrong or d32 and D23 may go wrong. The hard input hard output detector cannot determine which of the answers is correct. Therefore, a hard input hard wheel out decoder cannot correct the 124726.doc -24- 200823666 data in this case. In the - face-to-face decoding step, the soft input correction data (10) is generated for the first column from the input. The items of the soft input correction data 109 are calculated from the sign of the product of the other items on the same column and the size of the smallest item in the column (the probability value calculation is explained in more detail below). This indicates the original appearance of the item indicated by other items in the column and can be considered as a calculated probability or - extrinsic probability (relative to the intrinsic probability of the input). Soft input correction poor material 109 is then added to input 1〇5 to obtain a soft output 111 of the first column iteration. The soft output lu of the first column iteration thus combines the intrinsic and extrinsic probability values. The soft output reflects the intrinsic probability information from the original data and the probabilistic information derived from other items that are derived from the same co-located bits in the same column. At this point, the symbol of soft output 113 (convert soft output to a hard output) is displayed to show that the data is completely corrected. Thus, the soft input soft output decoding can correct this data in the absence of a hard input hard output decoder. In addition, the soft input soft output decoder can be squared using an iteration using only column parity calculations. If the correction is not completed, a row parity calculation can be used to perform further calculations. If such a first row iteration does not provide a full correction, then a second column iteration can be performed. Thus, a SISO can continue to work toward a solution if a hard input decoder stops and does not find a solution. A second example is shown in Figure 11. As in the previous example, the parity bit is calculated for both the column and the row of the array input data (in this example, only two input data items per column or row). Here, the parity bit is calculated as the modulus 2 sum of the input data bits of the column or row. Figure 12 shows a decoder 124 in the ECC unit 123 receiving the wheel 124726.doc -25-200823666, which calculates the equivalent bit and appends it to the data. In this case, the four-bit co-located data is attached to the four-bit input data. The input data and the parity bits thus form encoded signal data which is sent to a modulator 125. The modulator 125 programs the individual memory cells based on the signal data. In this case, the two-bit system is stored in one of the memory cells of the memory array 126, so the signal data of the eight bits is stored in four cells, and the cells have individual threshold voltage levels. V4. The memory cells are then read to have a threshold voltage range νι, to V4'. The read threshold voltage ranges are demodulated in a demodulator 127 to provide raw probability data (1.5, 1. 〇, 〇.2, 〇.3, 2 5, 2.0, 6.0, 1.0). . This can be obtained using a lookup table or other means. In some cases, providing the raw probability data is considered a function within a decoder, but for this case it is considered to occur within the demodulation transformer 127. An original probability value is obtained for each element, so that even if the bits are stored in the same unit, they may have different probability values. In this example, demodulator 127 provides a probability value as a log probability ratio, but the probability can also be expressed in other formats. These original probability values are positive for all data items, indicating that in the case of obtaining a hard output directly from those items, all data items are considered i at this time (assuming a second error). However, using a SISO decoder 129 within the ECC unit 123, the data can be completely corrected. Figures 13A through 13D show how the SISO decoder 129 corrects the input data. The decoder 129 is a specific example of a SISO decoder that can be used in a memory system such as the memory system 421 (the decoder 129 can be used as the decoder 429). Figure 13A shows that the first horizontal iteration uses the column symbol ΐ3ι to obtain the first calculated probability value 133 from the column value 124726.doc -26-200823666 rate value 132. In this case, llr is added to obtain a calculated probability value 133. It can be shown that the sum of the two LLRs in this example is provided by multiplying the products of the two LLRs by (.m) by the minimum llr value. LLR(Dl)©LLR(D2)«(.l) x sgn[LLR(Dl)] x sgn[LLR(D2)] χ min[LLR(Dl)5 LLR(D2)] where ten indicates LLR addition. Applying this LLR to these items provides the calculated probability values shown. For example, the calculation probability system 〇·ιφ2.5 ～0·1 ′ corresponding to the item corresponds to the calculation probability of the D12 item, which is 1. 5 + 2.51 L5. The calculated (external) probability value 133 is then added to the original (intrinsic) probability value 132 from which the output probability value 135 is obtained. Therefore, the output probability value corresponding to the item D" is the original probability value of 1.5 plus the calculated probability value, giving 1.4. It can be seen that the output probability value 135 of the top column (14, _14) refers to a relatively high probability value, indicating that the correct bit systems are 1 and 〇. However, the probability value 135 on the bottom column (-0.1, 〇·1) indicates that the bits are the lower probability values of 〇 and 1, respectively. The probability values indicate the correct input bits 疋. However, such lower probability values may not be considered good enough to terminate decoding at this point. Therefore, additional iterations can be performed. Figure 13A shows that the output probability value 135 from the first level of iteration is affected by the use of one of the first vertical iterations of the row parity bit 137. The calculated probability value 139 of the first vertical iteration is calculated in the same manner as before, and this time using the row co-located item 137 is calculated along the line. Thus, Dll is from Di2 and? 3 llr and to get (-(^ and ^, give 〇1}. Di2 is obtained from LLR and get 〇·4 and 6.0, giving -1.4). In this way, for each item 124726.doc - 27- 200823666 Obtain a calculated probability value 139. Next, the calculated (external) probability value 139 is added to the input probability values 135 (the output probability values of the first level iteration) to obtain the first vertical The output probability value i4i of the iteration. The output probability values 141 (1.5, -1.5, -1·5, 1.1) obtained from the vertical iteration of the brother can be considered to be good enough to terminate the decoding at this point. More decoding iterations may be performed to terminate the predetermined conditions required for decoding. Figure 13C shows that a second level of iteration is being performed. The calculated probability values 139 from the first vertical iteration are first compared to the original probability values 132. Adding an input value 143. The input value 143 and the column parity item 131 are then used together to obtain a second level calculated probability value 145. The second horizontal probability value 145 is then added to the input value 132. The second level of iteration has an output probability value of 147. The horizontal iteration output probability value 147 does not result in an overall probability value improvement from the output of the first vertical iteration. Figure 13D shows that a second vertical iteration is being performed. The output values 147 from the second level iteration are used. Input values for this iteration. As previously described, row co-located items 137 are used with the input values to obtain a calculated probability value 149. The calculated probability value 149 is then added to the input probability values 147 to obtain an output probability value 151. Comparing the output value 141 from the first vertical iteration, the display improves the output value 151 from the second vertical iteration. Thus, it can be seen that additional iterations can provide additional data improvements. Iterative decoding can be cycled throughout the iteration process until Satisfying a certain predetermined condition. For example, the predetermined condition may be that each probability value in a probability value output set exceeds a certain minimum probability value. Alternatively, the predetermined condition may be derived from 124726.doc -28· 200823666 (one) probability value Some parameters, such as an interval or average probability. The pre-conditions may only be performed - a certain number of iterations. In some cases ( As described below, the -嶋 decoder provides an output probability value, which is then subjected to another-operation' to indicate whether additional coffee iterations should be performed. The examples of Figures 13A through 13D can be viewed as a technical paradigm called acceleration deblocking The horizontal and vertical co-located bits provide a separately decodable two alternative coding scheme... using two such decoding schemes and using the from-decoding scheme

The output is the input to other alternatives, and the accelerated coding generally provides a higher error correction capability. Efficient decoding depends on having an appropriate encoding/decoding scheme. Various schemes are known for encoding data in a manner suitable for subsequent decoding in a SlS(R) decoder. The encoding/decoding scheme includes, but is not limited to, an accelerometer, a product code, a BCH code 'Reed Solomon code (Reed_s〇1〇m〇nc〇de), a convolutional code (refer to US Patent Application No. 11/383, 4〇1 and 11/383, 4〇5), Hamming code and low density parity correction (LDpC) code. The LDPC code has a code of a parity check matrix that satisfies a specific requirement, thereby generating a sparse parity check matrix. This means that each parity correction is performed on a relatively small number of bits. An example of a co-located check matrix for an LDpC code is shown in Figure 14. The conditions for an LDPC code are: (1) The number of 1 items in each column is the same and the number of total items in the comparison column is small. (2) The number of total items in each row is the same and the number of total items in the comparison line is small. (3) The number of 共用 shared between any two lines is not greater than! (The number of shares 1 can only be zero or one). The irregular LDPC code allows for a certain deviation of 1 number in the row and column. View Η, among the total of seven items in a column, each column has 124726.doc • 29- 200823666

There are three kinds of things that make the condition (1). In a total of seven projects in a row, each row has three! So that the condition (2) is satisfied. No two lines have a total of one or more, so the condition (3) is satisfied. For example, the first, first, and fourth rows each have -1 as the top item, but the rows are not addressed by another one and thus the 'matrix Η defines - LDPd the code from all the codewords in the matrix Composed of. This means that seven different parity check conditions must be met (defined by these seven columns). Each parity check condition is found in the word, and each item. For example, the first column indicates that the second, second, and fourth items within a character must have a modulus two and zero. The data can be encoded by computing a particular parity bit to form a codeword based on an LDPC code. Thus, one codeword of the parity check matrix η can be formed by four data bits and three parity bits calculated from the four data bits. Each 'bit' is calculated from a relatively small number of data bits, so the encoding may be relatively simple, even if a larger number of items are coded into a single block. A suitable LDPC code for memory applications uses approximately 4,000 to 8, 〇〇〇 one 兀 (1 to 2 segments, one of which is 512 octets). For example, encoding based on the LDPC code can add approximately 12% to unencoded material. The number of turns in one of the columns of one of the parity check matrices used for such encoding may be about 32 out of about 4000, so even if the character is large, the equivalent calculation is not too long. Thus, the parity bit may be relatively easy to calculate during encoding and the parity may also be relatively easily checked during decoding. The LDpc code can be used with hard input hard output decoding or SIS0 decoding. As before, SISO decoding can sometimes be improved during hard input hard output decoding. I24726.doc •30- 200823666 Yes. The original probability value can be supplied to an SISO decoder as an LLR or in some other form. An LDPC can use an iterative approach to a SISQ decoder. An item is shared by several co-located groups such that one of the calculated probability values obtained from a group provides improved data for use in another co-located group. Such calculations can be performed iteratively until a predetermined condition is met.

When the number of errors is extremely low, LDPC decoding may sometimes provide poor results. It is more difficult for the fork to be in a certain number of errors, resulting in a "wrong floor." One solution to this problem is to combine LDpc decoding with some other form of decoding. BCH or a similar generation of digital A hard input hard output decoder is added to an LDPC decoder. Thus, the LDpc decoder reduces the number of errors to a lower level, and then the bch decoder decodes the remaining errors. The decoder system that operates continuously in this manner Called "quote". In this case, the sequence is also executed before the data is stored in the memory array. (IV) Displayed in - ECC unit 155 (4) - Serial coding and decoding mode. The ECC unit includes an encoding system 157 and a decoding system I". The second system is received by the ECC unit 155 and first encoded in the encoder a, wherein the code is encoded according to the coding scheme A. Then, the coded data is sent to the system according to the coding scheme B. In the present m coding scheme a is a bile coding scheme, which adds a co-located bit heart, so that in one example, the number of data is increased by more than the element to the coding scheme, and the additional homolocation is added. Capital: = (10) material 'and thus add a quota in this example. The receiver sends the double coded data to - modulation / demodulation 124726.doc • 31 · 200823666 variable unit and stylized to a non-sinister secret Soil volatile memory array. Subsequently, you read the double weed in the 兮卞k body array to extract the data and demodulate the data to provide a soft input to the decoder. , ρη JIM Xji7 ^ especially, flat code Case B to decode data. Similarly, the decoder using the encoding scorpion A 'shell shaking SISOMm 55 ". Case A. The decoder 3 of this example is a WSO decoder, which is in the dual generation. The implementation of one or more decodings is performed on the data, and the decoder B sends the output to the decoder A. The items from the decoder B that are added to the co-located data are not included for editing. These items have been used by decoder B and are no longer necessary. The rim of decoder B is a soft output at the output of ^. This soft output can be converted to a hard data in a =:, 161, which removes the probability code & (b) into binary information. This hard data is then provided as a hard input to the second, and decoder A performs hard input and hard output decoding. The hard output from the second calculus horse is transmitted from the ECC unit 155 as correction data. In one embodiment, the field μ μ , & 〜 is used to terminate the decoding of the decoder within the iterative decoding: conditional decoder 8 indicates that the data is superior. After the generation in the decoder, the soft output can be converted to hard data and provided as a hard input to the decoder. The decoder then attempts to decode the data. If the decoding ^A cannot decode the data, then decoder B performs at least - additional iterations. If decoder A can decode the data, then no more aliasing is required in decoding HB. In this example, decoder eight provides a feedback (6) to decoder δ to indicate when decoder B should be terminated. k s Figure 15 The dry case handles the hard input hard output and the sis 〇 encoding sequence, and other combinations can be used. Two or more (10) ◦ decoders can be used in series and 124726.doc -32- 200823666 can also use two or more hard input hard output decoders. The soft input in the above example is obtained by using the parsing (four) that is higher than the previous stylized data. In other models, you can use other information to derive soft input data. In addition to the material in the memory level 70 - simple! · Decide that any quality information provided by the outside can be used to provide - soft input. In some memory designs, the count of the number of times a block has been erased is maintained. As the count increases, the memory's reality can be changed in a predetermined manner, making a particular error more likely: in the case where such a pattern is known, the erase count can be used to obtain probabilistic data. Other factors known to affect stylized data in a predictable manner can also be used to obtain probabilistic information. In this way, the same resolution for the program data can be used to read data from the memory array and the data is still used to provide a soft input. Two sources of probabilistic information can be combined. Thus, probabilistic information from the use of a high resolution item to extract the material can combine probabilistic data from another source. Thus, a soft input is not limited to being obtained directly from reading the memory array.

Probability information. X The above various II examples refer to flash memory. However, a variety of other non-volatile memory are currently in use and the techniques described herein are applicable to any suitable non-volatile memory system. Such memory systems may include, but are not limited to, a ferroelectric memory (FRAM or FeRAM) based memory system, a magnetoresistive memory (MRAM) based memory system, and a phase change based or "OUM" (" Phase change memory")) memory. All patents, patent applications, articles, books, specifications, other notices, documents and things cited herein are hereby incorporated by reference in their entirety for all purposes. Any inconsistency in the definition or use of terms between the persons, or the text of the document, shall be to some extent the term definition or use of the subject. The present invention has been described with respect to particular preferred embodiments, but it should be understood that the present invention is protected by the scope of the appended claims. & [Simplified Schematic] Figure 1 shows the probability function of the threshold voltage of a unit programmed into a logic state and a logic state in a non-volatile memory, including for distinguishing between logic 1 and logic. One of the states of the voltage Vd. Figure 2 shows the components of a memory system including a memory array, modulator/demodulator circuit, and encoder/decoder circuitry. Figure 3 shows the probability function of the threshold voltage of the unit programmed into a logic state and a logic state, showing the threshold voltage value. Figure 4 shows a component of a memory system including a memory array, a modulator/demodulator circuit, and an encoder/decoder circuit, a demodulation providing a probability value to a decoder. Figure 5 shows a NAND string connected to a sense amplifier to read the state of the memory cell. Figure 6A shows the probability function of the threshold voltage for a unit that is programmed to a logic state and a logic state, including three threshold voltages. Figure 6B shows the probability function of the read threshold voltage of the unit programmed to four states and shows the threshold voltage in the case of the read unit. Figure 7 shows the individual probability values for a first 124726.doc -34 - 200823666 and a second bit in a memory of two bits per cell as a function of threshold voltage. Figure 8 shows an encoder/decoder unit having a soft input soft output (SISO) decoder. Figure 9 shows an exemplary coding scheme in which the input data is configured in a matrix and a parity bit is calculated for each column and row. Figure 10 shows a specific example of a signal that is affected by noise that causes errors in the data that cannot be corrected using a hard input decoder, but can be corrected using a SISO decoder.

Figure 11 shows an alternative coding scheme in which the parity bits are calculated for input data, the input data is arranged in columns and rows, and a parity bit is calculated for each column and row. Figure 12 shows a component of a memory system' including an encoder providing the code shown and a demodulation transformer providing the original probability value to the _ _0 decoder. Figure 13A shows one of the first horizontal iterations performed by the SISO decoder of Figure 12. The figure shows one of the first vertical iterations performed by the 8180 decoder of Figure 12. Figure 13C shows a second horizontal iteration performed by the SISO decoder of Figure 12. Figure 13D shows a second vertical iteration performed by the SISO decoder of Figure I2. One Low Density Parity Check Figure 14 shows the (LDPC) parity check matrix used in a SISO decoder. 124726.doc -35- 200823666 Figure 15 shows an encoder/decoder with a serial encoder and a serial decoder. [Main component symbol description] 101 Signal 103 Noise 105 Input 107 Hard input 109 Soft input correction data

111 Soft Output 113 Soft Output 121 Decoder 123 ECC Unit 125 Modulator 126 Memory Array 126 Demodulation Transmitter 129 SISO Decoder 131 Column Co-located Bit 133 Calculated Probability Value 135 Probability Value 137 Row Co-located Bit 139 Calculated Probability Value 141 Output probability value 143 Input value 145 Second level calculation probability value 124726.doc -36- 200823666

147 Output probability value 149 Calculation probability value 151 Output probability value 155 ECC unit 157 Encoding system 159 Decoding system 161 Soft and hard converter 163 Feedback 200 Memory system 201 ECC unit 203 Encoder 205 Modulation/demodulation variable unit 207 Modulation 209 memory array 211 input data bit 213 demodulator 215 decoder 421 memory system 423 memory array 425 demodulation 427 modulation / demodulation circuit 429 decoder 431 ECC unit 541 string 124726. Doc -37- 200823666 543 string selection transistor 545 string selection transistor 547 sense amplifier 651 threshold voltage range 652 threshold voltage range 653 threshold voltage range 654 threshold voltage range 861 decoder 863 SISO decoder 864 hard and soft converter 865 Encoder 867 ECC unit 124726.doc -38-

Claims (1)

200823666 X. Patent Application Range: 1. A method of decoding data stored in a non-volatile memory array, the data being encoded according to a predetermined scheme, the method comprising: · from the non-volatile memory array Reading the encoded data to obtain a plurality of bits; obtaining probability information about the plurality of bits; and using the 敎 scheme to calculate an output probability value from the plurality of bits and the probability information To calculate. • The method of claim 1, wherein obtaining a probability for the plurality of bits comprises reading the encoded data using a resolution that exceeds a number of stylized states used to program the encoded data Read 3· as requested! The method wherein the output probability value is calculated to occur in a first iteration, and wherein the output probability values are subsequently used to calculate an additional output probability value using at least one additional iteration. 4. The method of claim 3, wherein the additional output probability value is calculated using an iteration until a predetermined condition is met. :: Method of claim 1 wherein the output probability values are used to obtain hard data. Hai Hard provides a hard input hard output decoder for the system. 6. A method of storing and retrieving data in a non-volatile memory array, comprising: receiving a plurality of input data bits for storing in the non-volatile memory redundant data bits from the plurality of input data bits Calculating a plurality of 124726.doc 200823666 yuan; storing the plurality of input data bits and the plurality of redundant data bits in a plurality of cells in the non-volatile memory array, wherein the plurality of cells are individual programs Converting to one of the n states; subsequently reading the plurality of cells to obtain the original data, the read analysis • n or more states per cell; _ calculating a plurality of original probability values from the original data, the plurality of original probability values Corresponding to the input data bit and the redundant data bit; calculating a first plurality of calculated probability values from the plurality of original probability values, wherein the one of the first plurality of calculated probability values is corresponding to an input body Calculating at least one original probability value of the level bit and at least one original probability value corresponding to a redundant data bit; and ~ a plurality of five different probability values Computing a plurality of output data bits yuan. 7. The method of claim 6, wherein calculating the plurality of output data bit packets comprises calculating a second plurality of calculated probability values from the first plurality of calculated probability values. • The method of monthly finding 7 wherein the first plurality of calculated probability values and the first plurality of leaf different probability values are progressively calculated using an accelerating code that repeatedly calculates a plurality of probability values until a predetermined condition is met. The method of 'the' wherein the plurality of redundant data bits are generated by a low cipher parity check (LDPC) encoder. 10. The request item, <method' further comprising performing a hard input hard output error correction code (ECC) operation on the plurality of output data. 124726.doc 200823666 wherein if the ECC operation indication is greater than a threshold, calculating from the first plurality of probability values, wherein if the ECC operation indication is lower than the threshold, correcting in the plurality of output data bits 11 One of the number of methods as claimed in item 10 is the number of errors, the second plurality of probability values 12, such as an error number of the number of methods of claim item 10. 13. A method of reading and storing data in a non-volatile memory array storing at least two bits of data per memory unit, comprising: receiving a plurality of input poor bits for storage in the non-volatile memory Calculating a plurality (four) of remaining data bits from the plurality of input data bits; storing the plurality of input data bits and the plurality of redundant data bits in the non-volatile memory array Within the unit, wherein the plurality of units are (4) stylized to a -number of stylized states, the private state indicating at least two bits per unit; and then reading the plurality of units to obtain original data, Reading a second number of read states, the second number being greater than the first number; and subsequently calculating a plurality of original probability values from the original data, one of the plurality of original probability values corresponding to one A single input data bit or a single redundant data bit. 14. The method of claim 13, wherein the plurality of original probability values are derived from a lookup table using the probability of each I24726.doc 200823666 bit stored in a memory unit and from the memory The original data of the body unit are individually associated. The method of claim 13, wherein the plurality of input data bits and the plurality of data bits are stored by staging the plurality of cells to a threshold voltage range, the threshold voltage range Individually represents two or more bits. 16. The method of claim 15, wherein the threshold voltage ranges are mapped to bits in accordance with a Gray code. The method of claim 15, wherein the threshold relocation ranges are mapped to bits according to a binary coding scheme. 18. The method of claim 13, wherein the reading is obtained by comparing the electro-migration of the future unit with the -type reference dust pattern, the pattern being in one of the threshold voltage ranges of the -stylized state The outer portion has a higher reference voltage density than at the center of the threshold voltage range. 19. The method of claim 13, wherein the Α 一 * 八 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含The original probability value corresponds to at least the original probability value corresponding to a few squats 70. 20. According to the method of claim 13, the soft input soft output error is corrected by the i code and the == bit is based on the calculation. And from the plurality of original probability values, such as the method of claim 20, 22. The method of claim 20, wherein: the second calibration code system - the acceleration code - the kind of non-volatile record The second school: take the method of “calling I”#, where 124726.doc 200823666 is stored in the memory unit that is programmed to the threshold voltage range, and the threshold voltage range corresponds to the state of the memory unit. The scoop contains: ° performing a plurality of read operations on a memory cell that is stylized to a threshold voltage range, the plurality of read operations performing 'the predetermined pattern for one of the threshold voltage ranges according to a predetermined pattern The first portion provides a higher density read operation than the second portion of the threshold voltage range; and derives at least one probability from the plurality of read operations, the representation being - programmed in the memory unit The bit has a logical state of 24. The method of claim 23, wherein the at least one probability value is derived using a lookup table from the plurality of read operations, the lookup table is for storage: Members yuan to provide individual probability values in the memory unit. The 概率γ 23^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 26. If the party of claim 25 /, a ν匕$, outputs the output information from the soft input to the soft output decoder, the hard output decodes 11, and the decoder performs further error correction. 27. A non-volatile memory system comprising: - a memory array comprising a plurality of data n/70' material units storing complex-one parity bits, the equivalent bit elements being based on a code scheme And calculating from the plurality of data bits; 124726.doc 200823666 a demodulation device that reads a plurality of units and derives a raw probability value corresponding to the plurality of data bits and the plurality of parity bits And a decoder that receives the raw probability values and uses the encoding scheme to calculate an output probability value therefrom. The non-volatile memory system of claim 27, wherein the demodulator • parses a number of read states per cell, the number of read states being greater than a stylization for stylizing the plurality of cells The number of states. The non-volatile memory system of claim 27, wherein the decoder then uses the encoding scheme to calculate an additional probability value from the output probability value. 30. The non-volatile memory system of claim 29, wherein the decoder uses two or more iterations to calculate additional probability values, the iterations being performed until a predetermined condition is met. 3 1 . The non-volatile memory system of claim 3, further comprising a hard input hard output decoder. • 32. The non-volatile memory system of claim 27, wherein the encoding scheme uses accelerated encoding. 33. The non-volatile memory system of claim 27, wherein the encoding scheme uses a low density parity check (LDPC) code. 34. The non-volatile memory system of claim 27, further comprising a converter that converts a soft input to a hard output. 3 5 - a non-volatile memory system comprising: a non-volatile memory array storing two or more bits in one other memory unit; and 124726.doc 200823666 a demodulation transformer, It derives a unique probability value for each of the two or more bits stored in the individual record unit. 36. The non-volatile memory system of claim 35, further comprising a lookup table for obtaining the individual probability values for each of the two or more bits. 37. The non-volatile memory system of claim 35, wherein the two or more bits comprise at least one co-located, which is added in accordance with a coding scheme. The non-volatile memory system of claim 35, wherein the demodulator derives the individual probability values by using a resolution to read individual memory cells, the resolution identifying more than individual memories The number of stylized states of the number of stylized states of the body unit. 39. The non-volatile memory system of claim 35, further comprising a soft input soft output decoder that receives the individual probability values as inputs and calculates an output probability pseudo from the individual probability values. 40. The non-volatile memory system of claim 35, wherein the demodulation device reads a single memory cell using a predetermined read operation pattern, the pattern having at least one higher density region and a lower density region . 41. A non-volatile memory system, comprising: a non-volatile memory cell array that is individually programmed to one of two or more threshold voltages, the threshold voltage ranges representing two or more states And a demodulation transformer that parses an individual cell threshold voltage to one of the two or more threshold voltage ranges and by identifying the first portion of the threshold voltage range for the identification One of the threshold voltage ranges 124726.doc 200823666 Brother-PA for a more density read operation to enter the individual unit of the threshold voltage range, the identification is used for the voltage of the eight, the demodulation from The non-volatile memory system ^ /, as in claim 41, further includes an input soft output decoder that receives the probability value as an input. 43. The non-volatile memory system of claim 42, wherein: decoding is performed using a plurality of iterations to calculate an output probability value, a predetermined condition. 满足 to satisfy a 44. The body system, send a gossip & contains a soft and hard converter, when the predetermined condition is met, A is replaced by a hard output value. - The output probability value is converted to 45. The non-volatile memory of claim 43 The system further includes a hard input hard output decoder that receives an output probability value of f from the soft input soft output decoder 'the hard input hard output decoder determines a time to satisfy the predetermined condition. 46. The non-volatile memory system of claim 41, wherein the non-volatile memory early staging system is individually programmed to four or more threshold voltage ranges, and the threshold electric house range represents four or more states to store two Or more bits, the demodulation transformer derives a probability value for each of the two or more bits. 124726.doc