CN101894582B - Method, device and equipment for decoding storage data - Google Patents
Method, device and equipment for decoding storage data Download PDFInfo
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- CN101894582B CN101894582B CN200910059383.9A CN200910059383A CN101894582B CN 101894582 B CN101894582 B CN 101894582B CN 200910059383 A CN200910059383 A CN 200910059383A CN 101894582 B CN101894582 B CN 101894582B
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Abstract
The embodiment of the invention discloses a method, a device and equipment for decoding storage data. The method comprises the following steps of: coding read storage data for generating a decoding check bit of the storage data; comparing a coding check bit of the read storage data with the decoding check bit; if the coding check bit and the decoding check bit are inconsistent, decoding the storage data for obtaining decoded storage data and transmitting the decoded storage data to a demand end; and if the coding check bit and the decoding check bit are consistent, directly transmitting the storage data to the demand end for optimizing a coding circuit in an error correcting code circuit and a decoding error detecting circuit and reducing resource consumption.
Description
Technical field
The present invention relates to technical field of data storage, relate in particular to the method that the data to storing in memory device are carried out decoding, device and equipment.
Background technology
At present in field of storage, along with the development of time and technology, new memory device manifests increasing advantage, flash memory has possessed the incomparable superperformance of a lot of conventional hard, be accompanied by the expansion of memory device application and the development of application technology, user requires also more and more higher to memory device read or write speed.Taking flash memory as example, utilizing the read-write of multiple passages is to improve the most direct way of the absolute readwrite bandwidth of flash memory, can increase exponentially the interface bandwidth of flash memory device, if 4 passage theoretical bandwidth are single passly to approach 4 times.
In order to ensure the reliability of data stored by flash memory, in flash memory control, must design error correcting code (ECC, Error Correct Code) circuit and to a certain extent data be protected, in certain error range, can recover data.No matter single channel or multichannel flash memory device, when data write flash memory, first encodes to it, for hyperchannel, need to be at each passage to data encoding, after having encoded by the check bit generating together with data data writing memory block.During from data storage area reading out data, need to carry out decoding error detection to each channel data of reading, detection data are made a mistake, adopt decoding error correction to correct the data within the scope of error correcting capability, its decoding as shown in Figure 1.
Along with flash memory development, its density is increasing, and ECC error correcting capability need to have corresponding raising.Error correcting capability improves, and can make ECC circuitry consumes logical resource greatly increase, and chip area increases, and therefore, reducing ECC circuit resource is that ECC designs maximum challenge.The resource of ECC circuit and its coding and decoding degree of parallelism, data bit width is directly related.Degree of parallelism is larger, and resource consumption is more, therefore, reduces degree of parallelism and just can make resource greatly reduce.The cost of doing is like this to have increased data transmission period, and transmission bandwidth reduces greatly, thereby affects the efficiency of whole system.
In prior art, common way is, keeps the error detection circuit part parallel degree of coding&decoding constant, reduces the degree of parallelism of error correction circuit, thereby reduces the resource of error correction circuit, because error correction circuit is that in whole ECC circuit, resource consumption is maximum.Like this, data readwrite bandwidth in the situation that not making a mistake can not be affected.Once error detection is found read data and is staggered the time, wide will the reduction of reading tape.Flash memory write data must be passed through coding circuit calculation check position, flash memory read data must carry out error detection computing through decoding error detection circuit, therefore, this two parts circuit can not lean on the method for direct reduction degree of parallelism to reduce resource, otherwise can reduce the bandwidth that reads and writes data, logical resource is increased greatly, and coding circuit and the decoding error detection circuit optimized in ECC design become a key issue that reduces logical resource.
Summary of the invention
The method that the embodiment of the present invention provides the data to storing in memory device to carry out decoding, device and equipment, effectively to reduce the use of system resource.
Embodiments of the invention provide a kind of storage data decoding method, and the method is by the multiplexing coding circuit decoding error detection circuit of doing, and described method comprises:
The input data of user side are write to flash memory after described coding circuit coding stores;
Described coding circuit coding generates the coding checkout position of storage data, and described coding checkout position is write to described flash memory stores;
In the time of the described storage data of described user side needs, reception control signal, described control signal is indicated the information of the storage data of described user side needs;
Described coding circuit reads described storage data according to described control signal from storage data field, and described storage data are encoded and generated decoding check bit, wherein, described coding circuit is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel;
When obtaining described storage data and writing flash memory by the described coding circuit described coding checkout position obtaining of encoding;
Described coding checkout position and described decoding check bit are compared;
If described more consistent, the described storage data that read are sent to demand data end.
The embodiment of the present invention provides a kind of storage data decoding method, and the method is by the multiplexing coding circuit decoding error detection circuit of doing, and described method comprises:
The input data of user side are write to flash memory after described coding circuit coding stores;
Described coding circuit coding generates the coding checkout position of storage data, and described coding checkout position is write to described flash memory stores;
In the time of the described storage data of described user side needs, reception control signal, described control signal is indicated the information of the storage data of described user side needs;
Described coding circuit reads described storage data according to described control signal from storage data field, and described storage data are encoded and generated decoding check bit, wherein, described coding circuit is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel;
When obtaining described storage data and writing flash memory by the described coding circuit described coding checkout position obtaining of encoding;
Described coding checkout position and described decoding check bit are compared;
If described more inconsistent, described storage data carried out to decoding and obtain the storage data after decoding;
Storage data after described decoding are sent to demand data end.
Embodiments of the invention also provide storage data decording apparatus, and this device is by the multiplexing coding circuit decoding error detection circuit of doing, and described device comprises: coding unit, control module and data transfer unit,
Described coding unit, for storing writing flash memory after the input data encoding of user side, and the coding checkout position of generation storage data, described coding checkout position is write to described flash memory stores, in the time that described user side needs described storage data, receive the control signal that described control module sends, read storage data according to described control signal from storage data field, and described storage data are encoded and generated decoding check bit, wherein, described control signal is indicated the information of the storage data of described user side needs;
Described control module, compares described coding checkout position and described decoding check bit for controlling described coding unit;
Described data transfer unit, for reading the coding checkout position of described storage data and described storage data, and describedly sends to demand data end by described storage data when more consistent;
Wherein, described storage data decording apparatus is coding circuit, and described storage data decording apparatus is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel.
Embodiments of the invention also provide storage data decording apparatus, and this device is by the multiplexing coding circuit decoding error detection circuit of doing, and described device comprises: coding unit, decoding error detection unit, decoding error correction unit, control module and data transfer unit,
Described coding unit, for storing writing flash memory after the input data encoding of user side, and the coding checkout position of generation storage data, described coding checkout position is write to described flash memory stores, in the time that described user side needs described storage data, the control signal that reception control unit sends, read storage data according to described control signal from storage data field, and described storage data are encoded and generated decoding check bit, wherein, described control signal is indicated the information of the storage data of described user side needs;
Described control module, compares described coding checkout position and described decoding check bit for controlling described coding unit;
Described decoding error detection unit, detects described storage data and generates the error in data positional information that described storage data make a mistake when more inconsistent for described;
Described decoding error correction unit, for determining according to described error in data positional information the position that described storage data make a mistake, carries out error correction to the storage data of described position;
Described data transfer unit, under the control of control module, described storage data, described coding checkout position and described decoding check bit being read and transmitted, and sends to demand data end by the described storage data after error correction;
Wherein, described storage data decording apparatus is coding circuit, and described storage data decording apparatus is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel.
Embodiments of the invention also provide storage data decoding equipment, and this equipment is by the multiplexing coding circuit decoding error detection circuit of doing, and described equipment comprises: coding circuit, decoding scheme, control device and data link,
Described coding circuit, for storing writing flash memory after the input data encoding of user side, and the coding checkout position of generation storage data, described coding checkout position is write to described flash memory stores, in the time that described user side needs described storage data, the control signal that reception control unit sends, read storage data according to described control signal from storage data field, and described storage data are encoded and generated the decoding check bit of described storage data, from described flash memory, deposit the coding checkout position that obtains described storage data, coding checkout position described in described decoding check bit sum is compared, wherein, described control signal is indicated the information of the storage data of described user side needs, described coding circuit is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel,
Described decoding scheme, more inconsistently carries out decoding to described storage data and obtains the storage data after decoding for described;
Described control device, for controlling described coding circuit and described decoding scheme carries out aforesaid operations;
Described data link, for read and transmit described storage data, described coding checkout position and described decoding check bit under control device control, describedly more described storage data are sent to demand data end, or describedly more inconsistent storage data after described decoding are sent to demand data end.
The technical scheme being provided by the embodiment of the invention described above can be found out, be optimized by the method, device and the equipment that carry out decoding in single channel and hyperchannel to storing data, adopt reception control signal, generate the decoding check bit of the storage data that read according to described control signal; Coding checkout position to the described storage data that read and described decoding check bit compare; Described more consistent, directly described storage data sent to demand data end or describedly more inconsistently described storage data are carried out to decoding obtain the storage data after decoding, and send to demand data to bring in the use that reduces system resource, the utilization of Hoisting System resource the storage data after described decoding.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 stores data encoding and decode procedure schematic diagram in prior art;
Fig. 2 is the method schematic diagram of one embodiment of the invention storage data decoding;
Fig. 3 is the method schematic diagram of further embodiment of this invention storage data decoding;
Fig. 4 controls lower storage reading and writing data schematic diagram the higher clock period of one embodiment of the invention;
Fig. 5 is the device schematic diagram of one embodiment of the invention storage data decoding;
Fig. 6 is the device schematic diagram of further embodiment of this invention storage data decoding;
Fig. 7 is the device schematic diagram of further embodiment of this invention storage data decoding;
Fig. 8 is the device schematic diagram of further embodiment of this invention storage data decoding;
Fig. 9 is further embodiment of this invention storage data decoding equipment schematic diagram.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
For ensureing to store in memory device the reliability of data, in storage is controlled, design error-correcting code circuit data are protected, in certain error range, can recover data.Memory device in the present invention can be all kinds of memory devices that use at present, comprises flash memory, various memory discs etc.Flash memory control in storage is controlled, error-correcting code circuit can be used on the user side passage of single channel read-write flash memory device or each passage of hyperchannel read-write flash memory device, in the not high situation of error rate, multiple passages can a multiplexing decoding error correction circuit.The coding circuit in error-correcting code circuit is carried out the multiplexing decoding error detection circuit of doing by technical solution of the present invention, and so, along with increasing of port number, resource can effectively be utilized.When user side data are stored, be encoded under the manipulation of storage device control apparatus as input data, generate coding checkout position, described coding checkout position is written in data storage area and preserves together with described user side data, when the user side storage data of described preservation are read out when user needs, process and send into user side by decoding, decoding is herein processed by following embodiment scheme and is embodied.
One embodiment of the invention proposes the method that storage data are carried out decoding, as shown in Figure 2, comprises following technical scheme:
S101, reception control signal, generate the decoding check bit of the storage data that read according to described control signal.
Reception control signal, encodes to the storage data that read data field from storage according to control signal, described in be coded in coding circuit and carry out, the coding circuit storage data generation decoding check bit reading of encode.
S102, coding checkout position and described decoding check bit to the described storage data that read compare.
Obtain to the described storage data of user side write storage when data field by the encode coding checkout position of described storage data of acquisition of coding circuit, described coding checkout position is stored in described storage data field.
S103, described more consistent, sends to demand data end by described storage data.
Coding checkout position to the described storage data that read and described decoding check bit compare, when the coding checkout position of the described storage data that read identical with described decoding check bit, or while meeting default comparison condition, described storage data are sent to the user side that needs described storage data.
The interpretation method of above-mentioned storage data is applicable to the decoding to storing data in all kinds of memory devices, controls as the decoding treatment process of flash memory, readable writable memory and memory disc class etc.For single channel and multichannel memory device, above-mentioned interpretation method is the optimization to coding circuit and decoding error detection circuit, and the above-mentioned interpretation method of sampling, by carrying out the multiplexing of decoding processing with coding circuit, effectively reduce the consumption of resource, promoted resource utilization.
Further embodiment of this invention proposes the method that storage data are carried out decoding, as shown in Figure 3, comprises following technical scheme:
S201, reception control signal, generate the decoding check bit of the storage data that read according to described control signal.With step S101.
S202, coding checkout position and described decoding check bit to the described storage data that read compare.With step S102.
S203, described more inconsistent, carries out decoding to described storage data and obtains the storage data after decoding.
Coding checkout position to the described storage data that read and described decoding check bit compare, when the coding checkout position of the described storage data that read not identical with described decoding check bit, or while not meeting default comparison condition, judge that described storage data make mistakes, now described storage data are sent into decoding scheme detects and error correction, obtained the storage data content after correcting a mistake.
S204, the storage data after described decoding are sent to demand data end.
To send to the user side that needs described storage data through the storage data that detect after error correction.
The interpretation method of above-mentioned storage data is applicable to the decoding to storing data in all kinds of memory devices, controls as the decoding treatment process of flash memory, readable writable memory and memory disc class etc.For single channel and multichannel memory device, above-mentioned interpretation method is the optimization to coding circuit and decoding error detection circuit, and the above-mentioned interpretation method of sampling, by carrying out the multiplexing of decoding processing with coding circuit, effectively reduce the consumption of resource, promoted resource utilization.
Further embodiment of this invention proposes the method that storage data are carried out decoding, taking flash memory as example, as shown in Figure 4, comprises following technical scheme:
S301, the storage data that read are encoded and generated the decoding check bit of described storage data.
The storage data that read from flash memory are encoded, and above-mentioned action can trigger according to user side demand, also may trigger according to the demand of system or other-end.The execution side of this interpretation method receives the control signal to storage demand data, the information of the storage data that this control signal indicating user end needs, described storage deposit data is in flash memory, encode to the described storage data that read from flash memory in decoded mode execution side, described coding can be carried out in coding circuit, coding circuit encode the storage data that read the decoding check bit that generates described storage data.
S302, coding checkout position and described decoding check bit to the described storage data that read compare, if described coding checkout position and described decoding check bit are inconsistent, execution step S303, if described coding checkout position is consistent with described decoding check bit, execution step S304.
When obtaining described storage data and depositing flash memory in by the coding circuit coding checkout position obtaining of encoding.It is that the input data of user side are write after described coding circuit coding that the storage data that are stored in the described needs in flash memory write flash memory, and the coding checkout position that also has the described storage data that described coding circuit coding generates that simultaneously writes of described storage data.
In the time that user side needs described storage data, coding circuit in interpretation method obtains the data of storing that are stored in flash memory, the coding checkout position that also has described storage data obtaining together with described storage data, in this step, the coding checkout position of the described storage data that the decoding check bit sum of the described storage data to above-mentioned generation obtains compares, and judges whether consistent, if inconsistent, execution step S303, if consistent, forward step S304 to and carries out.
S303, described storage data are carried out to decoding obtain the storage data after decoding.
If coding checkout position is inconsistent described in described decoding check bit sum, comprise described in described decoding check bit sum that coding checkout position is not identical, do not meet default a certain condition or be different from a certain specific threshold value, now judge that the described storage data from flash memory make mistakes, described storage data are sent into decoding error detection circuit, determine by decoding error detection circuit the positional information that described storage data make a mistake, can be parameter or with its identification information, the described positional information of determining is sent into decoding error correction circuit.Decoding error correction circuit obtains according to the definite positional information of decoding error detection circuit the position that described storage data make a mistake, and the storage data of this position are carried out to correcting data error.
S304, described storage data are sent to demand data end.
In this step, the storage data after error correction send to the user side that needs described storage data.
If according to step S302, described in described decoding check bit sum, coding checkout position is consistent, comprise described in described decoding check bit sum that coding checkout position is identical, meet default a certain condition or identical with a certain specific threshold value, now judge that the described storage data from flash memory are the storage data that write described flash memory, described poke data are correct, the described storage data that read from flash memory sent to the user side that needs described storage data.
The interpretation method of above-mentioned storage data is applicable to the decoding to storing data in all kinds of memory devices, controls as the decoding treatment process of flash memory, readable writable memory and memory disc class etc.For single channel and multichannel memory device, above-mentioned interpretation method is the optimization to coding circuit and decoding error detection circuit, and the above-mentioned interpretation method of sampling, by carrying out the multiplexing of decoding processing with coding circuit, effectively reduce the consumption of resource, promoted resource utilization.
Further embodiment of this invention proposes the method that storage data are carried out decoding, equally taking flash memory as example, comprises following technical scheme:
S401, the storage data that read are encoded and generated the decoding check bit of described storage data.
S402, coding checkout position and described decoding check bit to the described storage data that read compare, if described coding checkout position and described decoding check bit are inconsistent, execution step S403, if described coding checkout position is consistent with described decoding check bit, execution step S404.
S403, described storage data are carried out to decoding obtain the storage data after decoding.
S404, described storage data are sent to demand data end.
On the basis of last embodiment, in above steps, the system clock cycle applicable to the data of reading from flash memory can use higher system clock, because flash chip inputoutput data bit wide is lower, adopt higher system clock can effectively reduce the degree of parallelism of coding circuit and decoding error detection circuit, concrete, as, the inputoutput data bit wide of flash chip is 40M, system clock frequency adopts 4 overtones bands of flash chip inputoutput data bit wide, 4 system clock cycles are only used the data of reading a 8bits to flash memory, lower of each clock period need to be carried out the data encoding of 2bits, as shown in Figure 5, system_clk tag system clock in figure, data signal indication flash memory port read write data, bit wide is 8bits, the data that ecc_dat represents to send into the data of coding circuit or sends into decoding error detection circuit, bit wide is 2bits.So, the degree of parallelism of coding circuit and decoding scheme has reduced by 4 times, and resource is greatly reduced.It is minimum that described system clock can also adopt the higher clock period that the use of resource is down to, in the time that clock frequency is flash memory end inputoutput data bandwidth 8 overtones band, each clock period only need to be carried out the coding of 1bit data, now, the minimum use of coding&decoding error detection complete parallel resource of error-correcting code circuit.The enforcement of embodiment of the present invention interpretation method depends on control; in decoding; adopt the control of higher system clock cycle can realize the effective utilization to resource; the control of described higher system clock cycle is read for flash memory or when data writing; clock period is herein not limited to described above, can expect can effectively reduce resource use the higher clock period all within protection domain of the present invention.On the other hand, the multiplexing control that storage is adopted higher system clock cycle in decoding is processed when data encoding of coding circuit, coding circuit can adopt equally the control of higher system clock cycle in the coding that writes storage data to flash memory is processed.
The interpretation method of above-mentioned storage data is applicable to the decoding to storing data in all kinds of memory devices, controls as the decoding treatment process of flash memory, readable writable memory and memory disc class etc.For single channel and multichannel memory device, above-mentioned interpretation method is the optimization to coding circuit and decoding error detection circuit, and the above-mentioned interpretation method of sampling, by carrying out the multiplexing of decoding processing with coding circuit, effectively reduce the consumption of resource, promoted resource utilization.In promoting resource utilization, owing to adopting the control of higher system clock further to reduce the use of resource.
One embodiment of the invention proposes a storage data decording apparatus, and as shown in Figure 6, described storage data decording apparatus is by coding unit 601, and control module 602 and data transfer unit 603 form.
Described coding unit 601, the control signal sending for reception control unit 602, generates the decoding check bit of the storage data that read according to described control signal;
Described control module 602, the coding checkout position for control coding unit 601 to described storage data and described decoding check bit compare;
Described data transfer unit 603, for reading the coding checkout position of described storage data and described storage data, and describedly sends to demand data end by described storage data when more consistent.
Above-mentioned storage data decording apparatus is applicable to the decoding to storing data in all kinds of memory devices, controls as the decoding treatment process of flash memory, readable writable memory and memory disc class etc.For single channel and multichannel memory device, above-mentioned code translator is the optimization to coding unit and decoding error detection unit, and the above-mentioned code translator of sampling, by carrying out the multiplexing of decoding processing with coding unit, effectively reduce the consumption of resource, promoted resource utilization.
Further embodiment of this invention proposes a storage data decording apparatus, and as shown in Figure 7, described storage data decording apparatus is made up of coding unit 701, control module 702, data transfer unit 703, decoding error detection unit 704 and decoding error correction unit 705.
Described coding unit 701, the control signal sending for reception control unit 702, generates the decoding check bit of the storage data that read according to described control signal;
Described control module 702, the coding checkout position for control coding unit 701 to described storage data and described decoding check bit compare;
Described decoding error detection unit 704, detects described storage data and generates the error in data positional information that described storage data make a mistake when more inconsistent for described.
Described decoding error correction unit 705, for determining according to described error in data positional information the position that described storage data make a mistake, carries out error correction to the storage data of described position.
Described data transfer unit 703, under the control at control module 702, described storage data, described coding checkout position and described decoding check bit being read and transmitted, and sends to demand data end by the described storage data after error correction.
Above-mentioned storage data decording apparatus is applicable to the decoding to storing data in all kinds of memory devices, controls as the decoding treatment process of flash memory, readable writable memory and memory disc class etc.For single channel and multichannel memory device, above-mentioned code translator is the optimization to coding unit and decoding error detection unit, and the above-mentioned code translator of sampling, by carrying out the multiplexing of decoding processing with coding unit, effectively reduce the consumption of resource, promoted resource utilization.
Further embodiment of this invention proposes a storage data decording apparatus, and as shown in Figure 8, described storage data decording apparatus is made up of coding unit 801, control module 802, data transfer unit 803, decoding error detection unit 804 and decoding error correction unit 805.
Control module 802 reads the storage data of user's request from storage data field, and controls data transfer unit 803 the user's request data that read are sent into coding unit 801.In the present embodiment, data transfer unit 803 is stored reading, deposit and transfer operation of data, information and other data or parameter for described storage data decording apparatus, the data transfer operations such as data read, deposit, transmission are all carried out by this data transfer unit 803, follow-uply no longer specialize.The storage data of user's request enter after coding unit 801, by coding unit 801, the storage data of described user's request are encoded and are obtained the decoding check bit of the storage data from storing the user's request of reading data field.The coding checkout position of the storage data of the described user's request that control module 802 control coding unit read from storage described decoding check bit sum data field compares, and judges that whether coding checkout position is consistent described in described decoding check bit sum.Described coding checkout position by described storage data write before described storage data field by coding unit 801 to storage data encode generate, in the cataloged procedure of storage data, produce, the described coding checkout position producing writes storage data field in the lump together with described storage data, in the time need to reading the described storage data that write, described coding checkout position reads out together with described storage data, certainly, described coding checkout position read and write the time consistency that not necessarily storage data described above and described write and read, can exist the regular hour poor.Coding unit 801 carries out the comparison of coding checkout position and decoding check digit, and when described more consistent, control module 802 is controlled data transfer unit 803 the storage data of described user's request are sent into user side for user, and decode procedure finishes.When described when more inconsistent, control module 802 is controlled described storage data and is entered decoding error detection unit 804, the storage data generated data errors present information that described decoding error detection unit 804 receives described storage data and makes a mistake according to described storage Data Detection, decoding error detection unit 804 obtains the positional information of the storage data that make a mistake through a series of erroneous calculations, it is error in data positional information, described positional information can be for calculating the parameter of gained, also or for mark errors present label information, in every case within the information of energy misregistration Data Position is all included in this scope.Decoding error correction unit 805, be used for obtaining described error in data positional information, and the error in data positional information generating according to described decoding error detection unit is determined the position of the data that described storage data make a mistake, the storage data of described position are carried out to error correction to obtain correct storage data, the correct data after error correction is sent to the demand user side of described storage data.Described control module 802 is applicable to higher system clock cycle.
Above-mentioned storage data decording apparatus is applicable to the decoding to storing data in all kinds of memory devices, controls as the decoding treatment process of flash memory, readable writable memory and memory disc class etc.For single channel and multichannel memory device, above-mentioned code translator is the optimization to coding unit and decoding error detection unit, and the above-mentioned code translator of sampling, by carrying out the multiplexing of decoding processing with coding unit, effectively reduce the consumption of resource, promoted resource utilization.
One embodiment of the invention proposes a storage data decoding equipment, as shown in Figure 9, the memory device of storage data is taking flash memory as example, and described storage data decoding equipment comprises: coding circuit 901, control device 902, data link 903 and decoding scheme 906.Described storage data decoding equipment answers user's request the data of storing in flash memory are obtained and carried effective correct data to use to user.
Described coding circuit 901, the control signal sending for receiving control device 902, adopt the storage data that read to generate the decoding check bit of described storage data according to described control signal, the coding checkout position of the described storage data that described decoding check bit sum is read compares.
Described decoding scheme 906, more inconsistently carries out decoding to described storage data and obtains the storage data after decoding for described, and concrete described decoding scheme comprises decoding error detection circuit 9004 and decoding error correction circuit 9005.
Described control device 902, carries out aforesaid operations for control coding circuit 901 and decoding scheme 906.
Described data link 903, under controlling at control device 902, read and transmit described storage data, described coding checkout position and described decoding check bit, describedly more described storage data are sent to demand data end, or describedly more inconsistent storage data after described decoding are sent to demand data end.
Specifically, control device 902 receives user side instruction, described user side instruction can indicating user end demand to storage data, in the time that user side need to read the storage data of flash memory, control device 902 reads the storage data of user's request according to described user side instruction control data link 903 from flash memory, and controls data link 903 the user's request data that read are sent into coding circuit 901.In the present embodiment, data link 903 is stored reading, deposit and transfer operation of data, information and other data or parameter for described storage data decoding equipment, the data transfer operations such as data read, deposit, transmission are all carried out by this data link 903, follow-uply no longer specialize.The storage data of user's request enter after coding circuit 901, by coding circuit 901 to the encode decoding check bit of the storage data that obtain the user's request of reading from flash memory of the storage data of described user's request.The coding checkout position of the storage data of the described user's request that control device 902 control coding circuit 901 read described decoding check bit sum from flash memory compares, and judges that whether coding checkout position is consistent described in described decoding check bit sum.Described coding circuit 901 also for generating the coding checkout position of described storage data before described storage data write according to described storage data encoding, described coding checkout position writes with described storage data.Described coding checkout position by described storage data write before described flash memory by coding circuit 901 to storage data encode generate, in the cataloged procedure of storage data, produce, the described coding checkout position producing writes flash memory in the lump together with described storage data, in the time need to reading the described storage data that write, described coding checkout position reads out together with described storage data, certainly, described coding checkout position read and write the time consistency that not necessarily storage data described above and described write and read, can exist the regular hour poor.
Coding circuit 901 carries out the comparison of coding checkout position and decoding check digit, and when described more consistent, control device 902 is controlled data link 903 the storage data of described user's request are sent into user side for user, and decode procedure finishes.When described when more inconsistent, control device 902 is controlled described storage data and is entered decoding scheme 906, the storage data generated data errors present information that decoding error detection circuit 9004 in decoding scheme receives described storage data and makes a mistake according to described storage Data Detection, decoding error detection circuit obtains the positional information of the storage data that make a mistake through a series of erroneous calculations, it is error in data positional information, described positional information can be for calculating the parameter of gained, also or for mark errors present label information, in every case within the information of energy misregistration Data Position is all included in this scope.Decoding error correction circuit 9005 in decoding scheme 906, obtain described error in data positional information, and the error in data positional information generating according to described decoding error detection circuit 9004 is determined the position of the data that described storage data make a mistake, the storage data of described position are carried out to error correction to obtain correct storage data, the correct data after error correction is sent to the demand user side of described storage data.Described control device 902 is applicable to higher system clock cycle.As, the inputoutput data bit wide of flash chip is 40M, system clock frequency adopts 4 overtones bands of flash chip inputoutput data bit wide, and 4 system clock cycles are only used the data of reading a 8bits to flash memory, and lower of each clock period need to be carried out the data encoding of 2bits.So, the degree of parallelism of coding circuit 901 and decoding scheme 906 has reduced by 4 times, and resource is greatly reduced.It is minimum that described system clock can also adopt the higher clock period that the use of resource is down to, in the time that clock frequency is flash memory end inputoutput data bandwidth 8 overtones band, each clock period only need to be carried out the coding of 1bit data, now, the coding circuit 901 of error correcting code and the minimum use of decoding error detection circuit 9004 complete parallel resource.The enforcement of embodiment of the present invention interpretation method depends on control device 902; in decoding; adopt the control device 902 of higher system clock cycle can realize the effective utilization to resource; the control of described higher system clock cycle is read for flash memory or when data writing; clock period is herein not limited to described above, can expect can effectively reduce resource use the higher clock period all within protection domain of the present invention.On the other hand, the multiplexing control that storage is adopted higher system clock cycle in decoding is processed when data encoding of coding circuit 901 can adopt equally the control of higher system clock cycle in the coding that writes storage data to flash memory is processed.
Above-mentioned storage data decoding equipment, is suitable for for single channel or multichannel memory device, in the time being hyperchannel, how can adopt the same error correction unit of multiple channel multiplexing.How above-mentioned storage data decording apparatus, for single channel or multichannel memory device, in the time being hyperchannel, can adopt the same error correction unit of multiple channel multiplexing.
Coding circuit 901 mainly carries out check bit calculating to storage data, and control device 902 uses high frequency clock that the data after 8b-2b bit width conversion are sent into coding circuit 901, thereby makes coding circuit a resource shrinkage.Flash memory writes and reads bidirectional traffic with flash memory and all pass through coding circuit 901, thereby realize the multiplexing of coding circuit 901 and decoding error detection circuit 9004: for writing, coding circuit 901 is to the storage data calculation code check bit writing, and described coding checkout position is write to flash memory together with storage data; For reading, coding circuit 901 calculates decoding check bit to the described storage data that read, and the decoding check bit of newly calculating and the coding checkout position of reading from flash memory followed by data are compared, and judges that whether storage data are wrong.If there are data wrong, storage data are sent into decoding scheme 906.If user side is read and sent into data correctly directly by data from the data buffer storage 9001 of coding circuit 901.It is to realize by calculating decoding check bit and contrasting the decoding method whether consistent with coding checkout position that decoding error detection multiplexing and encoding circuit 901 carries out data error detection, whether wrongly data not only can be detected, the necessary parameter information of error correction circuit computational data errors present can also be calculated.Multiplexing and encoding circuit 901, replacing original decoding error detection circuit with coding circuit 901 is in order to reduce resource, therefore, based on the said equipment, after mistake appears in storage data, to calculate through decoding error detection circuit 9004 parameter of decoding error correction circuit 9005 needs, carry out correcting data error by decoding error correction circuit 9005.
Above-mentioned storage data decoding equipment is applicable to the decoding to storing data in all kinds of memory devices, controls as the decoding treatment process of flash memory, readable writable memory and memory disc class etc.For single channel and multichannel memory device, above-mentioned code translator is the optimization to coding circuit and decoding error detection circuit, and the above-mentioned code translator of sampling, by carrying out the multiplexing of decoding processing with coding circuit, effectively reduce the consumption of resource, promoted resource utilization.
One of ordinary skill in the art will appreciate that all or part of flow process realizing in above-described embodiment method, can carry out the hardware that instruction is relevant by computer program to complete, described program can be stored in a computer read/write memory medium, this program, in the time carrying out, can comprise as the flow process of the embodiment of above-mentioned each side method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or random store-memory body (Random Access Memory, RAM) etc.
The above; only for preferably embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with in technical scope that those skilled in the art disclose in the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (14)
1. a storage data decoding method, is characterized in that, described method is by the multiplexing coding circuit decoding error detection circuit of doing, and described method comprises:
The input data of user side are write to flash memory after described coding circuit coding stores;
Described coding circuit coding generates the coding checkout position of storage data, and described coding checkout position is write to described flash memory stores;
In the time of the described storage data of described user side needs, reception control signal, described control signal is indicated the information of the storage data of described user side needs;
Described coding circuit reads described storage data according to described control signal from storage data field, and described storage data are encoded and generated decoding check bit, wherein, described coding circuit is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel;
When obtaining described storage data and writing flash memory by the described coding circuit described coding checkout position obtaining of encoding;
Described coding checkout position and described decoding check bit are compared;
If described more consistent, the described storage data that read are sent to demand data end.
2. storage data decoding method as claimed in claim 1, is characterized in that, described method also comprises: control described storage data and be applicable to the higher clock period.
3. a storage data decoding method, is characterized in that, described method is by the multiplexing coding circuit decoding error detection circuit of doing, and described method comprises:
The input data of user side are write to flash memory after described coding circuit coding stores;
Described coding circuit coding generates the coding checkout position of storage data, and described coding checkout position is write to described flash memory stores;
In the time of the described storage data of described user side needs, reception control signal, described control signal is indicated the information of the storage data of described user side needs;
Described coding circuit reads described storage data according to described control signal from storage data field, and described storage data are encoded and generated decoding check bit, wherein, described coding circuit is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel;
When obtaining described storage data and writing flash memory by the described coding circuit described coding checkout position obtaining of encoding;
Described coding checkout position and described decoding check bit are compared;
If described more inconsistent, described storage data carried out to decoding and obtain the storage data after decoding;
Storage data after described decoding are sent to demand data end.
4. storage data decoding method as claimed in claim 3, is characterized in that, describedly described storage data are carried out to the storage data that decoding obtains after decoding comprises:
Detect described storage data, generate the error in data positional information that described storage data make a mistake;
Determine according to described error in data positional information the position that described storage data make a mistake;
The storage data of described position are carried out to error correction and obtain the storage data after decoding.
5. the storage data decoding method as described in claim 3 or 4, is characterized in that, described method also comprises: control described storage data and be applicable to the higher clock period.
6. a storage data decording apparatus, is characterized in that, described device is by the multiplexing coding circuit decoding error detection circuit of doing, and described device comprises: coding unit, control module and data transfer unit,
Described coding unit, for storing writing flash memory after the input data encoding of user side, and the coding checkout position of generation storage data, described coding checkout position is write to described flash memory stores, in the time that described user side needs described storage data, receive the control signal that described control module sends, read storage data according to described control signal from storage data field, and described storage data are encoded and generated decoding check bit, wherein, described control signal is indicated the information of the storage data of described user side needs;
Described control module, compares described coding checkout position and described decoding check bit for controlling described coding unit;
Described data transfer unit, for reading the coding checkout position of described storage data and described storage data, and describedly sends to demand data end by described storage data when more consistent;
Wherein, described storage data decording apparatus is coding circuit, and described storage data decording apparatus is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel.
7. storage data decording apparatus as claimed in claim 6, is characterized in that: described code translator also comprises decoding error detection unit,
Described decoding error detection unit, for described when more inconsistent, the storage data generated data errors present information that receives described storage data and make a mistake according to described storage Data Detection.
8. storage data decording apparatus as claimed in claim 7, is characterized in that: described code translator also comprises decoding error correction unit,
Described decoding error correction unit, determines for the error in data positional information generating according to described decoding error detection unit the position that described storage data make a mistake, and the storage data of described position are carried out to error correction.
9. the storage data decording apparatus as described in claim 6,7 or 8, is characterized in that: described control module is applicable to higher system clock cycle.
10. a storage data decording apparatus, is characterized in that, described device is by the multiplexing coding circuit decoding error detection circuit of doing, and described device comprises: coding unit, decoding error detection unit, decoding error correction unit, control module and data transfer unit,
Described coding unit, for storing writing flash memory after the input data encoding of user side, and the coding checkout position of generation storage data, described coding checkout position is write to described flash memory stores, in the time that described user side needs described storage data, the control signal that reception control unit sends, read storage data according to described control signal from storage data field, and described storage data are encoded and generated decoding check bit, wherein, described control signal is indicated the information of the storage data of described user side needs;
Described control module, compares described coding checkout position and described decoding check bit for controlling described coding unit;
Described decoding error detection unit, detects described storage data and generates the error in data positional information that described storage data make a mistake when more inconsistent for described;
Described decoding error correction unit, for determining according to described error in data positional information the position that described storage data make a mistake, carries out error correction to the storage data of described position;
Described data transfer unit, under the control of control module, described storage data, described coding checkout position and described decoding check bit being read and transmitted, and sends to demand data end by the described storage data after error correction;
Wherein, described storage data decording apparatus is coding circuit, and described storage data decording apparatus is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel.
11. storage data decording apparatus as claimed in claim 10, is characterized in that:
Described data transfer unit is also stored data described in when more consistent and is sent to demand data end for described.
12. storage data decording apparatus as described in claim 10 or 11, is characterized in that:
Described control module is applicable to higher system clock cycle.
13. 1 kinds of storage data decoding equipment, is characterized in that, described equipment is by the multiplexing coding circuit decoding error detection circuit of doing, and described equipment comprises: coding circuit, decoding scheme, control device and data link,
Described coding circuit, for storing writing flash memory after the input data encoding of user side, generate the coding checkout position of storage data, described coding checkout position is write to described flash memory stores, receive the control signal that described control device sends, described control signal is indicated the information of the storage data of described user side needs, read described storage data according to described control signal from storage data field, and described storage data are encoded and generated the decoding check bit of described storage data, from described flash memory, obtain the coding checkout position of described storage data, coding checkout position described in described decoding check bit sum is compared, determine that whether coding checkout position is more consistent described in described decoding check bit sum, wherein, described coding circuit is positioned on each passage of hyperchannel read-write flash memory device, the multiplexing described coding circuit of described hyperchannel,
Described control device, be used for receiving user side instruction, described user side instruction is used to indicate the demand of user side to described storage data, in the time that described user side needs described storage data, send described control signal to described coding circuit, determine described when more inconsistent at described coding circuit, control described data link described storage data are sent to described decoding scheme, determine describedly when more consistent at described coding circuit, control described data link described storage data are sent to demand data end;
Described data link, for under the control of control device, read and transmit described storage data, described coding checkout position and described decoding check bit, described when more consistent according to the control of described control device, described storage data are sent to demand data end, or described when more inconsistent according to the control of described control device, described storage data are sent to described decoding scheme and the storage data after described decoding scheme decoding are sent to demand data end;
Described decoding scheme, for receiving described storage data, carries out decoding to described storage data and obtains the storage data after decoding.
14. storage data decoding equipment as claimed in claim 13, is characterized in that: described control device is applicable to higher system clock cycle.
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| CN110389854B (en) * | 2019-07-17 | 2023-09-22 | 深圳市盈和致远科技有限公司 | ECC decoding and error correction method, ECC decoding and error correction device and computer readable storage medium |
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