CN113157490B - Flash memory embedded in chip and memory control method - Google Patents
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1456—Hardware arrangements for backup
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
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Abstract
The application relates to the technical field of information storage, and particularly discloses a Flash memory embedded in a chip. The storage controller is used for selecting one storage space according to a preset sequence to read storage data, checking the read storage data when the storage data of the storage space are read, and reading the same data stored in the other storage space when the read storage data have errors to replace the storage data with errors in the original storage space. Because a plurality of storage spaces are adopted to store the same data, when one storage space has data errors, the same data is read from the other storage space for replacement, so that the robustness of the data stored in the Flash memory embedded in the chip is improved.
Description
Technical Field
The invention relates to the technical field of information storage, in particular to a Flash storage controller embedded in a chip and a storage control method.
Background
The IC chip (Integrated Circuit Chip) is a microstructure formed by forming an integrated circuit of a large number of microelectronic devices (transistors, resistors, capacitors, etc.) on a small semiconductor wafer or a dielectric substrate, and then packaging the semiconductor wafer or substrate in a package. The Flash scheme embedded in the IC chip is basically mature, because the logic constitution modes of the Flash logic part and the chip digital function part are different, the Flash logic part and the chip digital function part are generally customized according to the chip manufacturing process, the Flash is a special design, and the Flash is generally used for storing the function execution codes of a CPU or other functional components, so that any problem of data read from the Flash can possibly cause the disorder of a system. Therefore, how to improve the robustness of the Flash memory data embedded in the chip and further improve the robustness of the system on chip is a main research direction in the Flash memory technology embedded in the chip at present.
Disclosure of Invention
The invention mainly solves the technical problem of how to improve the robustness of the Flash memory data embedded in the chip.
According to a first aspect, in one embodiment, a Flash memory embedded in a chip is provided, where the Flash memory includes at least two storage spaces and a storage controller; the storage content of each storage space is the same;
the storage controller is used for selecting one storage space according to a preset sequence to read storage data, checking the read storage data when the storage data of the storage space are read, and reading the same data stored in the other storage space when the read storage data have errors so as to replace the storage data with errors in the original storage space.
In one embodiment, the reading, by the storage controller, the same data stored in the other storage spaces includes:
when the storage controller reads the same data of other storage spaces, the read storage data is checked, and when the storage data read by the storage controller is checked to have errors, the storage space is replaced again to read the same data.
In an embodiment, the code storage structure of each storage space is the same, and the code storage structure includes an arrangement mode including a storage capacity, a Flash storage block and/or a data storage address.
In one embodiment, each of the memory spaces includes at least one memory cell row including a data portion and a redundancy portion; the redundancy part is used for checking and/or correcting the storage content of the data part.
In one embodiment, the redundant portion includes hamming code bits and error flag bits;
the Hamming code bits are used for carrying out Hamming code error checking and correction on the data part, and the error marking bits are used for marking the error state of the data part.
According to a second aspect, an embodiment provides a method for controlling storage of a Flash memory embedded in a chip, which is characterized by comprising:
selecting a storage space of the Flash memory according to a preset sequence; the Flash memory comprises at least two memory spaces, and the memory content of each memory space is the same;
reading the storage data of the selected storage space, and checking the read storage data;
and when the read storage data check result is that the error exists, reading the same data stored in the other storage space, and replacing the storage data with the error in the original storage space.
In an embodiment, the reading the same data stored in the other storage space includes:
and when the same data of other storage spaces are read, checking the read storage data.
In one embodiment, each of the memory spaces includes at least one memory cell row including a data portion and a redundancy portion; the redundant part is used for checking and/or correcting the storage content of the data part; the redundant part comprises Hamming code bits and error mark bits; the Hamming code bits are used for carrying out Hamming code error checking and correction on the data part, and the error marking bits are used for marking the error state of the data part.
In one embodiment, the method further comprises:
when the error of the storage data of at least one storage unit row of one storage space can not be corrected, the storage space is removed from the preset sequence.
According to a third aspect, an embodiment provides a computer readable storage medium having stored thereon a program executable by a processor to implement the method of the first aspect.
According to the Flash memory of the embodiment, the plurality of memory spaces are adopted to store the same data, and when one memory space has a data error, the same data is read from the other memory space to replace, so that the robustness of the data stored in the Flash memory embedded in the chip is improved.
Drawings
FIG. 1 is a schematic diagram of a Flash memory embedded in a chip in an embodiment;
FIG. 2 is a schematic diagram of a memory cell row structure in one embodiment;
FIG. 3 is a schematic diagram of a memory cell row redundancy portion in one embodiment;
FIG. 4 is a flow chart of a method for controlling the memory of a Flash memory embedded in a chip in another embodiment;
FIG. 5 is a schematic diagram of a distribution of Flash memory blocks in one embodiment.
Detailed Description
The invention will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, some operations associated with the present application have not been shown or described in the specification to avoid obscuring the core portions of the present application, and may not be necessary for a person skilled in the art to describe in detail the relevant operations based on the description herein and the general knowledge of one skilled in the art.
Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated.
Flash is a type of memory chip in which data can be modified by a specific program. Flash often means Flash Memory in the electronic and semiconductor fields, known as "Flash Memory" in general, and called Flash EEPROM Memory in full. The Flash memory is also called Flash memory, combines the advantages of ROM and RAM, not only has the performance of Electronic Erasable Programmable (EEPROM), but also can quickly read data (the advantage of NVRAM), so that the data cannot be lost due to power failure.
When a memory device built in an IC chip adopts a Flash technology, the Flash memory device can only be erased and written for a limited time, so that the technical problem of data robustness is always involved when the Flash memory device stores data. Flash memory is typically divided into main memory blocks for storing programs, where programs we write are typically divided into system memory and option bytes, where the system memory stores a boot program for storage in a system memory bootstrapping mode. The option bytes store configuration information of the chip and protection information for the main memory block. In order to ensure the reliability of the stored data, the error correction code is adopted to correct the errors generated in the storage process, and in fact, the probability of generating errors in the data storage in the actual application of the Flash technology is relatively small. A typical Flash consists of a data portion plus a redundancy portion, e.g., a common 140bit wide Flash consists of a 128bit data portion and a 12bit redundancy portion. Redundancy bits are typically used to check and correct errors in the data portion, the cause of errors in the data being typically single bit data flip due to corruption or external interference. When errors occur to single-bit data of Flash, the method for controlling the storage can be timely found and corrected even if errors occur to the data stored in the Flash.
In the embodiment of the invention, a plurality of storage spaces are used for storing the same data, and when one storage space has data errors, the same data is read from the other storage space and replaced, so that the robustness of the data stored in the Flash memory embedded in the chip is improved.
Embodiment one:
referring to fig. 1, a schematic structure diagram of a Flash memory embedded in a chip in an embodiment is shown, where the Flash memory includes at least two memory spaces 10 and a memory controller 20. The storage content of each storage space 10 is the same. The memory controller 20 is configured to select one memory space 10 according to a predetermined sequence, read the memory data of the memory space, check the read memory data, and read the same data of another memory space 10 to replace the memory data of the original memory space 10 with errors when the read memory data has errors. Wherein, the storage controller 20 reads the same data stored in the other storage space 10 includes: when the memory controller 20 reads the same data of the other memory spaces 10, the read memory data is verified, and when the memory data read by the memory controller 20 is verified to have errors, the memory space 10 is replaced again to read the same data.
In one embodiment, the code storage structure of each storage space 10 of the Flash memory is the same, and the code storage structure includes an arrangement mode including a storage capacity, a Flash storage block and a data storage address. In one embodiment, each Flash memory block has a capacity of 8K, each memory space 10 includes two Flash memory blocks, and the Flash memory includes n memory spaces 10. When the Flash memory block in each memory space 10 is not full, the space reserved for storing data is not processed, and in an embodiment, the last line of the reserved space of the Flash memory block which is occupied by the stored data last is reserved as a spare memory space.
Referring to fig. 2, a schematic diagram of a memory cell row structure in an embodiment is shown, where each memory space includes at least one memory cell row, and the memory cell row includes a data portion and a redundancy portion, and the redundancy portion is used to verify and/or correct the memory content of the data portion. In one embodiment, the memory cell row length is 140 bits, the data portion length is 128 bits, and the redundancy portion length is 12 bits. Wherein the general storage data errors are due to corruption or external interference but bit data flip.
Referring to fig. 3, a schematic diagram of a mechanism of a redundant portion of a memory cell row in an embodiment, where the redundant portion of the memory cell row includes hamming code bits for performing hamming code error checking and correction on a data portion, and error flag bits for marking an error state of the data portion. In one embodiment, the Hamming code bit length is 8 bits and the error flag bit length is 4 bits. The Hamming code bit is used for carrying out Hamming code error correction of the data part, and the error marking bit is used for marking the corresponding error condition of 4 words of the data part. The storage mode of the data part and the redundant part is not limited to clear limit distinction, and can be randomly stored according to a certain rule. In one embodiment, if the data portion has an error (typically, the error occurs as a single bit), the corresponding flag bit should be marked as "0", and Flash is erased to default to high, i.e., no error condition, and only "1" can write "0" before being erased, and no reverse operation is possible.
The application considers the technical problem that the Flash memory is read to be damaged by bits in the normal use process of the chip after the chip is subjected to production test, namely, the chip is damaged after being qualified by factory test. The method for adding the backup storage unit, the Hamming code error correction, the error marking and the like to realize the improvement of the robustness of the Flash storage data such as checking errors, correcting errors, marking errors and the like of the Flash storage, and the capability of positioning and correcting errors can be realized even if the read Flash row has bit damage, so that the method has stronger error correction capability and prevents the controller from reading the wrong storage data. Compared with the traditional data verification, the error correction method only can judge the situation of data errors, even if error correction codes are used, the error correction method has certain error correction capability, and once the error correction codes are damaged, the error correction codes are irreparable.
The embodiment of the application discloses a Flash memory embedded in a chip, wherein the Flash memory comprises at least two storage spaces and a storage controller, and the storage content of each storage space is the same. The storage controller is used for selecting one storage space according to a preset sequence to read storage data, checking the read storage data when the storage data of the storage space are read, and reading the same data stored in the other storage space when the read storage data have errors to replace the storage data with errors in the original storage space. Because a plurality of storage spaces are adopted to store the same data, when one storage space has data errors, the same data is read from the other storage space for replacement, so that the robustness of the data stored in the Flash memory embedded in the chip is improved.
Embodiment two:
referring to fig. 4, a flow chart of a method for controlling the memory storage of a Flash memory embedded in a chip in another embodiment includes:
step 110, a storage space is selected.
And selecting one storage space of the Flash memory according to a preset sequence, wherein the Flash memory comprises at least two storage spaces, and the storage content of each storage space is the same. In an embodiment, the preset sequence is sequentially selected according to the arrangement sequence of the storage spaces, for example, the first selection of the storage space 1 to read data is performed, the next selection of the storage space 2 to read data is performed, and the selection is sequentially replaced according to the manner.
Step 120, the read stored data is verified.
And reading the storage data of the selected storage space, and checking whether the read storage data has errors.
Step 130, replacing the storage space when the storage data has errors.
When the read storage data check result is that there is an error, the storage space is replaced to read the data, or the same data stored in another storage space is read.
Step 140, replacing the stored data with error in the original storage space.
And replacing the error-free data stored in the other read storage space with the storage data with errors in the original storage space. When the same data in other storage spaces are read, the read storage data are checked.
In an embodiment, each storage space of the Flash memory comprises at least one storage unit row, and the storage unit row comprises a data part and a redundancy part, wherein the redundancy part is used for checking and/or correcting the storage content of the data part. In one embodiment, the redundant portion includes hamming code bits for hamming code errors and error correction of the data portion and error flag bits for flag the error state of the data portion.
In one embodiment, when the error of the storage data of at least one storage unit row of one storage space is not corrected, the storage space is removed from the preset sequence.
Referring to fig. 5, a schematic distribution diagram of Flash memory blocks in an embodiment is shown, in which a specific implementation process of the method is described below, flash memory blocks 110 with the same capacity (e.g. 8K is a block) are virtually divided in a Flash memory space embedded in a chip, when a program code is downloaded, a zero address is used as a start address (referred to as a memory data a), when a Flash line occupied by the end of the code is not the last line of the block (not occupied by one Flash memory block 110), and a backup code is written from the start address of the next Flash memory block (referred to as a memory data B), which is equivalent to storing two copies of the code. Each memory cell row in Flash memory block 110 has a 128bit data portion, 8bit Hamming code bits, and 4 bit error flag bits. When the system is powered on and started, the program can be read from the code segment in the stored data A by default, and here, the Flash memory is temporarily defaulted to have no damaged bit (after factory test, the Flash can be ensured to be used normally). The bit of some Flash may not be too heavy to finish the service life in advance in the long-term operation process of the system (the connection line or PN junction in most production processes is not affected by impurities, processes and the like to meet the expected requirement, and the Flash has normal functional properties in a short term, and can cause failure after frequent reading and writing). When the Flash controller reads the data in the Flash during the program running process, firstly, whether the word mark part in the error mark bit of the storage unit row is problematic (the position where the word mark part marks the error word) is checked, and meanwhile, whether the data part is problematic or not is checked by calculating the containing plain code. If there is a problem, the corresponding word of the error marking bit is masked, then the corresponding storage unit in the storage data B is read according to the method, if the code segment stored in the corresponding storage unit row in the storage data B is not wrong, the corresponding position is directly replaced, if the code segment of the corresponding storage unit row in the storage data B is also problematic, the data parts of the two wrong storage unit rows in the storage data B and the storage data A are compared, how many bits are inconsistent are checked, if only two bits are inconsistent (each of the storage data A and the storage data B), correct data can be returned by using Hamming code to correct the error bit and mark the word where the error is located, the Hamming code of the 128-bit data part and the redundant part is read, and the Hamming code (mature error correcting technology) has one-bit error correcting capability. If the current memory cell row is bad with two bits (the word marking part marks the word where the first bad bit is located in advance) the word where the second bad bit is located can be confirmed by comparing with the code segment B and marked. Normally, the bit damage probability of Flash is very low, only the field of industrial control with higher requirement can pay attention to the problem, the probability of damaging two bits on one Flash is lower, the probability of damaging two bits of the corresponding word part between the storage data A and the storage data B is basically 0, namely the probability that the whole corresponding word part of two code segments is damaged and cannot be corrected during the service life of Flash is basically impossible.
If the hamming code bit is not matched and the data part code stored data a and the data part code stored data B are matched, i.e. the data part has no bit damage, the bit where the hamming code bit is located has a problem that the hamming code needs to be read by going to the corresponding memory cell row of another code segment. The memory cell row does not have individual error correction capability once the hamming code is in error, and the partial zero clearing of the error flag bit indicates that the memory cell row hamming code is out of order. If the error marking bit is partially damaged, it is basically impossible to damage all four words, if all four bytes of the error marking bit are damaged, then the whole Flash can be considered to be damaged, so that the Hamming code of the memory cell row where the Flash is located is marked with all the four error marking bits as '0', i.e. the Hamming code is not available.
The memory controller encounters error mark bit of error mark with hamming code mismatch or error in the course of reading code, need further error correction processing, thus will influence the reading speed of the normal procedure, and may influence the execution of the procedure, so when the system is reset (except power-on reset), flash will change the default code segment (if the memory data A is read by default before, the memory data B is backed up, the memory data B is regarded as the default read segment after reset, the memory data A is regarded as the code backup segment). By mutually checking the storage problem condition by using the code backup domain, the risk caused by Flash bit damage can be greatly improved, and the condition of error code disorder caused by CPU execution is avoided.
Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by a computer program. When all or part of the functions in the above embodiments are implemented by means of a computer program, the program may be stored in a computer readable storage medium, and the storage medium may include: read-only memory, random access memory, magnetic disk, optical disk, hard disk, etc., and the program is executed by a computer to realize the above-mentioned functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above can be realized. In addition, when all or part of the functions in the above embodiments are implemented by means of a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and the program in the above embodiments may be implemented by downloading or copying the program into a memory of a local device or updating a version of a system of the local device, and when the program in the memory is executed by a processor.
The foregoing description of the invention has been presented for purposes of illustration and description, and is not intended to be limiting. Several simple deductions, modifications or substitutions may also be made by a person skilled in the art to which the invention pertains, based on the idea of the invention.
Claims (3)
1. The Flash memory embedded in the chip is characterized by comprising at least two storage spaces and a storage controller; the storage content of each storage space is the same;
the storage controller is used for selecting one storage space to read storage data according to a preset sequence, checking the read storage data when the storage data of the storage space are read, and reading the same data stored in the other storage space when the read storage data have errors so as to replace the storage data with errors in the original storage space;
the storage controller reads the same data stored in other storage spaces, including:
when the storage controller reads the same data of other storage spaces, checking the read storage data, and when the storage data read by the storage controller is checked to have errors, replacing the storage space again to read the same data;
the code storage structure of each storage space is the same, and the code storage structure comprises a storage capacity, a Flash storage block and/or an arrangement mode of data storage addresses;
each memory space comprises at least one memory cell row, and the memory cell rows comprise a data part and a redundant part; the redundant part is used for checking and/or correcting the storage content of the data part;
the redundant part comprises Hamming code bits and error mark bits;
the Hamming code bits are used for carrying out Hamming code error checking and correction on the data part, and the error marking bits are used for marking the error state of the data part.
2. The method for controlling the storage of the Flash memory embedded in the chip is characterized by comprising the following steps of:
selecting a storage space of the Flash memory according to a preset sequence; the Flash memory comprises at least two memory spaces, and the memory content of each memory space is the same;
reading the storage data of the selected storage space, and checking the read storage data;
when the read storage data check result is that the error exists, the same data stored in the other storage space is read, and the storage data with the error in the original storage space is replaced;
the reading the same data stored in the other storage space includes:
when the same data of other storage spaces are read, checking the read storage data;
each memory space comprises at least one memory cell row, and the memory cell rows comprise a data part and a redundant part; the redundant part is used for checking and/or correcting the storage content of the data part; the redundant part comprises Hamming code bits and error mark bits; the Hamming code bit is used for carrying out Hamming code error checking and correction on the data part, and the error marking bit is used for marking the error state of the data part;
when the error of the storage data of at least one storage unit row of one storage space can not be corrected, the storage space is removed from the preset sequence.
3. A computer readable storage medium having stored thereon a program executable by a processor to implement the method of claim 2.
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226774A (en) * | 2008-02-15 | 2008-07-23 | 祥硕科技股份有限公司 | Method for reducing data error in flash memory device when using copy back instruction |
| CN101587744A (en) * | 2009-06-19 | 2009-11-25 | 上海微小卫星工程中心 | Multi-level data redundancy method of large scale FLASH memory array |
| CN101777013A (en) * | 2009-01-12 | 2010-07-14 | 成都市华为赛门铁克科技有限公司 | Solid state disk and data read-write method |
| CN101853212A (en) * | 2009-03-30 | 2010-10-06 | 芯邦科技（深圳）有限公司 | Data write-in method, data read method and data storage |
| CN102332302A (en) * | 2011-07-19 | 2012-01-25 | 北京时代全芯科技有限公司 | Phase change memory and redundancy replacing method for same |
| CN104750577A (en) * | 2015-04-13 | 2015-07-01 | 中国人民解放军国防科学技术大学 | Random multi-bit fault-tolerant method and device for on-chip large-capacity buffer memory |
| CN105575439A (en) * | 2015-12-15 | 2016-05-11 | 华为技术有限公司 | Memory cell failure error correction method and memory |
| CN109343790A (en) * | 2018-08-06 | 2019-02-15 | 百富计算机技术（深圳）有限公司 | A kind of date storage method based on NAND FLASH, terminal device and storage medium |
| CN109542668A (en) * | 2018-10-29 | 2019-03-29 | 百富计算机技术（深圳）有限公司 | Method of calibration, terminal device and storage medium based on NAND FLASH memory |
| CN111522684A (en) * | 2019-12-31 | 2020-08-11 | 北京航空航天大学 | Method and device for simultaneously correcting soft and hard errors of phase change memory |
| CN111863059A (en) * | 2019-04-29 | 2020-10-30 | 上海磁宇信息科技有限公司 | MRAM chip with dynamic redundancy function |
| CN112181304A (en) * | 2020-09-30 | 2021-01-05 | 浙江大学 | Satellite-borne NAND Flash storage management system |
| CN112309484A (en) * | 2020-01-09 | 2021-02-02 | 成都华微电子科技有限公司 | Design method of storage controller |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7173852B2 (en) * | 2003-10-03 | 2007-02-06 | Sandisk Corporation | Corrected data storage and handling methods |
| JP4041076B2 (en) * | 2004-02-27 | 2008-01-30 | 株式会社東芝 | Data storage system |
| JP4933722B2 (en) * | 2004-06-16 | 2012-05-16 | 富士通株式会社 | Disk control device, disk patrol method, and disk patrol program |
| JP4962060B2 (en) * | 2007-03-14 | 2012-06-27 | 富士通セミコンダクター株式会社 | Parity error recovery circuit |
| KR20150040016A (en) * | 2013-10-04 | 2015-04-14 | 에스케이하이닉스 주식회사 | Semiconductor memory device having a cosmic ray dtector, and electric device including the same, and operating method the same |
| US9405618B2 (en) * | 2014-05-28 | 2016-08-02 | Infineon Technologies Ag | Marker programming in non-volatile memories |
-
2021
- 2021-04-01 CN CN202110355023.4A patent/CN113157490B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226774A (en) * | 2008-02-15 | 2008-07-23 | 祥硕科技股份有限公司 | Method for reducing data error in flash memory device when using copy back instruction |
| CN101777013A (en) * | 2009-01-12 | 2010-07-14 | 成都市华为赛门铁克科技有限公司 | Solid state disk and data read-write method |
| CN101853212A (en) * | 2009-03-30 | 2010-10-06 | 芯邦科技（深圳）有限公司 | Data write-in method, data read method and data storage |
| CN101587744A (en) * | 2009-06-19 | 2009-11-25 | 上海微小卫星工程中心 | Multi-level data redundancy method of large scale FLASH memory array |
| CN102332302A (en) * | 2011-07-19 | 2012-01-25 | 北京时代全芯科技有限公司 | Phase change memory and redundancy replacing method for same |
| CN104750577A (en) * | 2015-04-13 | 2015-07-01 | 中国人民解放军国防科学技术大学 | Random multi-bit fault-tolerant method and device for on-chip large-capacity buffer memory |
| CN105575439A (en) * | 2015-12-15 | 2016-05-11 | 华为技术有限公司 | Memory cell failure error correction method and memory |
| CN109343790A (en) * | 2018-08-06 | 2019-02-15 | 百富计算机技术（深圳）有限公司 | A kind of date storage method based on NAND FLASH, terminal device and storage medium |
| CN109542668A (en) * | 2018-10-29 | 2019-03-29 | 百富计算机技术（深圳）有限公司 | Method of calibration, terminal device and storage medium based on NAND FLASH memory |
| CN111863059A (en) * | 2019-04-29 | 2020-10-30 | 上海磁宇信息科技有限公司 | MRAM chip with dynamic redundancy function |
| CN111522684A (en) * | 2019-12-31 | 2020-08-11 | 北京航空航天大学 | Method and device for simultaneously correcting soft and hard errors of phase change memory |
| CN112309484A (en) * | 2020-01-09 | 2021-02-02 | 成都华微电子科技有限公司 | Design method of storage controller |
| CN112181304A (en) * | 2020-09-30 | 2021-01-05 | 浙江大学 | Satellite-borne NAND Flash storage management system |
Non-Patent Citations (6)
| Title |
|---|
| A Temporal Locality-Aware Page-Mapped Flash Translation Layer;Youngjae Kim;Aayush Gupta;Bhuvan Urgaonkar;;Journal of Computer Science & Technology(第06期);全文 * |
| MobiGemini:Sensitive-Based Data and Resource Protection Framework for Mobile Device;Shuangxi Hong;Chuanchang Liu;Bo Cheng;Bingfei Ren;Junliang Chen;;中国通信(第07期);全文 * |
| 一种基于虚拟页地址映射的NAND Flash管理算法;许娜;彭飞;谭彦亮;苗志富;曹梦丹;;空间控制技术与应用(第03期);全文 * |
| 基于FPGA的NAND Flash ECC校验系统设计与实现;王轩;常亮;李杰;;电子设计工程(第18期);全文 * |
| 基于NAND Flash的转译层的设计;侯超;徐建城;;微型机与应用(第24期);全文 * |
| 基于二维汉明码结构的闪存纠错存储系统;余辉龙;张健;李清;覃翠;赵静;花涛;;微电子学与计算机(第03期);全文 * |
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