CN113157490A - Flash memory embedded in chip and storage control method - Google Patents
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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Abstract
The application relates to the technical field of information storage, and particularly discloses a Flash memory embedded in a chip. The storage controller is used for selecting one storage space according to a preset sequence to read the storage data, checking the read storage data when the storage data of the storage space is read, and reading the same data stored in the other storage space when the read storage data has errors to replace the storage data with errors in the original storage space. Because a plurality of storage spaces are adopted to store the same data, when one storage space has data errors, the same data is read from the other storage space for replacement, so that the robustness of the data stored in the Flash memory embedded in the chip is improved.
Description
Technical Field
The invention relates to the technical field of information storage, in particular to a Flash storage controller embedded in a chip and a storage control method.
Background
An IC Chip (Integrated Circuit Chip) is a micro-structure having a desired Circuit function, which is formed by fabricating an Integrated Circuit formed by a large number of microelectronic devices (transistors, resistors, capacitors, etc.) on a small or several small semiconductor wafers or dielectric substrates, and then encapsulating the Integrated Circuit in a package. At present, a Flash scheme embedded in an IC chip is basically mature, because the logic constitution mode of a Flash logic part and a chip digital function part is different, the Flash logic part is generally customized according to the chip manufacturing process and belongs to a special design, and the Flash is generally used for storing function execution codes of a CPU or other functional components, so that any problem of data read from the Flash can cause disorder of a system. Therefore, how to improve the robustness of the data stored in the chip embedded Flash and further improve the robustness of the system on chip is a main research direction in the chip embedded Flash storage technology at present.
Disclosure of Invention
The invention mainly solves the technical problem of how to improve the robustness of the data stored in the Flash embedded in the chip.
According to a first aspect, an embodiment provides a Flash memory embedded in a chip, where the Flash memory includes at least two memory spaces and a memory controller; the storage content of each storage space is the same;
the storage controller is used for selecting one storage space according to a preset sequence to read the storage data, checking the read storage data when the storage data of the storage space is read, and reading the same data stored in the other storage space when the read storage data has errors so as to replace the original storage data with errors in the storage space.
In one embodiment, the reading of the same data stored in other storage spaces by the storage controller includes:
when the storage controller reads the same data of other storage spaces, the read storage data is verified, and when the storage data read by the storage controller is verified to have errors, the storage spaces are replaced again to read the same data.
In an embodiment, the code storage structures of the storage spaces are the same, and the code storage structures include storage capacity, Flash storage blocks and/or data storage addresses.
In one embodiment, each of the memory spaces includes at least one memory cell row, the memory cell row including a data portion and a redundancy portion; the redundant part is used for checking and/or correcting the storage content of the data part.
In one embodiment, the redundant portion includes hamming code bits and error flag bits;
the Hamming code bit is used for Hamming code error checking and correction of the data part, and the error marking bit is used for marking the error state of the data part.
According to a second aspect, an embodiment provides a method for controlling storage of a Flash memory embedded in a chip, which is characterized by comprising:
selecting a storage space of a Flash memory according to a preset sequence; the Flash memory comprises at least two storage spaces, and the storage content of each storage space is the same;
reading the storage data of the selected storage space, and verifying the read storage data;
and when the read storage data check result shows that the storage data have errors, reading the same data stored in the other storage space, and replacing the original storage data with the errors in the storage space.
In an embodiment, the reading the same data stored in another storage space includes:
and when the same data of other storage spaces are read, checking the read storage data.
In one embodiment, each of the memory spaces includes at least one memory cell row, the memory cell row including a data portion and a redundancy portion; the redundant part is used for checking and/or correcting the storage content of the data part; the redundant portion includes hamming code bits and error flag bits; the Hamming code bit is used for Hamming code error checking and correction of the data part, and the error marking bit is used for marking the error state of the data part.
In one embodiment, the method further comprises:
when the storage data of at least one memory cell row of one memory space is in error and cannot be corrected, the memory space is removed from the preset sequence.
According to a third aspect, an embodiment provides a computer readable storage medium having a program stored thereon, the program being executable by a processor to implement the method of the first aspect.
According to the Flash memory of the embodiment, as the plurality of storage spaces are adopted to store the same data, when data errors occur in one storage space, the same data are read from the other storage space for replacement, so that the robustness of the data stored in the Flash memory embedded in the chip is improved.
Drawings
FIG. 1 is a schematic diagram illustrating a structure of a Flash memory embedded in a chip according to an embodiment;
FIG. 2 is a schematic diagram of an embodiment of a memory cell row structure;
FIG. 3 is a schematic diagram of the mechanism for redundancy in a row of memory cells in one embodiment;
FIG. 4 is a flow chart of a storage control method of a Flash memory embedded in a chip in another embodiment;
FIG. 5 is a schematic diagram illustrating a distribution of Flash memory blocks in an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
Flash is a kind of memory chip, and the data in it can be modified by a specific program. Flash generally means Flash Memory in the field of electronics and semiconductors, that is, Flash Memory is called Flash EEPROM Memory by its full name. The Flash memory is also called as Flash memory, combines the advantages of ROM and RAM, not only has the performance of Electrically Erasable and Programmable (EEPROM), but also can quickly read data (the advantage of NVRAM), so that the data can not be lost due to power failure.
When the storage device built in the IC chip adopts the Flash technology, the technology can only erase and write the storage device for limited times, so the Flash storage data timing can relate to the technical problem of data robustness. Flash storage is generally divided into a main storage block and an information block, the main storage block is used for storing programs, the programs written by us are generally stored in the main storage block, the information block is further divided into a system memory and option bytes, and the system memory stores a starting program used for being stored in a system memory boot mode. Configuration information of the option byte memory chip and protection information of the main memory block. In order to ensure the reliability of the stored data, the common method is to use an error correction code to correct errors generated during the storage process, and in fact, the probability of generating errors in the data storage is still relatively small in the practical application of the Flash technology. In general, Flash is composed of a data portion and a redundancy portion, for example, a common Flash with a bit width of 140 bits is composed of a data portion of 128 bits and a redundancy portion of 12 bits. The redundant bits are generally used to check and correct errors in the data portion, and the cause of the data errors is generally single-bit data inversion caused by damage or external interference. The storage control method is designed for timely finding and correcting errors of data stored in Flash when the errors of single-bit data of the Flash occur.
In the embodiment of the invention, a plurality of storage spaces are adopted to store the same data, when one storage space has data errors, the same data is read from the other storage space and replaced, so that the robustness of the data stored in the Flash memory embedded in the chip is improved.
The first embodiment is as follows:
referring to fig. 1, a schematic structural diagram of a Flash memory embedded in a chip in an embodiment is shown, where the Flash memory includes at least two storage spaces 10 and a storage controller 20. The storage content of each storage space 10 is the same. The memory controller 20 is configured to select one memory space 10 according to a preset sequence to read the memory data, check the read memory data when the memory data of the memory space is read, and read the same data stored in another memory space 10 when the read memory data has an error, so as to replace the memory data in the original memory space 10 that has the error. Wherein, the reading of the same data stored in the other storage spaces 10 by the storage controller 20 includes: when the memory controller 20 reads the same data of the other memory spaces 10, the read memory data is verified, and when the memory data read by the memory controller 20 is verified to have an error, the same data is read by replacing the memory spaces 10 again.
In an embodiment, the code storage structure of each storage space 10 of the Flash memory is the same, and the code storage structure includes the arrangement mode of storage capacity, Flash storage blocks and data storage addresses. In an embodiment, the capacity of each Flash memory block is 8K, each memory space 10 includes two Flash memory blocks, and the Flash memory includes n memory spaces 10. When the Flash memory block in each memory space 10 is not full, the space of the non-stored data is reserved, in an embodiment, the last line of the reserved space of the Flash memory block occupied by the stored data last is reserved as a spare memory space.
Referring to fig. 2, a schematic diagram of a memory cell row structure in an embodiment is shown, where each memory space includes at least one memory cell row, and the memory cell row includes a data portion and a redundancy portion, and the redundancy portion is used to check and/or correct a memory content of the data portion. In one embodiment, the memory cell row length is 140 bits, the data portion length is 128 bits, and the redundancy portion length is 12 bits. In general, the error of the stored data is caused by damage or external interference but the bit data is inverted.
Referring to fig. 3, a schematic diagram of a redundant portion of a memory cell row in an embodiment is shown, where the redundant portion of the memory cell row includes a hamming code bit for hamming code error checking and correcting and an error flag bit for marking an error state of a data portion. In one embodiment, the hamming bit length is 8 bits and the error mark bit length is 4 bits. The Hamming code bit is used for carrying out Hamming code error checking and correcting of the data part, and the error marking bit is used for marking the corresponding error condition of 4 words of the data part. The storage mode of the data part and the redundant part is not limited to clear limit division, and the data part and the redundant part can be stored in a disordered mode according to a certain rule. In one embodiment, if a data portion has an error (generally, the error is a single bit), the corresponding flag bit should be marked as "0", and the Flash is high by default after being erased, that is, no error condition exists, and only "1" can write "0" before being erased, and the reverse operation cannot be performed.
The application considers the technical problem that the Flash memory is read to be damaged in the normal use process of the chip after the chip is subjected to production test, namely the Flash memory is damaged after the chip is qualified through delivery test. The method for adding the backup storage unit, correcting the Hamming code, error marking and the like, which is provided by the application, realizes that the robustness of the Flash storage data is improved by checking errors, correcting errors, marking errors and the like of the Flash storage, the capability of positioning and correcting errors can be realized even if the read Flash line has bit damage, the method has strong error correction capability, and the controller is prevented from reading the wrong storage data. Compared with the traditional data verification, the method can only judge the data error condition, has certain error correction capability even if an error correction code is used, and once the error correction code is partially damaged, the method has the advantages that one part of stored data is simply copied, two parts of storage spaces are mutually combined, and the error marking is carried out, so that the method is a systematically proposed solution based on the whole memory.
The embodiment of the application discloses a Flash memory embedded in a chip, wherein the Flash memory comprises at least two storage spaces and a storage controller, and the storage content of each storage space is the same. The storage controller is used for selecting one storage space according to a preset sequence to read the storage data, checking the read storage data when the storage data of the storage space is read, and reading the same data stored in the other storage space when the read storage data has errors to replace the storage data with errors in the original storage space. Because a plurality of storage spaces are adopted to store the same data, when one storage space has data errors, the same data is read from the other storage space for replacement, so that the robustness of the data stored in the Flash memory embedded in the chip is improved.
Example two:
referring to fig. 4, a schematic flow chart of a method for controlling storage of a Flash memory embedded in a chip in another embodiment includes:
Selecting a storage space of a Flash memory according to a preset sequence, wherein the Flash memory comprises at least two storage spaces, and the storage content of each storage space is the same. In one embodiment, the predetermined sequence is sequentially selected according to the arrangement sequence of the storage spaces, for example, the first time, the number 1 storage space is selected for reading data, the next time, the number 2 storage space is selected for reading data, and the selection is sequentially changed according to the manner.
And reading the storage data of the selected storage space, and checking whether the read storage data has errors.
And step 130, replacing the storage space when the stored data has errors.
When the read storage data check result shows that the storage data are in error, the storage space is replaced to read the data, or the same data stored in another storage space is read.
And step 140, replacing the storage data with the error in the original storage space.
And replacing the error-free data stored in the read other storage space with the error-containing storage data in the original storage space. When the same data of other storage spaces are read, the read storage data are verified.
In one embodiment, each storage space of the Flash memory comprises at least one storage unit row, each storage unit row comprises a data part and a redundant part, and the redundant part is used for checking and/or correcting the storage content of the data part. In one embodiment, the redundant portion includes hamming code bits for hamming code error checking and correction and error flag bits for marking error status of the data portion.
In one embodiment, when the storage data of at least one memory cell row of a memory space is erroneous and cannot be corrected, the memory space is removed from the predetermined sequence.
Referring to fig. 5, a distribution diagram of Flash memory blocks in an embodiment is shown, and a specific implementation process of the method is described below by using a specific embodiment, the Flash memory blocks 110 with the same capacity (for example, a block with a size of 8K) are virtually partitioned in a Flash memory space embedded in a chip, a zero address is used as a start address (referred to as storage data a) when program codes are downloaded, and when a Flash line occupied at the end of a code is not a last line of the block (one Flash memory block 110 is not occupied), backup codes are written in from the start address of a next Flash memory block (referred to as storage data B), which is equivalent to storing two copies of one code. Each memory cell row in Flash memory block 110 has a 128-bit data portion, 8-bit hamming bits, and 4-bit error flag bits. When the system is powered on and started, the program is read from the code segment in the storage data A by default, and here, the Flash memory is defaulted temporarily to have no damaged bit (after factory test, Flash can be ensured to be normally used). Bit positions of some flashes can not bear the burden of ending the service life in advance in the long-term operation process of the system (most of connecting lines or PN junctions in the production process are influenced by impurities, processes and the like and do not meet the expected requirements, normal functional attributes are achieved in the short-term effect, and failure can be caused after frequent reading and writing). When the Flash controller reads data in Flash in the program running process, firstly, whether a word mark part in an error mark position of a memory unit line has a problem (the word mark part marks the position of an error word) is checked, and meanwhile, whether a data part containing a clear code check data part has a problem is calculated. If the data part of the storage data B and the data part of the storage data A with the error are not consistent, if only two bits are inconsistent (one in each of the storage data A and the storage data B), the hamming code can be used for correcting the error bit to return correct data and marking the word where the error is located, and a 128-bit data part and a hamming code of a redundant part are read, wherein the hamming code (mature error correction code technology) has one-bit error correction capability. If the current memory cell line is damaged by two bits (not damaged at the same time, the word marking part marks the word of the first damaged bit in advance), the word of the second damaged bit can be confirmed by comparing with the code B segment, and the marking is carried out. Normally, the bit damage probability of Flash is very low, the problem can be concerned only in the industrial control field with higher requirement, the probability of damaging two bits on one Flash is lower, the probability of damaging two bits is basically 0 in the part corresponding to the word between the storage data A and the storage data B, namely, the probability that all the parts corresponding to the word of the two code segments are damaged and cannot be corrected is basically impossible in the service life specified by the Flash.
If the Hamming code bit is not matched and the code storage data A and the data storage data B of the data part are matched, namely the data part has no bit damage, the bit where the Hamming code bit is positioned has a problem and needs to go to a corresponding storage unit row of another code segment to read the Hamming code. When the Hamming code has an error, the memory cell row does not have the independent error correction capability, and the Hamming code of the memory cell row is indicated to be invalid by clearing all the error marking bit parts. If the error marking bit part is damaged, all four characters are basically not damaged, if the situation that all four bytes of the error marking bit are damaged is really met, the whole Flash can be considered to be damaged, so that the four error marking bits are all '0' to mark the Hamming code error of the memory unit row where the Flash is located, namely the Hamming code is unavailable.
When a memory controller encounters an error mark bit with an error mark of Hamming code mismatch or error in the process of reading a code, further error correction processing is needed, which affects the reading speed of a normal program and further may affect the execution of the program, so that when a system is reset (except power-on reset), Flash changes a default code segment (if the memory data A is read by default before, the memory data B is backed up, and after the reset, the memory data B is used as a default reading segment and the memory data A is used as a code backup segment). By utilizing the code backup domain to mutually check the storage problem condition, the risk caused by Flash bit damage can be greatly improved, and the condition that the CPU executes wrong codes disorderly is avoided.
Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by computer programs. When all or part of the functions of the above embodiments are implemented by a computer program, the program may be stored in a computer-readable storage medium, and the storage medium may include: a read only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to realize the above functions. For example, the program may be stored in a memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above may be implemented. In addition, when all or part of the functions in the above embodiments are implemented by a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and may be downloaded or copied to a memory of a local device, or may be version-updated in a system of the local device, and when the program in the memory is executed by a processor, all or part of the functions in the above embodiments may be implemented.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A Flash memory embedded in a chip is characterized by comprising at least two memory spaces and a memory controller; the storage content of each storage space is the same;
the storage controller is used for selecting one storage space according to a preset sequence to read the storage data, checking the read storage data when the storage data of the storage space is read, and reading the same data stored in the other storage space when the read storage data has errors so as to replace the original storage data with errors in the storage space.
2. The Flash memory of claim 1 wherein the memory controller reads the same data stored in the other memory spaces, including:
when the storage controller reads the same data of other storage spaces, the read storage data is verified, and when the storage data read by the storage controller is verified to have errors, the storage spaces are replaced again to read the same data.
3. The Flash memory according to claim 1, wherein the code storage structure of each of the storage spaces is the same, the code storage structure comprising an arrangement comprising storage capacity, Flash memory blocks and/or data storage addresses.
4. The Flash memory according to claim 1, wherein each of the memory spaces comprises at least one memory cell row, the memory cell row comprising a data portion and a redundant portion; the redundant part is used for checking and/or correcting the storage content of the data part.
5. The Flash memory of claim 4 wherein the redundant portion includes Hamming bits and error flag bits;
the Hamming code bit is used for Hamming code error checking and correction of the data part, and the error marking bit is used for marking the error state of the data part.
6. A storage control method for a Flash memory embedded in a chip is characterized by comprising the following steps:
selecting a storage space of a Flash memory according to a preset sequence; the Flash memory comprises at least two storage spaces, and the storage content of each storage space is the same;
reading the storage data of the selected storage space, and verifying the read storage data;
and when the read storage data check result shows that the storage data have errors, reading the same data stored in the other storage space, and replacing the original storage data with the errors in the storage space.
7. The method of claim 6, wherein said reading the same data stored in another of said storage spaces comprises:
and when the same data of other storage spaces are read, checking the read storage data.
8. The method of claim 7, wherein each of the memory spaces comprises at least one row of memory cells, the row of memory cells comprising a data portion and a redundant portion; the redundant part is used for checking and/or correcting the storage content of the data part; the redundant portion includes hamming code bits and error flag bits; the Hamming code bit is used for Hamming code error checking and correction of the data part, and the error marking bit is used for marking the error state of the data part.
9. The method of claim 8, further comprising:
when the storage data of at least one memory cell row of one memory space is in error and cannot be corrected, the memory space is removed from the preset sequence.
10. A computer-readable storage medium, characterized in that the medium has stored thereon a program which is executable by a processor to implement the method according to any one of claims 6-9.
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