CN112000511A - ECC circuit optimization method based on Hamming code - Google Patents
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Abstract
The invention discloses an ECC circuit optimization method based on Hamming codes, which comprises the following steps: analyzing the encoding or decoding circuit only comprising a two-input one-output exclusive-OR gate, and determining the key path of the encoding or decoding circuit. And reconstructing a critical path of the coding or decoding circuit by adopting at least one exclusive-OR gate with the input end more than or equal to three. The multi-input exclusive-OR gate is adopted to reconstruct the original encoding and decoding circuit which is only composed of two input exclusive-OR gates, so that the gate-level delay on the key path of the reconstructed encoding and decoding circuit is effectively reduced. Therefore, fewer devices and smaller device area are adopted, and the time delay of the ECC coding and decoding circuit based on the Hamming code is obviously reduced compared with that of the traditional method.
Description
Technical Field
The invention relates to the field of monitoring and error correction of data code streams, in particular to an ECC circuit optimization method based on Hamming codes.
Background
An ECC algorithm based on hamming codes is often applied to communications, is mainly used for monitoring and correcting data code streams in communications, and is a common coding algorithm. The encoding is realized based on the exclusive or of each data bit, and the principle and the realization mode are relatively simple. In conventional circuit design, only one logic gate of a two-input exclusive-or gate is needed to realize the whole encoding and decoding. However, although the circuit design is simple in structure, the performance of the circuit design is often not optimal, and the circuit design is only suitable for the design with low performance requirements.
Disclosure of Invention
In order to solve the defects in the prior art.
The embodiment of the invention discloses an ECC circuit optimization method based on Hamming codes, which comprises the following steps: analyzing the encoding or decoding circuit only comprising a two-input one-output exclusive-OR gate, and determining the key path of the encoding or decoding circuit. And reconstructing a critical path of the coding or decoding circuit by adopting at least one exclusive-OR gate with the input end more than or equal to three.
In one possible embodiment, the specific method for analyzing the encoding or decoding circuit including only two-input one-output exclusive or gates to determine the critical path of the encoding or decoding circuit is as follows: and applying excitation to the coding or decoding circuit, and determining the logic path with the longest delay from the input end to the output end on the coding or decoding circuit as a critical path.
In one possible embodiment, the reconstruction is performed such that the gate-level delay of the reconstructed critical path is smaller than the gate-level delay of the critical path of the encoding or decoding circuit including only two-input one-output exclusive-or gates
The embodiment of the application has the advantages that: the multi-input exclusive-OR gate is adopted to reconstruct the original encoding and decoding circuit which is only composed of two input exclusive-OR gates, so that the gate-level delay on the key path of the reconstructed encoding and decoding circuit is effectively reduced. Therefore, fewer devices and smaller device area are adopted, and the time delay of the ECC coding and decoding circuit based on the Hamming code is obviously reduced compared with that of the traditional method.
Drawings
FIG. 1 is a flowchart of an ECC circuit optimization method based on Hamming codes according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the decoded output of code0 in a conventional decoding method;
FIG. 3(a) is a schematic diagram of a first ECC decoded block in the decoded output of code0 in the conventional decoding method;
FIG. 3(b) is a schematic diagram of a second ECC decoded block in the decoded output of code0 in the conventional decoding method;
FIG. 4 is a schematic diagram of a first two-input-one-output XOR gate of a comparative example of the present invention;
FIG. 5 is a schematic diagram of a second two-input-one-output XOR gate of a comparative example of the present invention;
FIG. 6 is a schematic diagram of the decoding output of code0 in the decoding method according to the embodiment of the present invention;
FIG. 7 is a schematic diagram of a third two-input-one-output XOR gate according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a three-input-one-output XOR gate according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a four-input one-output xor gate according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The common technical defect of the prior art that the whole coding or decoding circuit is realized by only a two-input one-output exclusive-or gate, so that the coding and decoding process needs to experience multi-stage gate-level delay.
The embodiment of the application adopts at least one exclusive-OR gate with the input end more than or equal to three to form a key path of an encoding or decoding circuit. Namely, a two-input one-output exclusive-OR gate and an exclusive-OR gate with an input end larger than or equal to three, even all exclusive-OR gates with input ends larger than or equal to three form a key path of an encoding or decoding circuit. Therefore, compared with the key path of the coding or decoding circuit which is formed by only two-input one-output exclusive-OR gates, the gate-level delay on the key path is reduced, and the overall delay of the circuit is reduced. The purpose of original coding or decoding is achieved by adopting less device number and/or smaller design area, and the optimal design of a circuit with better performance is achieved.
Before the optimization of the critical path is carried out, the coding or decoding circuit only comprising the two-input one-output exclusive-or gate needs to be analyzed to find the critical path in the circuit.
Except for optimizing the critical path of the coding or decoding circuit, the other logic paths except the critical path in the logic path of the coding or decoding circuit can be reconstructed by adopting at least one exclusive-or gate with the input end being more than or equal to three, so that the gate-level delay on the reconstructed logic path is less than the gate-level delay on the corresponding logic path only comprising two-input one-output exclusive-or gate.
For some coding or decoding circuits, the gate-level delay of the ECC circuit can be effectively reduced only by arranging at least one exclusive-OR gate with the input end being more than or equal to three on the critical path.
Specifically, fig. 1 is a flowchart of an ECC circuit optimization method based on hamming codes according to an embodiment of the present invention, as shown in fig. 1.
In step S101, the encoding or decoding circuit is analyzed to find a critical path of the circuit.
Specifically, a path with the longest delay from the input end to the output end of the coding or decoding circuit is found by applying test excitation to the input end of the coding or decoding circuit, and the path is determined to be a critical path. There is one and only one critical path in the encoding or decoding circuit.
In step S102, at least one xor gate with an input terminal greater than or equal to three is used as a logic gate on the critical path, and the critical path is optimized, that is, the critical path of the encoding or decoding circuit is reconstructed by using at least one xor gate with an input terminal greater than or equal to three.
The gate-level delay of the key path of the reconstructed coding or decoding circuit is smaller than that of the original coding or decoding circuit which only comprises a two-input one-output exclusive-OR gate.
A Hamming code decoding circuit based on 64-bit data bits and 8-bit coding bits obtains a critical path of the circuit through analysis, and the critical path constructed by a traditional decoding method only comprising a two-input one-output exclusive-OR gate is used as a comparison example I to be compared with the embodiment of the application.
Comparative example 1
Fig. 2 is a schematic diagram of the decoded output of code0 in the conventional decoding method. As shown in fig. 2, the circuit comprises a first ECC decoding block, a second ECC decoding block and a last stage exclusive or gate XOR. FIG. 3(a) is a schematic diagram of a first ECC decoding block; fig. 3(b) is a schematic diagram of a second ECC decoding block. As shown in fig. 3(a), the first ECC decoding block consists of 35 two-input one-output exclusive or gates, and has 36-bit input terminals and 1-bit output terminal Z0. As shown in fig. 3(b), the second ECC decoding block is composed of 35 two-input one-output xor gates, and has 36-bit input terminals and 1-bit output terminal Z1. The output terminal Z0 and the output terminal Z1 perform an exclusive or operation as input signals of the final stage exclusive or gate XOR in fig. 2 to output the decoding result o _ code <0> from the output terminal Z.
The gate level logic expression for the decoded output bit o _ code <0> is as follows:
wherein d isi(i ═ 0, 1.. 63) denotes the original data bits, parityi(i ═ 0,1,. 7) denotes the coded bits. Therefore, when analyzing a hamming code decoding circuit that only includes 64-bit data bits and 8-bit code bits with two-input-one-output exclusive or gates, the conventional decoding method as shown in fig. 2 will generate a maximum of 7 gate-level delay on the critical path.
A schematic diagram of the first two-input one-output XOR2_1 in fig. 3(a) is shown in fig. 4. The MOS transistor comprises 4 MOS transistors M4-1, M4-2, M4-3, M4-4 and 1 NOT 4-1. The input signal A4-1 and the input signal A4-2 are respectively input from two input terminals of the XOR2_1, and the output signal Z4 is output from an output terminal of the XOR2_ 1. A4-2 is inverted by NOT4-1 to output signal A4-2B. A4-1 is connected with a grid of M4-1, a grid of M4-2, a source of M4-3 and a drain of M4-4; a4-2 is connected to the drain of M4-2 and the gate of M4-4; A4-2B accesses the source of M4-1 and the gate of M4-3; the drain of M4-1, the source of M4-2, the drain of M4-3 and the source of M4-4 are connected to each other, and the connection is output as Z4.
The schematic diagram of the second two-input-one-output exclusive or gate XOR2_2 in fig. 3(a) is shown in fig. 5. The MOS transistor comprises 4 MOS transistors M5-1, M5-2, M5-3, M5-4 and 2 NOTs 5-1 and NOT 5-2. The input signal A5-1 and the input signal A5-2 are respectively input from two input terminals of the XOR2_2, and the output signal Z5 is output from an output terminal of the XOR2_ 2. A5-2 is inverted by NOT5-1 to output signal A5-2B. A5-1 is connected with a grid of M5-1, a grid of M5-2, a source of M5-3 and a drain of M5-4; a5-2 is connected to the drain of M5-2 and the gate of M5-4; A5-2B accesses the source of M5-1 and the gate of M5-3; the drain of M5-1, the source of M5-2, the drain of M5-3 and the source of M5-4 are connected, and NOT5-2 inverts the state of the connection point and outputs the inverted state as Z5. Although the number of devices and the connection relationship are different from those of the XOR2_1, the XOR2_1 and the XOR2_2 each implement exclusive or logic.
For ease of comparison with the examples of the present invention. Except for the decoded output bit o _ code <0>, the gate-level logic expression of the remaining 7-bit decoded output of the decoding circuit is as follows:
example one
After analyzing the hamming code decoding circuit of 64-bit data bits and 8-bit coding bits, the critical path of the hamming code decoding circuit is obtained, and the critical path of the hamming code decoding circuit is reconstructed by adopting a certain number of three-input exclusive or gates and four-input exclusive or gates, so that a code0 decoding output schematic diagram shown in fig. 6 is obtained. Specifically, as shown in fig. 6, the schematic diagram is composed of 30 two-input one-output xor gates, 10 three-input one-output xor gates, and 7 four-input one-output xor gates; there are 72 inputs including 64 data bits and 8 coded bits, and a 1-bit output Z. The decoding result o _ code <0> is output from the output terminal Z.
The gate level logic expression for the decoded output bit o _ code <0> is as follows:
wherein d isi(i ═ 0, 1.. 63) denotes the original data bits, parityi(i ═ 0,1,. 7) denotes the coded bits. Therefore, as shown in the schematic diagram of fig. 6, the critical path will generate a gate delay of 5 levels at most.
In particular, the schematic diagram of the third two-input one-output exclusive or gate XOR2_3 in fig. 6 is shown in fig. 7. The MOS transistor comprises 4 MOS transistors M7-1, M7-2, M7-3, M7-4 and 2 NOTs 7-1 and NOT 7-2. The input signal A7-1 and the input signal A7-2 are respectively input from two input terminals of the XOR2_3, and the output signal Z7 is output from an output terminal of the XOR2_ 3. A7-1 is inverted by NOT7-1 to output a signal A7-1B; a7-2 is inverted by NOT7-2 to output signal A7-2B. A7-1 is connected to the grid of M7-1 and the grid of M7-4; A7-1B accesses the grid of M7-2 and the grid of M7-3;a7-2 is connected to the source of M7-1 and the drain of M7-2; A7-2B is connected to the drain of M7-3 and the source of M7-4; the drain of M7-1, the source of M7-2, the source of M7-3 and the drain of M7-4 are connected to each other, and the connection is output as Z7.
Fig. 6 shows a schematic diagram of a three-input one-output exclusive or gate XOR3, as shown in fig. 8. The MOS transistor comprises 8 MOS transistors M8-1, M8-2, M8-3, M8-4, M8-5, M8-6, M8-7, M8-8 and 5 NOT8-1, NOT8-2, NOT8-3, NOT8-4 and NOT 8-5. Input signal A8-1, input signal A8-2, and input signal A8-3 are input by three inputs of XOR3, respectively, and output signal Z8 is output by an output of XOR 3. A8-1 is inverted by NOT8-1 to output a signal A8-1B; a8-2 is inverted by NOT8-2 to output a signal A8-2B; a8-3 is inverted by NOT8-3 to output signal A8-3B. A8-2B accesses the grid of M8-1 and the grid of M8-4; a8-2 is connected into the grid of M8-2 and the grid of M8-3; a8-3 is connected with the source of M8-1 and the drain of M8-2; A8-3B is connected to the drain of M8-3 and the source of M8-4; the drain of M8-1, the source of M8-2, the source of M8-3 and the drain of M8-4 are connected to each other, and the state of the connection point is used as an internal signal a 8-23. a8-23 is inverted by NOT8-4 to output signals a8-23 b. a8-23 is connected into a grid of M8-5 and a grid of M8-8; a8-23b is connected into the grid of M8-6 and the grid of M8-7; a8-1 is connected with the source of M8-5 and the drain of M8-6; A8-1B is connected to the drain of M8-7 and the source of M8-8; the drain of M8-5, the source of M8-6, the source of M8-7 and the drain of M8-8 are connected, and NOT8-5 inverts the state of the connection point and outputs the inverted state as Z8.
Fig. 4 shows a schematic diagram of a four-input one-output exclusive or gate XOR4, as shown in fig. 9. The MOS transistor comprises 12 MOS transistors M9-1, M9-2, M9-3, M9-4, M9-5, M9-6, M9-7, M9-8, M9-9, M9-10, M9-11, M9-12 and 9 NOT9-1, NOT9-2, NOT9-3, NOT9-4, NOT9-5, NOT9-6, NOT9-7, NOT9-8 and NOT 9-9. The input signal A9-1, the input signal A9-2, the input signal A9-3 and the input signal A9-4 are respectively input from four input ends of an XOR4, and the output signal Z9 is input from four input ends of an XOR4The output of XOR 4. A9-1 is inverted by NOT9-1 to output a signal A9-1B; a9-2 outputs a signal A9-2B after being inverted by NOT9-2, and A9-2F is output by inverting A9-2B by NOT 9-3; a9-3 outputs a signal A9-3B after being inverted by NOT9-4, and A9-3F is output by inverting A9-3B by NOT 9-5; a9-4 is inverted by NOT9-6 to output signal A9-4B. A9-1 is connected to the grid of M9-1 and the grid of M9-4; A9-1B accesses the grid of M9-2 and the grid of M9-3; A9-2B is connected to the source of M9-1 and the drain of M9-2; A9-2F is connected to the drain of M9-3 and the source of M9-4; the drain of M9-1, the source of M9-2, the source of M9-3 and the drain of M9-4 are connected to each other, and the state of the connection point is used as an internal signal a 9-12. a9-12 is inverted by NOT9-7 to output a9-12 b. A9-4 is connected to the grid of M9-5 and the grid of M9-8; A9-4B is connected to the grid of M9-6 and the grid of M9-7; A9-3B is connected to the source of M9-5 and the drain of M9-6; A9-3F is connected to the drain of M9-7 and the source of M9-8; the drain of M9-5, the source of M9-6, the source of M9-7 and the drain of M9-8 are connected and the state of the connection is used as an internal signal a 9-34. a9-34 outputs signals a9-34b after NOT9-8 is inverted. a9-12 is connected into the grid of M9-9 and the grid of M9-12; a9-12b is connected into the grid of M9-10 and the grid of M9-11; a9-34b is connected to the source of M9-9 and the drain of M9-10; a9-34 is connected to the drain of M9-11 and the source of M9-12; the drain of M9-9, the source of M9-10, the source of M9-11 and the drain of M9-12 are connected, and NOT9-9 inverts the state of the connection point and outputs the inverted state as Z9.
Except for the decoded output bit o _ code <0>, the gate-level logic expression of the remaining 7-bit decoded output of the decoding circuit is as follows:
the output delays in comparative example one and example one were compared as shown in the following table:
TABLE 1
As can be seen from Table 1, the use of the method of example one reduced the delay time by a minimum of 11.6% as compared with the use of comparative example one of the conventional method.
Further, the devices used in the 8-bit output encoding circuit portion of the decoding circuit in the comparative example one and the example one were compared as shown in the following table:
TABLE 2
As can be seen from table 2, the first example of the present application uses a smaller number of devices than the first comparative example using the conventional method.
The method for optimizing the ECC circuit based on the Hamming code provided by the embodiment of the invention adopts fewer devices and smaller device area, so that the time delay of the ECC coding and decoding circuit based on the Hamming code is obviously reduced compared with the traditional method.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. An ECC circuit optimization method based on Hamming codes, which is characterized by comprising the following steps:
analyzing an encoding or decoding circuit only comprising a two-input one-output exclusive-OR gate, and determining a critical path of the encoding or decoding circuit;
and reconstructing a critical path of the coding or decoding circuit by using at least one exclusive-OR gate with the input end being more than or equal to three.
2. The method of claim 1, wherein analyzing the encoding or decoding circuit that comprises only two-input one-output exclusive-or gates determines a critical path of the encoding or decoding circuit, specifically:
and applying excitation to the coding or decoding circuit, and determining the logic path with the longest delay from the input end to the output end on the coding or decoding circuit as a critical path.
3. The method of claim 1 or2, wherein the reconstructed critical path has a gate-level delay that is less than a gate-level delay of the critical path of the encoding or decoding circuit that includes only two-input-one-output exclusive-OR gates.
4. The method of claim 1 or2, wherein the xor gate with the input equal to or greater than three comprises a three-input one-output xor gate; the three-input one-output exclusive-OR gate comprises 8 MOS transistors M8-1, M8-2, M8-3, M8-4, M8-5, M8-6, M8-7, M8-8 and 5 NOT gates NOT8-1, NOT8-2, NOT8-3, NOT8-4 and NOT 8-5; wherein the content of the first and second substances,
an input signal A8-1, an input signal A8-2 and an input signal A8-3 are respectively input from three input ends; a8-1 is inverted by NOT8-1 to output a signal A8-1B; a8-2 is inverted by NOT8-2 to output a signal A8-2B; a8-3 is inverted by NOT8-3 to output a signal A8-3B; A8-2B accesses the grid of M8-1 and the grid of M8-4; a8-2 is connected into the grid of M8-2 and the grid of M8-3; a8-3 is connected with the source of M8-1 and the drain of M8-2; A8-3B is connected to the drain of M8-3 and the source of M8-4; the drain of M8-1, the source of M8-2, the source of M8-3 and the drain of M8-4 are connected, and the state of the connection point is used as an internal signal a 8-23; a8-23 is inverted by NOT8-4 to output signals a8-23 b; a8-23 is connected into a grid of M8-5 and a grid of M8-8; a8-23b is connected into the grid of M8-6 and the grid of M8-7; a8-1 is connected with the source of M8-5 and the drain of M8-6; A8-1B is connected to the drain of M8-7 and the source of M8-8; the drain of M8-5, the source of M8-6, the source of M8-7 and the drain of M8-8 are connected, and NOT8-5 inverts the state of the connection point and outputs the inverted signal as an output signal Z8.
5. The method of claim 1 or2, wherein the xor gate with the input terminal equal to or greater than three comprises a four-input one-output xor gate; the four-input one-output exclusive-OR gate comprises 12 MOS transistors M9-1, M9-2, M9-3, M9-4, M9-5, M9-6, M9-7, M9-8, M9-9, M9-10, M9-11, M9-12 and 9 NOT9-1, NOT9-2, NOT9-3, NOT9-4, NOT9-5, NOT9-6, NOT9-7, NOT9-8 and NOT 9-9; wherein the content of the first and second substances,
an input signal A9-1, an input signal A9-2, an input signal A9-3 and an input signal A9-4 are respectively input from four input ends; a9-1 is inverted by NOT9-1 to output a signal A9-1B; a9-2 outputs a signal A9-2B after being inverted by NOT9-2, and A9-2F is output by inverting A9-2B by NOT 9-3; a9-3 outputs a signal A9-3B after being inverted by NOT9-4, and A9-3F is output by inverting A9-3B by NOT 9-5; a9-4 is inverted by NOT9-6 to output a signal A9-4B; a9-1 is connected to the grid of M9-1 and the grid of M9-4; A9-1B accesses the grid of M9-2 and the grid of M9-3; A9-2B is connected to the source of M9-1 and the drain of M9-2; A9-2F is connected to the drain of M9-3 and the source of M9-4; the drain of M9-1, the source of M9-2, the source of M9-3 and the drain of M9-4 are connected, and the state of the connection point is used as an internal signal a 9-12; a9-12 is inverted by NOT9-7 to output a9-12 b; a9-4 is connected to the grid of M9-5 and the grid of M9-8; A9-4B is connected to the grid of M9-6 and the grid of M9-7; A9-3B is connected to the source of M9-5 and the drain of M9-6; A9-3F is connected to the drain of M9-7 and the source of M9-8; the drain of M9-5, the source of M9-6, the source of M9-7 and the drain of M9-8 are connected, and the state of the connection point is used as an internal signal a 9-34; a9-34 outputs signals a9-34b after NOT9-8 is inverted; a9-12 is connected into the grid of M9-9 and the grid of M9-12; a9-12b is connected into the grid of M9-10 and the grid of M9-11; a9-34b is connected to the source of M9-9 and the drain of M9-10; a9-34 is connected to the drain of M9-11 and the source of M9-12; the drain of M9-9, the source of M9-10, the source of M9-11 and the drain of M9-12 are connected, and NOT9-9 inverts the state of the connection point and outputs the inverted signal as an output signal Z9.
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