CN104539297A - Four-stage production line-based high-speed QC-LDPC coder in DTMB - Google Patents

Abstract

The invention provides a four-stage production line-based high-speed QC-LDPC coder in a DTMB. The four-stage production line-based high-speed QC-LDPC coder comprises a sparse matrix and vector multiplier, an I-type backward iteration circuit, a high-density matrix and vector multiplier and an II-type backward iteration circuit. The sparse matrix and vector multiplier realizes a spare matrix and vector multiplication, the high-density matrix and vector multiplier realizes high-density matrix and vector multiplication, and the I-type backward iteration circuit and the II-type backward iteration circuit realize backward iteration operation. The whole coding process is divided into four stages of production line. The 4/5 code rate high-speed QC-LDPC code in the DTMB, provided by the invention, has the advantages of simple structure, low cost, large handling capacity and the like.

Description

High-speed QC-LDPC encoder based on four-stage assembly line in DTMB

Technical Field

The invention relates to the field of channel coding, in particular to a high-speed QC-LDPC encoder based on a four-stage pipeline in a DTMB system.

Background

A Low-Density Parity-Check (LDPC) code is one of the efficient channel coding techniques, and a Quasi-Cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a special LDPC code. The generation matrix G and the check matrix H of the QC-LDPC code are both arrays formed by cyclic matrixes, have the characteristic of segmented circulation, and are called the QC-LDPC code. The first row of the circulant matrix is the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the last row by 1 bit, so that the circulant matrix is completely characterized by its first row. Typically, the first row of the circulant matrix is referred to as its generator polynomial.

The DTMB standard adopts a QC-LDPC code in a system form, the left half part of a generating matrix G of the DTMB standard is an identity matrix, and the right half part of the generating matrix G is a cyclic matrix G with e multiplied by c b multiplied by b orders_i,j(0≤i<e,e≤j<t, t ═ e + c), as follows:

where I is a b × b order identity matrix and 0 is a b × b order all-zero matrix. Successive b rows and b columns of G are referred to as block rows and block columns, respectively. From equation (1), G has e block rows and t block columns. The DTMB standard employs a QC-LDPC code with code rate η of 4/5 for which t 59, e 48, c 11, and b 127.

The existing solution of the 4/5 code rate QC-LDPC encoder in the DTMB standard is a serial encoder based on 11I-Type Shift Register plus Accumulator (SRAA-I) circuits. The serial encoder, which is composed of 11 SRAA-I circuits, completes the encoding within 6096 clock cycles. This scheme requires 2794 registers, 1397 two-input and gates, and 1397 two-input xor gates, and also requires 67056-bit ROM to store the generator polynomial of the circulant matrix. This solution has two drawbacks: firstly, a large amount of memory is needed, resulting in high circuit cost; and secondly, information bits are input serially, so that the encoding speed is low.

Disclosure of Invention

The invention provides a high-speed QC-LDPC encoder based on a four-level pipeline, aiming at the technical problems that the existing implementation scheme of an 4/5 code rate QC-LDPC encoder in a DTMB system has the defects of high cost and low encoding speed.

As shown in fig. 2, the high-speed QC-LDPC encoder based on four-stage pipeline in DTMB system mainly consists of 4 parts: sparse matrix and vector multiplier, I-type backward iteration circuit, high-density matrix and vector multiplier and II-type backward iteration circuit. The encoding process is completed in 4 steps: step 1, calculating vectors f and w by using a sparse matrix and a vector multiplier; step 2, calculating vectors q and x by using an I-type backward iteration circuit; step 3, calculating partial check vector p by using multiplier of high density matrix and vector_x(ii) a And 4, calculating the vector y by using a II type backward iterative circuit, and performing exclusive OR on the vector y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

The 4/5 code rate high-speed QC-LDPC encoder in the DTMB system has a simple structure, and can reduce memories under the condition of obviously improving the encoding speed, thereby reducing the cost and improving the throughput.

The advantages and methods of the present invention will be further understood by reference to the following detailed description and drawings.

Drawings

FIG. 1 is a schematic diagram of an approximate lower triangular check matrix after row-column swapping;

FIG. 2 is a four-stage pipeline based QC-LDPC encoding process;

FIG. 3 is a functional block diagram of a loop left shift accumulator RLA circuit;

FIG. 4 is a high density matrix and vector multiplier consisting of 1 RLA circuit;

FIG. 5 is a sparse matrix and vector multiplier;

FIG. 6 shows the connection relationship between each multi-input XOR gate and the register in the multiplier of the sparse matrix and the vector;

FIG. 7 is a type I backward iteration circuit;

FIG. 8 shows the block positions of the non-zero circulant matrix in the matrix Q and its circulant right shift;

FIG. 9 is a type II backward iteration circuit;

FIG. 10 shows the block positions of the non-zero circulant matrix in matrix Y and its circulant right shift;

fig. 11 summarizes the hardware resources and processing time required for each encoding step of the encoder and the entire encoding process.

Detailed Description

The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.

The row weight and column weight of the circulant matrix are the same and denoted as w. If w is 0, then the circulant matrix is an all-zero matrix. If w is 1, the circulant matrix is replaceable, called the permutation matrix, which can be obtained by right-shifting the identity matrix I cyclically by a few bits. The check matrix H of the QC-LDPC code is a cyclic matrix H of order b x b formed by c x t_j,k(1. ltoreq. j. ltoreq. c, 1. ltoreq. k. ltoreq. t, t. e + c) in the following array:

in general, any cyclic matrix in the check matrix H is either an all-zero matrix (w ═ 0) or a permutation matrix (w ═ 1). Let the cyclic matrix H_j,kFirst line g of_j,k＝(g_j,k,1,g_j,k,2,…,g_j,k,b) Is its generator polynomial of which g_j,k,m0 or 1 (1. ltoreq. m. ltoreq. b). Since H is sparse, g_j,kThere are only 1 ' and even no ' 1 '.

For the QC-LDPC code with 4/5 code rates in the DTMB system, the first 48 block columns of H correspond to an information vector a, and the last 11 block columns of H correspond to a check vector p. With 127 bits as one segment, the information vector a is equally divided into 48 segments, i.e. a ═ a₁,a₂,…,a₄₈) (ii) a The check vector p is equally divided into 11 segments, i.e. p ═ p (p)₁,p₂,…,p₁₁)。

Performing row exchange and column exchange operation on the check matrix H, and converting the check matrix H into an approximate lower triangular shape H_ALTAs shown in fig. 1. The process of the line-column exchange is as follows: step 1, exchanging block columns, wherein the front 9 block columns and the rear 48 block columns are exchanged; step 2, block line exchange is carried out, and the first line is moved to the last line; and step 3, circularly and leftwards shifting all permutation matrixes by 1 bit respectively.

In fig. 1, the unit of all matrices is b 127 bits instead of 1 bit. A is composed of 9 × 48 cyclic matrices of 127 × 127 th order, B is composed of 9 × 02 cyclic matrices of 127 × 1127 th order, T is composed of 9 × 9 cyclic matrices of 127 × 127 th order, C is composed of 2 × 48 cyclic matrices of 127 × 127 th order, D is composed of 2 × 2 cyclic matrices of 127 × 127 th order, and E is composed of 2 × 9 cyclic matrices of 127 × 127 th order. T is a lower triangular matrix, and u-2 reflects a check matrix H_ALTProximity to the lower triangular matrix. In fig. 1, the matrices a and C correspond to the information vector a, and the matrices B and D correspond to a portion of the check vector p_x＝(p₁,p₂) The matrices T and E correspond to the remaining check vectors p_y＝(p₃,p₄,…,p₁₁)。p＝(p_x,p_y). The matrix and the vector satisfy the following relations:

p_x ^Τ＝Φ(ET^-1Aa^Τ+Ca^Τ) (3)

p_y ^Τ＝T^-1(Aa^Τ+Bp_x ^Τ) (4)

wherein Φ is (ET)^-1B+D)^-1Upper label of^ΤAnd^-1respectively representing transpose and inverse. As is well known, the inverse, product, and sum of the circulant matrix remains a circulant matrix. Thus, Φ is also an array consisting of a circulant matrix. Although both matrices E, T, B and D are sparse matrices, in general Φ is no longer sparse but rather high densityIn (1).

Let f^T＝Aa^T，q^T＝T^-1f^T，w^T＝Ca^T，x^T＝Eq^T+w^T，p_x ^T＝Φx^T，y^T＝T^–1Bp_x ^TAnd p_y ^T＝q^T+y^T. Vectors f and w can be calculated by:

${\left[\begin{array}{cc}f& w\end{array}\right]}^T=\left[\begin{array}{c}A\\ C\end{array}\right]a^T=F{a}^T---\left(5\right)$

wherein,

$F=\left[\begin{array}{c}A\\ C\end{array}\right]---\left(6\right)$

q^T＝T^–1f^Tand x^T＝Eq^T+w^TThe following matrix equation can be constructed:

$\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]{\left[\begin{array}{cc}q& x\end{array}\right]}^T=Q{\left[\begin{array}{cc}q& x\end{array}\right]}^T={\left[\begin{array}{cc}f& w\end{array}\right]}^T---\left(7\right)$

wherein,

$Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]---\left(8\right)$

once p is calculated_x，y^T＝T^–1Bp_x ^TRewritable as follows:

[B T][p_x y]^Τ＝Y[p_x y]^Τ＝0 (9)

wherein,

Y＝[B T] (10)

since Q and Y are lower triangular matrices as well as T, both [ Q x ] in equation (7) and Y in equation (9) can be calculated in backward iteration.

Φ relates to the multiplication of the high density matrix with the vector, F relates to the multiplication of the sparse matrix with the vector, and Q and Y relate to backward iterative computations. From the above discussion, a four-stage pipeline based QC-LDPC encoding process can be presented, as shown in FIG. 2.

p_x ^T＝Φx^TIs equivalent to p_x＝xΦ^T. Let x be (x)₁,x₂,…,x_u×b). Defining a u-bit vector s_n＝(x_n,x_n+b,…,x_n+(u-1)×b) Wherein n is more than or equal to 1 and less than or equal to b. Let phi_j(1. ltoreq. j. ltoreq. u) is represented by^TAll circulant matrix generator polynomials in block j of (1) to form a u x b order matrix. Then there is

p_j＝(…((0+s₁Φ_j)^ls(1)+s₂Φ_j)^ls(1)+…+s_bΦ_j)^ls(1) (11)

Wherein, the upper label^ls(1)Indicates the left of the cycleShift by 1.

From equation (11), a round-shift-Left-Accumulator (RLA) circuit can be obtained, as shown in fig. 3. The index of the lookup table is a u-bit vector s_nLook-up table L_jStoring variable u-bit vectors and fixed phi in advance_jAll possible products of, therefore, 2^ub-bit Read-Only Memory (ROM). b bit register R₁,R₂,…,R_uVector segments x for buffer vectors x, respectively₁,x₂,…,x_uB bit register R_u+jFor storing p_xIs verified by the verification segment p_j. 1 RLA circuit calculates the vector p_jB clock cycles are required.

For DTMB systems, p is calculated using 2 RLA circuits_x＝(p₁,p₂) Is a reasonable scheme, such as the high-density matrix and vector multiplier shown in fig. 4. The high-density matrix and vector multiplier consists of 2 lookup tables L₁,L₂4 127 bit registers R_3,1,R_3,2,…,R_3,4And 2 127 bit two-input XOR gates X_3,1,X_3,2And (4) forming. Look-up table L₁,L₂Storing variable 2-bit vectors and fixed matrices phi, respectively₁,Φ₂All possible products of, register R_3,1,R_3,2Vector segments x for buffer vectors x, respectively₁,x₂Register R_3,3,R_3,4Respectively for storing p_xIs verified by the verification segment p₁,p₂. The 2 RLA circuits use 127 two-input exclusive or gates, 1016 bits of ROM and 254 registers. 2 RLA circuits calculate the vector p_x127 clock cycles are required. Vector p is calculated using a high density matrix and vector multiplier_xThe steps are as follows:

step 1, zero clearing register R_3,3,R_3,4Input vector segment x₁,x₂Store them in the register R respectively_3,1,R_3,2Performing the following steps;

step 2, register R_3,1,R_3,2Simultaneously circulating left for 1 time, XOR gate X_3,1,X_3,2Respectively to the lookup table L₁,L₂Output of and register R_3,3,R_3,4The contents of (A) are XOR-ed, and the XOR results are circularly left-shifted 1 time and then stored back to the register R respectively_3,3,R_3,4；

Step 3, repeating step 2 127 times, and after finishing, the register R_3,3,R_3,4The contents of the storage are respectively the check segment p₁,p₂Which constitutes part of a check vector p_x。

Let f be (f)₁,f₂,…,f₉) And w ═ f₁₀,f₁₁) Then [ f w ]]＝(f₁,f₂,…,f₁₁). According to formula (5), f_jIs the jth block row of the matrix F and a^TProduct of, i.e.

$f_j=H_{j,1}{a}_1^T+H_{j,2}{a}_2^T+...+H_{j,i}{a}_i^T+...+H_{j,48}{a}_{48}^T---\left(12\right)$

Wherein i is more than or equal to 1 and less than or equal to 48, and j is more than or equal to 1 and less than or equal to 11. f. of_jN bit f of_j,n(1. ltoreq. n.ltoreq.127) is

$\begin{array}{c}{f}_{j,n}=g_{j,1}^{\mathrm{rs}(n-1)}{a}_1+g_{j,2}^{\mathrm{rs}(n-1)}{a}_2+...+g_{j,i}^{\mathrm{rs}(n-1)}{a}_i+...g_{j,48}^{\mathrm{rs}(n-1)}{a}_{48}\\ =g_{j,1}{a}_1^{\mathrm{ls}(n-1)}+g_{j,2}{a}_2^{\mathrm{ls}(n-1)}+...+g_{j,i}{a}_i^{\mathrm{ls}(n-1)}+...+g_{j,48}{a}_{48}^{\mathrm{ls}(n-1)}\end{array}---\left(13\right)$

Wherein, the upper label^rs(n–1)And^ls(n–1)respectively representing a cyclic right shift by n-1 bits and a cyclic left shift by n-1 bits. Since any circulant matrix generates a polynomial g_j,iWith only a small number of '1's, or even all zeros, the inner product in equation (13) can be scaled by decimation of the loop left shift registerHead-sum, as shown in fig. 5 as a sparse matrix and vector multiplier. The sparse matrix and vector multiplier consists of 59 127-bit registers R_1,1,R_1,2,…,R_1,59And 11 multiple input XOR gates X_1,1,X_1,2,…,X_1,11And (4) forming. Register R_1,1,R_1,2,…,R_1,48For loading and looping left-shifting information segments a₁,a₂,…,a₄₈Register R_1,49,R_1,50,…,R_1,59For storing [ f w]Vector segment f of₁,f₂,…,f₁₁. The sparse connection in fig. 5 depends on all circulant matrix generator polynomials in matrix F. If g is_j,i,m1 (1. ltoreq. m.ltoreq.127), then the information section a_iIs connected to the exclusive or gate X_1,j. Thus, register R_1,iDepends on the position of the non-zero elements of all circulant matrix generator polynomials in the ith block column of the matrix F, and a multi-input xor gate X_1,jDepends on the position of the non-zero elements of all circulant matrix generator polynomials in the jth block row of the matrix F. Fig. 6 shows the connection relationship between each multi-input exclusive or gate and the register in the multiplier of the sparse matrix and the vector. Since all cyclic matrix generator polynomials in F have a total of 127 '1', the sparse matrix and vector multiplier needs to compute F simultaneously using 250 two-input xor gates_1,n,f_2,n,…,f_11,n. f and w may be counted in 127 clock cycles. The steps of calculating vectors f and w using a sparse matrix and vector multiplier are as follows:

step 1, input information segment a₁,a₂,…,a₄₈Store them in the register R respectively_1,1,R_1,2,…,R_1,48Performing the following steps;

step 2, register R_1,1,R_1,2,…,R_1,48Simultaneously circulating left for 1 time, XOR gate X_1,1,X_1,2,…,X_1,11Shift the XOR result to the left into register R, respectively_1,49,R_1,50,…,R_1,59Performing the following steps;

step 3, repeating step 2 127 times, and after finishing, the register R_1,49,R_1,50,…,R_1,59The contents of the memory are respectively vector segments f₁,f₂,…,f₁₁They constitute vectors f and w.

Equation (7) implies a backward iterative operation, and the vectors q and x must be solved segment by segment. Definition [ q x]＝(q₁,q₂,…,q₁₁) And initialized to all zeros. First, q is₁Exactly equal to f₁. Secondly, q is₂Is the 2 nd block row and vector [ Q x ] of the matrix Q]^TProduct of f₂And (2) of (1). Then, q₃Is block 3 row and vector [ Q x ] of matrix Q]^TProduct of f₃And (2) of (1). Repeating the above process until q is calculated₁₁A type I backward iterative circuit as shown in fig. 7. The I-type backward iterative circuit consists of 11 127-bit registers R_2,1,R_2,2,…,R_2,11And 10 multiple input modulo-2 adders A_2,2,A_2,3,…,A_2,11And (4) forming.

To calculate q_j(j is 1. ltoreq. j.ltoreq.11) as an example. The non-zero circulant matrix in the check matrix H is typically a circularly right shifted version of the identity matrix. Suppose there are N non-zero circulants in the jth block row of the matrix Q, and their cyclic right shift numbers are s respectively_j,k1,s_j,k2,…,s_j,kN(1≤k1,k2,…,kN<j) In that respect Then the process of the first step is carried out,

$\begin{array}{c}{q}_j=f_j+I^{\mathrm{rs}\left(s_{j,k1}\right)}{q}_{k1}+I^{\mathrm{rs}\left(s_{j,k2}\right)}{q}_{k2}+...+I^{\mathrm{rs}\left(s_{j,\mathrm{kN}}\right)}{q}_{\mathrm{kN}}\\ =f_j+q_{k1}^{\mathrm{ls}\left(s_{j,k1}\right)}+q_{k2}^{\mathrm{ls}\left(s_{j,k2}\right)}+...+q_{\mathrm{kN}}^{\mathrm{ls}\left(s_{j,\mathrm{kN}}\right)}\end{array}---\left(14\right)$

since N is small, equation (14) can be computed by a multiple input modulo-2 adder that shifts the input cycle to the left in 1 clock cycle. Therefore, the calculation of vector [ q x ] takes 11 clock cycles. Since the matrix Q has 29 non-zero cyclic matrices in common, the type I backward iterative circuit needs to use (β -c) b 2286 two-input xor gates.

The matrix Q is composed of 11 × 11 cyclic matrices Q of 127 × 127 orders_j,k(j is more than or equal to 1 and less than or equal to 11, and k is more than or equal to 1 and less than or equal to 11). Non-zero circulant matrix Q_j,kThe number of cyclic right shifts relative to an identity matrix of order 127 × 127 is s_j,k，0≤s_j,k<127. For the convenience of description, the cyclic right shift number of the all-zero circulant matrix with respect to the 127 × 127 th circulant matrix is denoted as s_j,k'-'. In FIG. 7, a non-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jPerforming XOR operation, wherein the vector segment corresponding to the all-zero cyclic matrix does not participate in the XOR operation, A_2,jIs calculated as q_jIs stored in a register R_2,jIn (1). Fig. 8 shows the block positions of the non-zero circulant matrix in the matrix Q and its circulant right-shift number. The steps for computing the vectors q and x using a type I backward iterative circuit are as follows:

step 1, inputting vector segment f₁Dividing the vector segment q₁＝f₁Into a register R_2,1Performing the following steps;

step 2, inputting vector segment f_jNon-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jPerforming XOR operation to obtain result q_jIs stored in a register R_2,jWherein j is more than or equal to 2 and less than or equal to 11, and k is more than or equal to 1<j，0≤s_j,k<127；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for 10 times, and finally, obtaining a register R_2,1,R_2,2,…,R_2,11Stored are respectively vector segments q₁,q₂,…,q₁₁They constitute vectors q and x.

Equation (9) also implies a backward iterative operation, and the vector y must be solved segment by segment. Definition y ═ (y)₁,y₂,…,y₉) And initialized to all zeros. First, y₁Is the 1 st block row of matrix Y and vector p_x y]^TThe product of the two. Second, y₂Is the 2 nd block row of matrix Y and vector p_x y]^TThe product of the two. Repeating the above process until y is calculated₉Up to this point, a type II backward iteration circuit as shown in fig. 9. The type II backward iterative circuit consists of 11 127 bit registers R_4,1,R_4,2,…,R_4,11And 9 multiple-input modulo-2 adders A_4,1,A_4,2,…,A_4,9And (4) forming. The calculation of vector y takes 9 clock cycles in total. Since matrix Y has 27 non-zero circulant matrices in common, the backward iteration circuit of type II needs to use (ξ -2 c +2u) b 1143 two-input xor gates. The matrix Y is composed of 9 × 11 cyclic matrices Y of 127 × 127 orders_j,k(j is more than or equal to 1 and less than or equal to 9, and k is more than or equal to 1 and less than or equal to 11). Non-zero circulant matrix Y_j,kThe number of cyclic right shifts relative to an identity matrix of order 127 × 127 is s_j,k，0≤s_j,k<127. Fig. 10 shows the block positions of the non-zero circulant matrix in matrix Y and its circulant right-shift number. The steps for computing the vector y using a type II backward iterative circuit are as follows:

step 1, inputting a check segment p₁,p₂Store them in the register R respectively_4,10,R_4,11Performing the following steps;

step 2, non-zero circulant matrix Y_j,kCorresponding vector segment p_kOr y_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_4,jIn the process, an XOR operation is performed, and the result y of the XOR operation_jIs stored in a register R_4,jWherein j is more than or equal to 1 and less than or equal to 9, and k is more than or equal to 1<1+j，0≤s_j,k<127；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for 9 times, and finally, obtaining a register R_4,1,R_4,2,…,R_4,9Stored are respectively vector segments y₁,y₂,…,y₉They constitute a vector y.

The invention provides a high-speed QC-LDPC coding method based on a four-level pipeline, which is suitable for 4/5 code rate QC-LDPC codes in a DTMB system, and the coding steps are described as follows:

step 1, calculating vectors f and w by using a sparse matrix and a vector multiplier;

step 2, calculating vectors q and x by using an I-type backward iteration circuit;

step 3, calculating partial check vector p by using multiplier of high density matrix and vector_x；

And 4, calculating the vector y by using a II type backward iterative circuit, and performing exclusive OR on the vector y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

Fig. 11 summarizes the hardware resource consumption and processing time required by each encoding step of the encoder and the entire encoding process.

As can be seen from fig. 11, when the pipeline is full, the whole encoding process needs 175 clock cycles of max (t-c + b, c, u + b), which is less than 6096 clock cycles needed by the serial encoding method based on 11 SRAA-I circuits. The former has a coding speed 34.8 times that of the latter.

The existing solution of 4/5 code rate QC-LDPC encoder in DTMB standard requires 2794 registers, 1397 two-input AND gates and 1397 two-input XOR gates, and 67056 bit ROM to store the generator polynomial of the circulant matrix. The invention requires 11121 registers, 0 two-input and gates and 3933 two-input xor gates, and only 1016 bits of ROM are required.

In conclusion, compared with the conventional serial SRAA method, the method has the advantages of high coding speed, low memory consumption and the like.

The above description is only one embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can change or replace the present invention within the technical scope of the present invention without creative efforts, and the present invention shall be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope defined by the claims.

Claims (7)

1. A high-speed QC-LDPC encoder based on four-stage pipeline in DTMB, the check matrix H of 4/5 code rate QC-LDPC code is an array formed by c x t b-order cyclic matrixes, wherein c is 11, t is 59, b is 127, e is t-c is 48, the check matrix H is transformed into an approximate lower triangular shape by row-column exchange and can be divided into 6 sub-matrixes, $H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right],$ a is a matrix composed of 9 × 48B × B-order cyclic matrices, B is a matrix composed of 9 × 02B × 1B-order cyclic matrices, T is a lower triangular matrix composed of 9 × 9B × B-order cyclic matrices, C is a matrix composed of 2 × 48B × B-order cyclic matrices, D is a matrix composed of 2 × 2B × B-order cyclic matrices, E is a matrix composed of 2 × 9B × B-order cyclic matrices, and Φ ═ is (ET)^-1B+D)^-1Is composed of 2 × 2 b-order cyclic matrices, phi_jIs formed by phi^TAll circulant matrix generator polynomials in the jth block column of (2 x b), wherein superscript^ΤAnd^-1respectively representing transposition and inversion, j is more than or equal to 1 and less than or equal to 2, $Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]$ is composed of 11 × 11 b × b order cyclic matrices Q_j,kWherein I is an identity matrix, 0 is an all-zero matrix, 1 is equal to or more than j is equal to or less than 11,1 is equal to or more than k is equal to or less than 11, and a non-zero cyclic matrix Q_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<b，Y＝[B T]Is composed of 9 × 11 b × b order cyclic matrices Y_j,kWherein j is more than or equal to 1 and less than or equal to 9, k is more than or equal to 1 and less than or equal to 11, and a non-zero cyclic matrix Y_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<B, A and C correspond to the information vector a, and the matrixes B and D correspond to a part of the check vector p_xThe matrices T and E correspond to the remaining check vectors p_yCheck vector p ═ p (p)_x,p_y) The information vector a is equally divided into 48 segments with b bits as one segment, i.e. a ═ a₁,a₂,…,a₄₈) The check vector p is equally divided into 11 segments, i.e. p ═ p (p)₁,p₂,…,p₁₁)，p_x＝(p₁,p₂)，p_y＝(p₃,p₄,…,p₁₁) The vector f is equally divided into 9 segments, i.e. f ═ f (f)₁,f₂,…,f₉) The vector w is equally divided into 2 segments, i.e. w ═ f₁₀,f₁₁)，[f w]＝(f₁,f₂,…,f₁₁) The vector q is equally divided into 9 segments, i.e. q ═ q (q)₁,q₂,…,q₉) The vector x is equally divided into 2 segments, i.e. x ═ p₁₀,p₁₁)，[q x]＝(q₁,q₂,…,q₁₁) The vector y is equally divided into 9 segments, i.e. y ═ y (y)₁,y₂,…,y₉) Characterised in that the encoder comprises the following components:

the sparse matrix and vector multiplier consists of 59 127-bit registers R_1,1,R_1,2,…,R_1,59And 11 multiple input XOR gates X_1,1,X_1,2,…,X_1,11A component for calculating vectors f and w;

the I-type backward iterative circuit consists of 11 127-bit registers R_2,1,R_2,2,…,R_2,11And 10 multiple input modulo-2 adders A_2,2,A_2,3,…,A_2,11A component for computing vectors q and x;

the multiplier of high-density matrix and vector is composed of 2 lookup tables L₁,L₂4 127 bit registers R_3,1,R_3,2,…,R_3,4And 2 127 bit two-input XOR gates X_3,1,X_3,2Composition for calculating partial check vector p_xLook-up table L₁,L₂Storing variable 2-bit vectors and fixed matrices phi, respectively₁,Φ₂All possible products of (c);

a type II backward iterative circuit consisting of 11 127-bit registers R_4,1,R_4,2,…,R_4,11And 9 multiple-input modulo-2 adders A_4,1,A_4,2,…,A_4,9Composition for calculating the XOR of the vector y, y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

2. The high-speed QC-LDPC encoder according to claim 1, wherein said row-column switching process is as follows:

step 1, exchanging block columns, wherein the front 9 block columns and the rear 48 block columns are exchanged;

step 2, block line exchange is carried out, and the first line is moved to the last line;

and step 3, circularly and leftwards shifting all permutation matrixes by 1 bit respectively.

3. The high-speed QC-LDPC encoder according to claim 1, wherein said sparse matrix and vector multiplier is configured to compute vectors f and w as follows:

step 1, input information segment a₁,a₂,…,a₄₈Store them in the register R respectively_1,1,R_1,2,…,R_1,48Performing the following steps;

step 2, register R_1,1,R_1,2,…,R_1,48Simultaneously circulating left for 1 time, XOR gate X_1,1,X_1,2,…,X_1,11Shift the XOR result to the left into register R, respectively_1,49,R_1,50,…,R_1,59Performing the following steps;

step 3, repeating step 2 127 times, and after finishing, the register R_1,49,R_1,50,…,R_1,59The contents of the memory are respectively vector segments f₁,f₂,…,f₁₁They constitute vectors f and w.

4. The high-speed QC-LDPC encoder according to claim 1, wherein said type I backward iterative circuit calculates vectors q and x as follows:

step 1, inputting vector segment f₁Will beVector segment q₁＝f₁Into a register R_2,1Performing the following steps;

step 2, inputting vector segment f_jNon-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jPerforming XOR operation to obtain result q_jIs stored in a register R_2,jWherein j is more than or equal to 2 and less than or equal to 11, and k is more than or equal to 1<j，0≤s_j,k<127；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for 10 times, and finally, obtaining a register R_2,1,R_2,2,…,R_2,11Stored are respectively vector segments q₁,q₂,…,q₁₁They constitute vectors q and x.

5. The high-speed QC-LDPC encoder according to claim 1, wherein said high density matrix and vector multiplier calculates vector p_xThe steps are as follows:

step 1, zero clearing register R_3,3,R_3,4Input vector segment x₁,x₂Store them in the register R respectively_3,1,R_3,2Performing the following steps;

step 2, register R_3,1,R_3,2Simultaneously circulating left for 1 time, XOR gate X_3,1,X_3,2Respectively to the lookup table L₁,L₂Output of and register R_3,3,R_3,4The contents of (A) are XOR-ed, and the XOR results are circularly left-shifted 1 time and then stored back to the register R respectively_3,3,R_3,4；

Step 3, repeating step 2 127 times, and after finishing, the register R_3,3,R_3,4The contents of the storage are respectively the check segment p₁,p₂Which form part of a check vector p_x。

6. The high-speed QC-LDPC encoder based on four-stage pipeline in DTMB according to claim 1, wherein said type II backward iterative circuit calculates vector y as follows:

step 1, inputting a check segment p₁,p₂Store them in the register R respectively_4,10,R_4,11Performing the following steps;

step 2, non-zero circulant matrix Y_j,kCorresponding vector segment p_kOr y_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_4,jIn the process, an XOR operation is performed, and the result y of the XOR operation_jIs stored in a register R_4,jWherein j is more than or equal to 1 and less than or equal to 9, and k is more than or equal to 1<2+j，0≤s_j,k<127；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for 9 times, and finally, obtaining a register R_4,1,R_4,2,…,R_4,9Stored are respectively vector segments y₁,y₂,…,y₉They constitute a vector y.

7. A high-speed QC-LDPC coding method based on four-stage pipeline in DTMB, the check matrix H of 4/5 code rate QC-LDPC code is an array formed by c x t b-order cyclic matrixes, wherein c is 11, t is 59, b is 127, e is t-c is 48, the check matrix H is transformed into approximate lower triangular shape by row-column exchange and can be divided into 6 sub-matrixes, $H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right],$ a is composed of 9 × 48B × B-order cyclic matrices, B is composed of 9 × 02B × B-order cyclic matrices, lower triangular matrix T is composed of 9 × 9B × B-order cyclic matrices, C is composed of 2 × 48B × B-order cyclic matrices, D is composed of 2 × 2B × B-order cyclic matrices, and E is composed of 2 × 9B × B-order cyclic matricesb × b order circulant matrix, phi ═ ET^-1B+D)^-1Is composed of 2 × 2 b-order cyclic matrices, phi_jIs formed by phi^TAll circulant matrix generator polynomials in the jth block column of (2 x b), wherein superscript^ΤAnd^-1respectively representing transposition and inversion, j is more than or equal to 1 and less than or equal to 2, $Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]$ is composed of 11 × 11 b × b order cyclic matrices Q_j,kWherein I is an identity matrix, 0 is an all-zero matrix, 1 is equal to or more than j is equal to or less than 11,1 is equal to or more than k is equal to or less than 11, and a non-zero cyclic matrix Q_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<b，Y＝[B T]Is composed of 9 × 11 b × b order cyclic matrices Y_j,kWherein j is more than or equal to 1 and less than or equal to 9, k is more than or equal to 1 and less than or equal to 11, and a non-zero cyclic matrix Y_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<B, A and C correspond to the information vector a, and the matrixes B and D correspond to a part of the check vector p_xThe matrices T and E correspond to the remaining check vectors p_yCheck vector p ═ p (p)_x,p_y) The information vector a is equally divided into 48 segments with b bits as one segment, i.e. a ═ a₁,a₂,…,a₄₈) The check vector p is equally divided into 11 segments, i.e. p ═ p (p)₁,p₂,…,p₁₁)，p_x＝(p₁,p₂)，p_y＝(p₃,p₄,…,p₁₁) The vector f is equally divided into 9 segments, i.e. f ═ f (f)₁,f₂,…,f₉) The vector w is equally divided into 2 segments, i.e. w ═ f₁₀,f₁₁)，[f w]＝(f₁,f₂,…,f₁₁) The vector q is equally divided into 9 segments, i.e. q ═ q (q)₁,q₂,…,q₉) The vector x is equally divided into 2 segments, i.e. x ═ p₁₀,p₁₁)，[q x]＝(q₁,q₂,…,q₁₁) The vector y is equally divided into 9 segments, i.e. y ═ y (y)₁,y₂,…,y₉) Characterized in that said coding method comprises the following steps:

step 1, calculating vectors f and w by using a sparse matrix and a vector multiplier;

step 2, calculating vectors q and x by using an I-type backward iteration circuit;

step 3, calculating partial check vector p by using multiplier of high density matrix and vector_x；

And 4, calculating the vector y by using a II type backward iterative circuit, and performing exclusive OR on the vector y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。