CN104579365A - High-speed QC-LDPC (quasi-cyclic low-density parity-check) encoder based on four-level assembly lines - Google Patents

Abstract

The invention provides a high-speed QC-LDPC (quasi-cyclic low-density parity-check) encoder based on four-level assembly lines. The encoder comprises a multiplier for sparse matrixes and vectors, an I-type backward iterative circuit, a multiplier for high-density matrixes and vectors and an II-type backward iterative circuit. The multiplier for the sparse matrixes and vectors is used for multiplication of the sparse matrixes and vectors, the multiplier for the high-density matrixes and vectors is used for multiplication of the high-density matrixes and vectors, and each of the I-type backward iterative circuit and the II-type backward iterative circuit is used for backward iterative operation. The whole encoding process is divided into the four-level assembly lines. The high-speed QC-LDPC encoder has the advantages of simple structure, low cost, high throughput capacity and the like.

Description

High-speed QC-LDPC encoder based on four-stage production line

Technical Field

The invention relates to the field of channel coding, in particular to a high-speed QC-LDPC encoder based on a four-stage pipeline in a communication system.

Background

A Low-Density Parity-Check (LDPC) code is one of the efficient channel coding techniques, and a Quasi-Cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a special LDPC code. The generation matrix G and the check matrix H of the QC-LDPC code are both arrays formed by cyclic matrixes, have the characteristic of segmented circulation, and are called the QC-LDPC code. The first row of the circulant matrix is the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the last row by 1 bit, so that the circulant matrix is completely characterized by its first row. Typically, the first row of the circulant matrix is referred to as its generator polynomial.

The communication system usually adopts QC-LDPC code of system form, its left half of generating matrix G is a identity matrix, the right half is by e x c b x b rank cyclic matrix G_i,j(0≤i<e,e≤j<t, t ═ e + c), as follows:

where I is a b × b order identity matrix and 0 is a b × b order all-zero matrix. Successive b rows and b columns of G are referred to as block rows and block columns, respectively. From equation (1), G has e block rows and t block columns.

Currently, QC-LDPC codes widely employ a serial encoder based on c Type-I shift Register plus Accumulator (SRAA-I) circuits. The serial encoder composed of c SRAA-I circuits completes encoding within e multiplied by b clock cycles. This scheme requires 2 × c × b registers, c × b two-input and gates, and c × b two-input xor gates, and also requires an e × c × b bit ROM to store the generator polynomial of the circulant matrix. This solution has two drawbacks: firstly, a large amount of memory is needed, resulting in high circuit cost; and secondly, information bits are input serially, so that the encoding speed is low.

Disclosure of Invention

The invention provides a high-speed QC-LDPC encoder based on a four-level pipeline, aiming at the technical problems that the existing implementation scheme of the QC-LDPC encoder in a communication system has the defects of high cost and low encoding speed.

As shown in fig. 2, the high-speed QC-LDPC encoder based on four-stage pipeline in communication system mainly consists of 4 parts: the device comprises a sparse matrix and vector multiplier, a type I backward iteration circuit, a high-density matrix and vector multiplier and a type II backward iteration circuit. The encoding process is completed in 4 steps: step 1, using sparse matrices and vectorsThe multiplier calculates vectors f and w; step 2, calculating vectors q and x by using an I-type backward iteration circuit; step 3, calculating partial check vector p by using multiplier of high density matrix and vector_x(ii) a And 4, calculating the vector y by using a II type backward iterative circuit, and performing exclusive OR on the vector y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

The high-speed QC-LDPC encoder provided by the invention has a simple structure, and can reduce memories under the condition of obviously improving the encoding speed, thereby reducing the cost and improving the throughput.

The advantages and methods of the present invention will be further understood by reference to the following detailed description and drawings.

Drawings

FIG. 1 is a schematic diagram of an approximate lower triangular check matrix after row-column swapping;

FIG. 2 is a four-stage pipeline based QC-LDPC encoding process;

FIG. 3 is a functional block diagram of a loop left shift accumulator RLA circuit;

FIG. 4 is a high density matrix and vector multiplier consisting of u RLA circuits;

FIG. 5 is a sparse matrix and vector multiplier;

FIG. 6 is a type I backward iteration circuit;

FIG. 7 is a type II backward iteration circuit;

fig. 8 summarizes the hardware resources and processing time required for each encoding step of the encoder and the entire encoding process.

Detailed Description

The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.

The row weight and column weight of the circulant matrix are the same and denoted as w. If w is 0, then the circulant matrix is an all-zero matrix. If w is 1, the circulant matrix is replaceable, called the permutation matrix, which can be obtained by right-shifting the identity matrix I cyclically by a few bits. The check matrix H of the QC-LDPC code is a cyclic matrix H of order b x b formed by c x t_j,k(1. ltoreq. j. ltoreq. c, 1. ltoreq. k. ltoreq. t, t. e + c) in the following array:

in general, any cyclic matrix in the check matrix H is either an all-zero matrix (w ═ 0) or a permutation matrix (w ═ 1). Let the cyclic matrix H_j,kFirst line g of_j,k＝(g_j,k,1,g_j,k,2,…,g_j,k,b) Is its generator polynomial of which g_j,k,m0 or 1 (1. ltoreq. m. ltoreq. b). Since H is sparse, g_j,kThere are only 1 ' and even no ' 1 '.

The first e block column of H corresponds to the information vector a, and the last c block column corresponds to the check vector p. With b bits as one segment, the information vector a is equally divided into e segments, i.e. a ═ a₁,a₂,…,a_e) (ii) a The check vector p is equally divided into c segments, i.e. p ═ p (p)₁,p₂,…,p_c)。

Performing row exchange and column exchange operation on the check matrix H, and converting the check matrix H into an approximate lower triangular shape H_ALTAs shown in fig. 1. In fig. 1, the unit of all matrices is b bits instead of 1 bit. A is composed of (C-u). times.e circulant matrices of B × B order, B is composed of (C-u). times.0 u circulant matrices of B × 1B order, T is composed of (C-u). times.c-u circulant matrices of B × B order, C is composed of uxe.times.b order circulant matrices of B × B order, D is composed of uXu.times.b order circulant matrices of B × B order, E is composed of uX (C-u) circulant matrices of B × B orderAnd forming a cyclic matrix. T is a lower triangular matrix, u reflects a check matrix H_ALTProximity to the lower triangular matrix. In fig. 1, the matrices a and C correspond to the information vector a, and the matrices B and D correspond to a portion of the check vector p_x＝(p₁,p₂,…,p_u) The matrices T and E correspond to the remaining check vectors p_y＝(p_u+1,p_u+2,…,p_c)。p＝(p_x,p_y). The matrix and the vector satisfy the following relations:

p_x ^Τ＝Φ(ET^-1Aa^Τ+Ca^Τ) (3)

p_y ^Τ＝T^-1(Aa^Τ+Bp_x ^Τ) (4)

wherein Φ is (ET)^-1B+D)^-1Upper label of^ΤAnd^-1respectively representing transpose and inverse. As is well known, the inverse, product, and sum of the circulant matrix remains a circulant matrix. Thus, Φ is also an array consisting of a circulant matrix. Although both matrices E, T, B and D are sparse matrices, typically Φ is no longer sparse but rather high density.

Let f^T＝Aa^T，q^T＝T^–1f^T，w^T＝Ca^T，x^T＝Eq^T+w^T，p_x ^T＝Φx^T，y^T＝T^–1Bp_x ^TAnd p_y ^T＝q^T+y^T. Vectors f and w can be calculated by:

${\left[\begin{array}{cc}f& w\end{array}\right]}^T=\left[\begin{array}{c}A\\ C\end{array}\right]a^T={\mathrm{Fa}}^T---\left(5\right)$

wherein,

$F=\left[\begin{array}{c}A\\ C\end{array}\right]---\left(6\right)$

q^T＝T^–1f^Tand x^T＝Eq^T+w^TThe following matrix equation can be constructed:

$\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]{\left[\begin{array}{cc}q& x\end{array}\right]}^T=Q{\left[\begin{array}{cc}q& x\end{array}\right]}^T={\left[\begin{array}{cc}f& w\end{array}\right]}^T---\left(7\right)$

wherein,

$Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]---\left(8\right)$

once p is calculated_x，y^T＝T^–1Bp_x ^TRewritable as follows:

[B T][p_xy]^Τ＝Y[p_xy]^Τ＝0 (9)

wherein,

Y＝[B T](10)

since Q and Y are lower triangular matrices as well as T, both [ Q x ] in equation (7) and Y in equation (9) can be calculated in backward iteration.

Φ relates to the multiplication of the high density matrix with the vector, F relates to the multiplication of the sparse matrix with the vector, and Q and Y relate to backward iterative computations. From the above discussion, a four-stage pipeline based QC-LDPC encoding process can be presented, as shown in FIG. 2.

p_x ^T＝Φx^TIs equivalent to p_x＝xΦ^T. Let x be (x)₁,x₂,…,x_u×b). Defining a u-bit vector s_n＝(x_n,x_n+b,…,x_n+(u-1)×b) Wherein n is more than or equal to 1 and less than or equal to b. Let phi_j(1. ltoreq. j. ltoreq. u) is represented by^TAll circulant matrix generator polynomials in block j of (1) to form a u x b order matrix. Then there is

p_j＝(…((0+s₁Φ_j)^ls(1)+s₂Φ_j)^ls(1)+…+s_bΦ_j)^ls(1)(11)

Wherein, the upper label^ls(1)Indicating a cycle left shift by 1 bit.

From equation (11), a round-shift-Left-Accumulator (RLA) circuit can be obtained, as shown in fig. 3. The index of the lookup table is a u-bit vector s_nLook-up table L_jStoring variable u-bit vectors and fixed phi in advance_jAll possible products of, therefore, 2^ub-bit Read-Only Memory (ROM). b bit register R₁,R₂,…,R_uVector segments x for buffer vectors x, respectively₁,x₂,…,x_uB bit register R_u+jFor storing p_xIs verified by the verification segment p_j. 1 RLA circuit calculates the vector p_jB clock cycles are required.

Since u is very small, p is calculated simultaneously using u RLA circuits_x＝(p₁,p₂,…,p_u) Is a reasonable scheme, such as the high-density matrix and vector multiplier shown in fig. 4. The high-density matrix and vector multiplier consists of u lookup tables L₁,L₂,…,L_u2u b-bit registers R_3,1,R_3,2,…,R_3,2uAnd u b-bit two-input XOR gates X_3,1,X_3,2,…,X_3,uAnd (4) forming. Look-up table L₁,L₂,…,L_uStoring variable u-bit vectors and fixed matrices phi, respectively₁,Φ₂,…,Φ_uAll possible products of, register R_3,1,R_3,2,…,R_3,uVector segments x for buffer vectors x, respectively₁,x₂,…,x_uRegister R_3,u+1,R_3,u+2,…,R_3,2uRespectively for storing p_xIs verified by the verification segment p₁,p₂,…,p_u. u RLA circuits require the use of ub two-input XOR gates, 2^uub bits of ROM and 2ub registers. u RLA circuits calculate the vector p_xB clock cycles are required. Vector p is calculated using a high density matrix and vector multiplier_xThe steps are as follows:

step 1, zero clearing register R_3,u+1,R_3,u+2,…,R_3,2uInput vector segment x₁,x₂,…,x_uStore them in the register R respectively_3,1,R_3,2,…,R_3,uPerforming the following steps;

step 2, register R_3,1,R_3,2,…,R_3,uSimultaneously circulating left for 1 time, XOR gate X_3,1,X_3,2,…,X_3,uRespectively to the lookup table L₁,L₂,…,L_uOutput of and register R_3,u+1,R_3,u+2,…,R_3,2uThe contents of (A) are XOR-ed, and the XOR results are circularly left-shifted 1 time and then stored back to the register R respectively_3,u+1,R_3,u+2,…,R_3,2u；

Step 3, repeating step 2 for b times, and after the step is completed, using a register R_3,u+1,R_3,u+2,…,R_3,2uThe contents of the storage are respectively the check segment p₁,p₂,…,p_uWhich form part of a check vector p_x。

Let f be (f)₁,f₂,…,f_c–u) And w ═ f_c–u+1,f_c–u+2,…,f_c) Then [ f w ]]＝(f₁,f₂,…,f_c). According to formula (5), f_jIs the jth block row of the matrix F and a^TProduct of, i.e.

$f_j=H_{j,1}{a}_1^T+H_{j,2}{a}_2^T+...+H_{j,i}{a}_i^T+...+H_{j,e}{a}_e^T---\left(12\right)$

Wherein i is more than or equal to 1 and less than or equal to e, and j is more than or equal to 1 and less than or equal to c. f. of_jN bit f of_j,n(1. ltoreq. n. ltoreq. b) is

$\begin{array}{c}{f}_{j,n}=g_{j,1}^{\mathrm{rs}(n-1)}{a}_1+g_{j,2}^{\mathrm{rs}(n-1)}{a}_2+...+g_{j,i}^{\mathrm{rs}(n-1)}{a}_i+...+g_{j,e}^{\mathrm{rs}(n-1)}{a}_e\\ =g_{j,1}{a}_1^{\mathrm{ls}(n-1)}+g_{j,2}{a}_2^{\mathrm{ls}(n-1)}+...+g_{j,i}{a}_i^{\mathrm{ls}(n-1)}+...+g_{j,e}{a}_e^{\mathrm{ls}(n-1)}\end{array}---\left(13\right)$

Wherein, the upper label^rs(n–1)And^ls(n–1)respectively representing a cyclic right shift by n-1 bits and a cyclic left shift by n-1 bits. Since any circulant matrix generates a polynomial g_j,iWith only a small number of '1's, or even all zeros, the inner product in equation (13) can be achieved by summing the taps of the circular left shift register, as shown in the sparse matrix and vector multiplier of fig. 5. The sparse matrix and vector multiplier is composed of t b-bit registers R_1,1,R_1,2,…,R_1,tAnd c a plurality of multiple-input XOR gates X_1,1,X_1,2,…,X_1,cAnd (4) forming. Register R_1,1,R_1,2,…,R_1,eFor loading and looping left-shifting information segments a₁,a₂,…,a_eRegister R_1,e+1,R_1,e+2,…,R_1,tFor storing [ f w]Vector segment f of₁,f₂,…,f_c. The sparse connection in fig. 5 depends on all circulant matrix generator polynomials in matrix F. If g is_j,i,m1 (1. ltoreq. m. ltoreq. b), then the information section a_iIs connected to the exclusive or gate X_1,j. Thus, register R_1,iDepends on the position of the non-zero elements of all circulant matrix generator polynomials in the ith block column of the matrix F, and a multi-input xor gate X_1,jDepends on the position of the non-zero elements of all circulant matrix generator polynomials in the jth block row of the matrix F. If all circulant matrix generator polynomials in F have a total of α '1', then the sparse matrix and vector multiplier requires the simultaneous computation of F using (α -c) two-input XOR gates_1,n,f_2,n,…,f_c,n. f and w may be counted over b clock cycles. The steps of calculating vectors f and w using a sparse matrix and vector multiplier are as follows:

step 1, input information segment a₁,a₂,…,a_eStore them in the register R respectively_1,1,R_1,2,…,R_1,ePerforming the following steps;

step 2, register R_1,1,R_1,2,…,R_1,eSimultaneously circulating left for 1 time, XOR gate X_1,1,X_1,2,…,X_1,cShift the XOR result to the left into register R, respectively_1,e+1,R_1,e+2,…,R_1,tPerforming the following steps;

step 3, repeating step 2 for b times, and after the step is completed, using a register R_1,e+1,R_1,e+2,…,R_1,tThe contents of the memory are respectively vector segments f₁,f₂,…,f_cThey constitute vectors f and w.

Equation (7) implies a backward iterative operation, and the vectors q and x must be solved segment by segment. Definition [ q x]＝(q₁,q₂,…,q_c) And initialized to all zeros. First, q is₁Exactly equal to f₁. Secondly, q is₂Is the 2 nd block row and vector [ Q x ] of the matrix Q]^TProduct of f₂And (2) of (1). Then, q₃Is block 3 row and vector [ Q x ] of matrix Q]^TProduct of f₃And (2) of (1). Repeating the above process until q is calculated_cA type I backward iterative circuit as shown in fig. 6. The I-type backward iterative circuit is composed of c b-bit registers R_2,1,R_2,2,…,R_2,cAnd c-1 multiple input modulo-2 adder A_2,2,A_2,3,…,A_2,cAnd (4) forming.

To calculate q_j(j is not less than 1 and not more than c) as an example. The non-zero circulant matrix in the check matrix H is typically a circularly right shifted version of the identity matrix. Suppose there are N non-zero circulants in the jth block row of the matrix Q, and their cyclic right shift numbers are s respectively_j,k1,s_j,k2,…,s_j,kN(1≤k1,k2,…,kN<j) In that respect Then the process of the first step is carried out,

$\begin{array}{c}{q}_j=f_j+I^{\mathrm{rs}\left(s_{j,k+1}\right)}{q}_{k1}+I^{\mathrm{rs}\left(s_{j,k2}\right)}{q}_{k2}+...+I^{\mathrm{rs}\left(s_{j,\mathrm{kN}}\right)}{q}_{\mathrm{kN}}\\ =f_j+q_{k1}^{\mathrm{ls}\left(s_{j,k1}\right)}+q_{k2}^{\mathrm{ls}\left(s_{j,k2}\right)}+...+q_{\mathrm{kN}}^{\mathrm{ls}\left(s_{j,\mathrm{kN}}\right)}\end{array}---\left(14\right)$

since N is small, equation (14) can be computed by a multiple input modulo-2 adder that shifts the input cycle to the left in 1 clock cycle. Therefore, c clock cycles are required to compute vector [ q x ]. Assuming that the matrix Q has β non-zero circulant matrices in common, then the type I backward iterative circuit needs to use (β -c) b two-input xor gates.

The matrix Q is a circulant matrix Q of order c × c b × c_j,k(j is more than or equal to 1 and less than or equal to c, and k is more than or equal to 1 and less than or equal to c). Non-zero circulant matrix Q_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,k，0≤s_j,k<b. For ease of description, an all-zero circulant matrix is relative to a b × b order circulant matrixThe cyclic right shift number of is denoted as s_j,k'-'. In FIG. 6, a non-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jPerforming XOR operation, wherein the vector segment corresponding to the all-zero cyclic matrix does not participate in the XOR operation, A_2,jIs calculated as q_jIs stored in a register R_2,jIn (1). The steps for computing the vectors q and x using a type I backward iterative circuit are as follows:

step 1, inputting vector segment f₁Dividing the vector segment q₁＝f₁Into a register R_2,1Performing the following steps;

step 2, inputting vector segment f_jNon-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jPerforming XOR operation to obtain result q_jIs stored in a register R_2,jWherein j is more than or equal to 2 and less than or equal to c, and k is more than or equal to 1<j，0≤s_j,k<b；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 c-1 times, and finally, obtaining a register R_2,1,R_2,2,…,R_2,cStored are respectively vector segments q₁,q₂,…,q_cThey constitute vectors q and x.

Equation (9) also implies a backward iterative operation, and the vector y must be solved segment by segment. Definition y ═ (y)₁,y₂,…,y_c–u) And initialized to all zeros. First, y₁Is the 1 st block row of matrix Y and vector p_xy]^TThe product of the two. Second, y₂Is the 2 nd block row of matrix Y and vector p_xy]^TThe product of the two. Repeating the above process until y is calculated_c–uUp to the type II backward iteration circuit as shown in fig. 7. The type II backward iterative circuit is composed of c b-bit registers R_4,1,R_4,2,…,R_4,cAnd c-u multiple-input modulo-2 adder A_4,1,A_4,2,…,A_4,c-uAnd (4) forming. Direction of calculationThe quantity y takes (c-u) clock cycles in total. Assuming that there are xi non-zero circulant matrices in the matrix Y, then the backward iterative circuit of type II needs to use (xi-2 c +2u) b two-input xor gates. The matrix Y is a cyclic matrix Y of order b × b consisting of (c-u) × c_j,k(j is more than or equal to 1 and less than or equal to c-u, and k is more than or equal to 1 and less than or equal to c). Non-zero circulant matrix Y_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,k，0≤s_j,k<b. The steps for computing the vector y using a type II backward iterative circuit are as follows:

step 1, inputting a check segment p₁,p₂,…,p_uStore them in the register R respectively_4,c-u+1,R_4,c-u+2,…,R_4,cPerforming the following steps;

step 2, non-zero circulant matrix Y_j,kCorresponding vector segment p_kOr y_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_4,jIn the process, an XOR operation is performed, and the result y of the XOR operation_jIs stored in a register R_4,jWherein j is more than or equal to 1 and less than or equal to c-u, and k is more than or equal to 1<u+j，0≤s_j,k<b；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for c-u times, and finally, obtaining a register R_4,1,R_4,2,…,R_4,c-uStored are respectively vector segments y₁,y₂,…,y_c-uThey constitute a vector y.

The invention provides a high-speed QC-LDPC coding method based on a four-level pipeline, which is suitable for QC-LDPC codes in a communication system, and the coding steps are described as follows:

step 1, calculating vectors f and w by using a sparse matrix and a vector multiplier;

step 2, calculating vectors q and x by using an I-type backward iteration circuit;

step 3, calculating partial check vector p by using multiplier of high density matrix and vector_x；

Step 4, calculating vectors by using a II type backward iteration circuitAnd xoring y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

Fig. 8 summarizes the hardware resource consumption and processing time required by each encoding step of the encoder and the entire encoding process.

As can be seen from FIG. 8, when the pipeline is full, the whole encoding process requires max (t-c + b, c, u + b) clock cycles, which is much smaller than e × b clock cycles required by the serial encoding method based on c SRAA-I circuits.

Existing solutions for QC-LDPC encoders in communication systems require e x c x b bit ROM, whereas the present invention requires 2^uub bit ROM. Since u is usually small, so 2^uub is much smaller than e × c × b.

In conclusion, compared with the conventional serial SRAA method, the method has the advantages of high coding speed, low memory consumption and the like.

The above description is only one embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can change or replace the present invention within the technical scope of the present invention without creative efforts, and the present invention shall be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope defined by the claims.

Claims (6)

1. A high-speed QC-LDPC encoder based on four-stage pipeline, the check matrix H of QC-LDPC code is an array formed by c x t b order cyclic matrixes, wherein c, t and b are positive integers, t is e + c, the check matrix H is transformed into an approximate lower triangular shape by row-column exchange and can be divided into 6 sub-matrixes, $H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right],$ a is composed of (C-u) x E B × B cyclic matrices, B is composed of (C-u) x 0u B × 1B cyclic matrices, lower triangular matrix T is composed of (C-u) x (C-u) B × B cyclic matrices, C is composed of u × E B × B cyclic matrices, D is composed of u × u B cyclic matrices, E is composed of u × u (C-u) B × B cyclic matrices, where u is a positive integer, and Φ ═ ET^-1B+D)^-1Is composed of uXu b-order cyclic matrices, phi_jIs formed by phi^TAll circulant matrix generator polynomials in the jth block column of (1), wherein superscript^ΤAnd^-1respectively representing transposition and inversion, j is more than or equal to 1 and less than or equal to u, $Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]$ is formed by c × c b-order cyclic matrixes Q_j,kWherein I is an identity matrix, 0 is an all-zero matrix, 1 is more than or equal to j and less than or equal to c,1 is more than or equal to k and less than or equal to c, and a non-zero cyclic matrix Q_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<b，Y＝[B T]Is composed of (c-u) x c cyclic matrices of b x b order_j,kWherein j is more than or equal to 1 and less than or equal to c-u, k is more than or equal to 1 and less than or equal to c, and a non-zero cyclic matrix Y_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<B, A and C correspond to the information vector a, and the matrixes B and D correspond to a part of the check vector p_xThe matrices T and E correspond to the remaining correctionsVector of experiment p_yCheck vector p ═ p (p)_x,p_y) The information vector a is equally divided into e segments by b bits, i.e. a ═ a₁,a₂,…,a_e) The check vector p is equally divided into c segments, i.e. p ═ p (p)₁,p₂,…,p_c)，p_x＝(p₁,p₂,…,p_u)，p_y＝(p_u+1,p_u+2,…,p_c) The vector f is equally divided into segments c-u, i.e. f ═ f₁,f₂,…,f_c–u) The vector w is divided equally into u segments, i.e. w ═ f_c–u+1,f_c–u+2,…,f_c)，[f w]＝(f₁,f₂,…,f_c) The vector q is equally divided into segments c-u, i.e. q ═ q (q)₁,q₂,…,q_c–u) The vector x is equally divided into u segments, i.e. x ═ q_c–u+1,q_c–u+2,…,q_c)，[q x]＝(q₁,q₂,…,q_c) The vector y is equally divided into segments c-u, i.e. y ═ y₁,y₂,…,y_c–u) Characterised in that the encoder comprises the following components:

a sparse matrix and vector multiplier consisting of t b-bit registers R_1,1,R_1,2,…,R_1,tAnd c a plurality of multiple-input XOR gates X_1,1,X_1,2,…,X_1,cA component for calculating vectors f and w;

the I-type backward iterative circuit consists of c b-bit registers R_2,1,R_2,2,…,R_2,cAnd c-1 multiple input modulo-2 adder A_2,2,A_2,3,…,A_2,cA component for computing vectors q and x;

the multiplier for high-density matrix and vector is composed of u lookup tables L₁,L₂,…,L_u2u b-bit registers R_3,1,R_3,2,…,R_3,2uAnd u b-bit two-input XOR gates X_3,1,X_3,2,…,X_3,uComposition for calculating partial check vector p_xLook-up table L₁,L₂,…,L_uStoring variable u-bit vectors and fixed matrices phi, respectively₁,Φ₂,…,Φ_uAll possibilities ofMultiplying;

a type II backward iterative circuit consisting of c b-bit registers R_4,1,R_4,2,…,R_4,cAnd c-u multiple-input modulo-2 adder A_4,1,A_4,2,…,A_4,c-uComposition for calculating the XOR of the vector y, y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

2. The four-stage pipeline-based high-speed QC-LDPC encoder according to claim 1, wherein said sparse matrix and vector multiplier calculates vectors f and w as follows:

step 1, input information segment a₁,a₂,…,a_eStore them in the register R respectively_1,1,R_1,2,…,R_1,ePerforming the following steps;

step 2, register R_1,1,R_1,2,…,R_1,eSimultaneously circulating left for 1 time, XOR gate X_1,1,X_1,2,…,X_1,cShift the XOR result to the left into register R, respectively_1,e+1,R_1,e+2,…,R_1,tPerforming the following steps;

step 3, repeating step 2 for b times, and after the step is completed, using a register R_1,e+1,R_1,e+2,…,R_1,tThe contents of the memory are respectively vector segments f₁,f₂,…,f_cThey constitute vectors f and w.

3. A four-stage pipeline-based high-speed QC-LDPC encoder according to claim 1, wherein the type I backward iterative circuit calculates the vectors q and x as follows:

step 1, inputting vector segment f₁Dividing the vector segment q₁＝f₁Into a register R_2,1Performing the following steps;

step 2, inputting vector segment f_jNon-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jTo carry out the differenceOR operation, XOR result q_jIs stored in a register R_2,jWherein j is more than or equal to 2 and less than or equal to c, and k is more than or equal to 1<j，0≤s_j,k<b；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 c-1 times, and finally, obtaining a register R_2,1,R_2,2,…,R_2,cStored are respectively vector segments q₁,q₂,…,q_cThey constitute vectors q and x.

4. The four-stage pipeline-based high-speed QC-LDPC encoder according to claim 1, wherein the high density matrix and vector multiplier calculates vector p_xThe steps are as follows:

step 1, zero clearing register R_3,u+1,R_3,u+2,…,R_3,2uInput vector segment x₁,x₂,…,x_uStore them in the register R respectively_3,1,R_3,2,…,R_3,uPerforming the following steps;

step 2, register R_3,1,R_3,2,…,R_3,uSimultaneously circulating left for 1 time, XOR gate X_3,1,X_3,2,…,X_3,uRespectively to the lookup table L₁,L₂,…,L_uOutput of and register R_3,u+1,R_3,u+2,…,R_3,2uThe contents of (A) are XOR-ed, and the XOR results are circularly left-shifted 1 time and then stored back to the register R respectively_3,u+1,R_3,u+2,…,R_3,2u；

Step 3, repeating step 2 for b times, and after the step is completed, using a register R_3,u+1,R_3,u+2,…,R_3,2uThe contents of the storage are respectively the check segment p₁,p₂,…,p_uWhich form part of a check vector p_x。

5. The high-speed QC-LDPC encoder based on four-stage pipeline according to claim 1, wherein said type II backward iterative circuit calculates vector y as follows:

step 1, inputting a check segment p₁,p₂,…,p_uStore them in the register R respectively_4,c-u+1,R_4,c-u+2,…,R_4,cPerforming the following steps;

step 2, non-zero circulant matrix Y_j,kCorresponding vector segment p_kOr y_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_4,jIn the process, an XOR operation is performed, and the result y of the XOR operation_jIs stored in a register R_4,jWherein j is more than or equal to 1 and less than or equal to c-u, and k is more than or equal to 1<u+j，0≤s_j,k<b；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for c-u times, and finally, obtaining a register R_4,1,R_4,2,…,R_4,c-uStored are respectively vector segments y₁,y₂,…,y_c-uThey constitute a vector y.

6. A high-speed QC-LDPC coding method based on four-stage production line, the check matrix H of QC-LDPC code is an array formed by c x t b order cyclic matrixes, wherein c, t and b are positive integers, t is e + c, the check matrix H is transformed into an approximate lower triangular shape by row-column exchange and can be divided into 6 sub-matrixes, $H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right],$ a is composed of (C-u) x E B × B cyclic matrices, B is composed of (C-u) x 0u B × 1B cyclic matrices, lower triangular matrix T is composed of (C-u) x (C-u) B × B cyclic matrices, C is composed of u × E B × B cyclic matrices, D is composed of u × u B cyclic matrices, E is composed of u × u (C-u) B × B cyclic matrices, where u is a positive integer, and Φ ═ ET^-1B+D)^-1Is composed of uXu b-order cyclic matrices, phi_jIs formed by phi^TAll circulant matrix generator polynomials in the jth block column of (1), wherein superscript^ΤAnd^-1respectively representing transposition and inversion, j is more than or equal to 1 and less than or equal to u, $Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]$ is formed by c × c b-order cyclic matrixes Q_j,kWherein I is an identity matrix, 0 is an all-zero matrix, 1 is more than or equal to j and less than or equal to c,1 is more than or equal to k and less than or equal to c, and a non-zero cyclic matrix Q_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<b，Y＝[B T]Is composed of (c-u) x c cyclic matrices of b x b order_j,kWherein j is more than or equal to 1 and less than or equal to c-u, k is more than or equal to 1 and less than or equal to c, and a non-zero cyclic matrix Y_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<B, A and C correspond to the information vector a, and the matrixes B and D correspond to a part of the check vector p_xThe matrices T and E correspond to the remaining check vectors p_yCheck vector p ═ p (p)_x,p_y) The information vector a is equally divided into e segments by b bits, i.e. a ═ a₁,a₂,…,a_e) The check vector p is equally divided into c segments, i.e. p ═ p (p)₁,p₂,…,p_c)，p_x＝(p₁,p₂,…,p_u)，p_y＝(p_u+1,p_u+2,…,p_c) The vector f is equally divided into segments c-u, i.e. f ═ f₁,f₂,…,f_{c– u}) The vector w is divided equally into u segments, i.e. w ═ f_c–u+1,f_c–u+2,…,f_c)，[f w]＝(f₁,f₂,…,f_c) The vector q is equally divided into cSegment-u, i.e. q ═ q (q)₁,q₂,…,q_c–u) The vector x is equally divided into u segments, i.e. x ═ q_c–u+1,q_c–u+2,…,q_c)，[q x]＝(q₁,q₂,…,q_c) The vector y is equally divided into segments c-u, i.e. y ═ y₁,y₂,…,y_c–u) Characterized in that said coding method comprises the following steps:

step 1, calculating vectors f and w by using a sparse matrix and a vector multiplier;

step 2, calculating vectors q and x by using an I-type backward iteration circuit;

step 3, calculating partial check vector p by using multiplier of high density matrix and vector_x；

And 4, calculating the vector y by using a II type backward iterative circuit, and performing exclusive OR on the vector y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。