CN101192833B - A device and method for low-density checksum LDPC parallel coding - Google Patents

Abstract

The invention relates to the communications field and provides parallel encoding device and a method for a low density parity-check code (LDPC). By adopting the practice of step-by-step encoding combined with the serial-parallel approach, a concatenated encoding scheme with linear complexity combining with pre-encoding and parallel convolution coding structures is provided thereby. The encoding device for realizing the encoding scheme mainly comprises an information storage unit, a pre-encoding unit and an encoding unit (comprising a data distribution unit and a convolution coding unit) as well as a v (0) verification bit generating unit. The encoding device of the invention adopts a circular shift register and a model 2 adder, which is easy to realize and avoid multiplication operation of vector and matrix. Complexity of the encoding device is reduced. The encoding device provided by the invention features good expansibility. A plurality of basic encoders are used for parallel encoding so that encoding efficiency can be improved by many times compared with the single basic encoding device. Therefore, when hardware complexity permits, parallel structures can be applied as much as possible, which greatly improves encoding efficiency.

Description

A kind of device and method of low-density checksum LDPC parallel coding

Technical field

The present invention relates to the communications field, relate in particular to a kind of device and method of low-density checksum LDPC parallel coding.

Background technology

Low-density checksum LDPC is the coded system of being limit near Shannon (Shannon) in a kind of performance of proposition in 1964 by Gal lager at first, in a very long time, owing to be subjected to the restriction of scientific and technological level, LDPC does not obtain paying attention to and promoting, proved that up to D.Mac Kay in 1996 and R.Neal LDPC code performance and cost all are better than Turbo code (the serial lingware of BROLAND company exploitation), the LDPC sign indicating number just enters people's the visual field once more, has started one research boom.

Enter from theoretical research the process of practical development at low-density checksum LDPC, encoder complexity and the coding time delay that causes thereof become the key factor that restriction LDPC sign indicating number is used in high-speed data service.

The LDPC sign indicating number adopts cyclic shift and partitioning of matrix technology from simplifying the angle of encoder complexity among the IEEE 802.16e, big check matrix is decomposed into the parallel organization of a plurality of minor matrixs.Wherein, the LDPC sign indicating number serves as that female sign indicating number expansion produces with the LDPC sign indicating number of a group or several group systems, and check matrix H is defined as

$H=\left[\begin{array}{cccccc}{P}_{\mathrm{0,0}}& P_{\mathrm{0,1}}& {\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{\mathrm{0,2}}& \&CenterDot;\&CenterDot;\&CenterDot;& P_{0,n_b-2}& P_{0,n_b-1}\\ {\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{\mathrm{1,0}}& {\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{\mathrm{1,1}}& {\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">\; <figure-callout\; id="2"\; label="P"\; filenames="H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>\; </figure-callout>}}_{\mathrm{1,2}}& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{1,n_b-2}& {\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{1,n_b-1}\\ {\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{\mathrm{2,0}}& {\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{\mathrm{2,1}}& {\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="H061E4891320061205E000033.png"\; state="\{\{state\}\}">\; <figure-callout\; id="2"\; label="P"\; filenames="H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>\; </figure-callout>}}_{\mathrm{2,2}}& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{2,n_b-2}& {\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="H061E4891320061205E000033.png"\; state="\{\{state\}\}">P</figure-callout>}}_{2,n_b-1}\\ \&CenterDot;\&CenterDot;\&CenterDot;& \&CenterDot;\&CenterDot;\&CenterDot;& \&CenterDot;\&CenterDot;\&CenterDot;& \&CenterDot;\&CenterDot;\&CenterDot;& \&CenterDot;\&CenterDot;\&CenterDot;& \&CenterDot;\&CenterDot;\&CenterDot;\\ P_{m_b-\mathrm{1,0}}& P_{m_b-\mathrm{1,1}}& P_{m_b-\mathrm{1,2}}& \&CenterDot;\&CenterDot;\&CenterDot;& P_{m_b-1,n_b-2}& P_{m_b-1,n_b-1}\end{array}\right]$

P in the formula _{I, j}Be z * z null matrix or permutation matrix, wherein the span of i is 0,1,2 ..., (m _b-1), the span of j is 0,1,2 ... (n _b-1), check matrix H is by m _b* n _bDimension basic matrix H _bExpansion forms, then code length n=z * n _b, check bit m=z * m _b,

The information bit number is k=n-m.Permutation matrix adopts the right cyclic shift of z * z unit matrix to generate, and can be determined by its figure place that circulates to the right.

The design process of check matrix H is: at first with the generator matrix H of check matrix _bIn 0 element change-1,1 number of times that is changed to the cyclic shift of permutation matrix into, generate the basic matrix H of check matrix thus _Bm, again with H _BmExpand to check matrix H.H _bSeparated into two parts,

H _B1Corresponding to information bit, H _B2Corresponding to check bit.H _B2Further resolve into two parts, H _B2=[h _b| H ' _B2], h _bBe m _bDimensional vector wherein has the odd number nonzero element, H ' _B2Be biconjugate angular moment battle array, the element of correspondence position is 1 when i=j and i=j+1, and other positions are 0.

h _bMiddle h _b(0)=and l, h _b(m _b-1)=and l, h _b(x)=and l ', 0≤l＜z, 0≤l '＜z, 1≤x≤m _b-2, h _b(i)=0,0＜i＜m _b-1, i ≠ x, h _b(0) and h _b(m _b-1) number of times of cyclic shift must be identical.X is H _BmIn non-index negative, that undetermined element is capable.H ' _B2In element during H, all be extended to unit matrix at structure.

At above-mentioned check matrix, provided the basic principle of three kinds of encoding schemes among the IEEE 802.16e, comprise the parallel encoding scheme that serial code, parallel encoding and a plurality of minor matrix multiply each other:

Method 1---serial code

Information sequence s is divided into k _bGroup, k _b=n _b-m _b, every group of z bit.S after the grouping is designated as u:u=[u (0) ^T, u (1) ^T..., u (k _b-1) ^T] ^T, each element among the u is the z dimensional vector, i.e. u (i)=[s _Izs _Iz+1S _{(i+1) z-1}] ^T, use H _BmEncode, verification sequence can produce by z bit groupings.Verification sequence after the grouping is defined as v, v=[v (0) ^T, v (1) ^T..., v (m _b-1) ^T] ^T, each element among the v is the z dimensional vector, i.e. v (i)=[p _Izp _Iz+1P _{(i+1) z-1}] ^T, transmitting sequence c=[u, v], cataloged procedure be divided into two the step finish:

(1) v (0) is determined in initialization;

With H _BmC obtains by the row addition

$P_{p\left({x,k}_b\right)}v\left(0\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\&Sigma;}}}\underset{i=0}{\overset{m_b-1}{\mathrm{\&Sigma;}}}{P}_{p(i,j)}u\left(j\right)---\left(1\right)$

1≤x≤m wherein _b-2, be H _BmIn non-index negative, that undetermined element is capable.P _iMiddle i refers to p (x, the k in the formula (1) _b) or p (i, j), the number of times of the right cyclic shift of expression circulation z * z unit matrix.Can be when asking v (0) with (1) premultiplication Because p (x, k _b) represent right number of times, so

(2) utilize regressing calculation, ask v (i+1), suppose known v (i), wherein 0≤i≤m _b-2.

According to H ' _B2Structure, ask check bit to get regressing calculation and can be write as:

$v\left(1\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\&Sigma;}}}{P}_{p(i,j)}u\left(j\right)+P_{p(i,k_b)}v\left(0\right),$ i＝0 (2)

$v(i+1)=v\left(i\right)+\underset{j=0}{\overset{k_b-1}{\mathrm{\&Sigma;}}}{P}_{p(i,j)}u\left(j\right)+P_{p\left({i,k}_b\right)}v\left(0\right),$ i＝1，…，m _b-2 (3)

P in the formula _-1=0 _{Z * z}Can determine all check bits except that v (0) by formula (2) and (3).

Method 2---parallel encoding, this method and method 1 difference are:

(1) v (0) is determined in initialization;

$v\left(0\right)=P_{p\left({x,k}_b\right)}^{-1}\underset{j=0}{\overset{k_b-1}{\mathrm{\&Sigma;}}}\left(\underset{q=0}{\overset{m_b-1}{\mathrm{\&Sigma;}}}{P}_{p(q,j)}\right)u\left(j\right)---\left(4\right)$

(2) utilize formula (5) formula, but parallel computation v (1) is to v (m _b-1):

$v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\&Sigma;}}}\left(\underset{q=i}{\overset{m_b-1}{\mathrm{\&Sigma;}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=i}{\overset{m_b-1}{\mathrm{\&Sigma;}}}{P}_{p(q,k_b)}v\left(0\right),$ i＝1，…，m _b-1 (5)

The coding method that method 3---minor matrix multiplies each other

Adopt the fast coding scheme of LDPC, matrix H is changed into following form again

$H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right]---\left(6\right)$

Wherein the dimension of A is (m-z) * k, and the dimension of B is (m-z) * z, and the dimension of T is (m-z) * (m-z), and the dimension of C is z * k, and the dimension of D is z * z, and the dimension of E is z * (m-z)

$\left(\begin{array}{c}B\\ D\end{array}\right)$ Correspond respectively to h with D _bAnd h _b(m _b-1) expansion.

Therefore, code word is divided into three parts, c=(u p ₁p ₂), u is the systematic code information bit, p ₁And p ₂Be check digit, p ₁Length is z, p ₂Length is (m-z).According to Hc ^T=0 reaches (6) can get formula (7) and (8):

${\mathrm{Au}}^T+{\mathrm{Bp}}_1^T+{\mathrm{Tp}}_2^T=0---\left(7\right)$

$({\mathrm{ET}}^{-1}A+C)u^T+({\mathrm{ET}}^{-1}B+D)p_1^T=0---\left(8\right)$

By the character of check matrix H as can be known

(perhaps cyclic shift) then has:

$p_1^T=({\mathrm{ET}}^{-1}A+C)u^T$

$p_2^T=T^{-1}({\mathrm{Au}}^T+{\mathrm{Bp}}_1^T)$

Thereby cataloged procedure can be finished with operation shown in Figure 1, and operation shown in Figure 1 is finished by following FOUR EASY STEPS, that is:

(1) calculates Au ^TAnd Cu ^T

(2) calculate ET ^-1(Au ^T)

(3) calculate

$p_1^T={\mathrm{ET}}^{-1}\left({\mathrm{Au}}^T\right)+{\mathrm{Cu}}^T$

(4) calculate

$p_2^T=T^{-1}({\mathrm{Au}}^T+{\mathrm{Bp}}_1^T)$

Though provided the basic principle of three kinds of encoding schemes among the IEEE802.16e, do not provided the design principle and the method for physical circuit.Though the serial code scheme, promptly method 1, though relatively simple for structure, code efficiency is lower, is difficult to be applied in the high speed data transmission system; For full parallel encoding scheme, promptly method 2, although can effectively improve coding rate, and the hardware complexity height, it is big to take memory space, realizes relatively difficulty; The parallel encoding scheme that minor matrix multiplies each other, it is method 3, though can effectively improve coding rate, and when the matrix-block that decomposes is smaller, hard-wired complexity is lower, but its encoder complexity still is exponential increase with the increase of matrix exponent number, for minute block size and code length certain restriction is arranged all.

This shows, three kinds of schemes of this that provides in the prior art all have obvious defects, the coding that has restricted the LDPC sign indicating number is realized, limited the application of LDPC sign indicating number in high-speed data service, especially its involved hardware circuit aspect, do not have concrete implementation, IEEE802.16e has also only provided the basic coding principle of LDPC sign indicating number.

Summary of the invention

In view of above-mentioned existing in prior technology problem, embodiments of the invention provide a kind of device and method of low-density checksum LDPC parallel coding, solve existing LDPC coding and realize existing problem, thereby promoted theoretical foundation and the hard-wired basis that provides strong widely for the application of LDPC sign indicating number in high-speed data service.

Embodiments of the invention are achieved through the following technical solutions:

A kind of device of low-density checksum LDPC parallel coding comprises information memory cell, precoding unit and coding unit, and information memory cell links to each other with precoding unit, and precoding unit links to each other with coding unit,

Information memory cell comprises one or more circulating register, be used for information sequence is stored in corresponding circulating register according to every group of information bit that comprises some, determine the quantity and the position of described circulating register tap, be specially: when adopting a described device to encode, the quantity of the tap of described circulating register correspondence and position are determined according to the quantity and the numerical value of the non-negative element in the basic matrix respective column of LDPC code check matrix; When adopting more than one described device to carry out parallel encoding, the quantity of the tap of described circulating register correspondence determines that according to the quantity of the non-negative element in the basic matrix respective column of LDPC code check matrix the position of the tap of described circulating register correspondence is determined according to the numerical value of the non-negative element in the basic matrix respective column of LDPC code check matrix and the sequence number of described device;

Precoding unit comprises one or more modulo 2 adder, described precoding unit is used for determining corresponding relation between described circulating register tap output and the modulo 2 adder according to the quantity of information memory cell circulating register tap and position, and the nodulo-2 addition computing is carried out to finish the precoding of verification sequence in the information bit and the particular verified position that will participate in check equations, the quantity of described modulo 2 adder is determined by the line number of the basic matrix of LDPC code check matrix, imports the quantity of the bit of corresponding modulo 2 adder and is determined by the quantity of non-negative element in the first submatrix corresponding row of the basic matrix of LDPC check matrix;

Coding unit, be used for the precoding finished according to described precoding unit, further finish the LDPC parallel encoding, coding unit comprises data allocations unit and convolutional encoding unit, wherein the data allocations unit links to each other with described precoding unit, the data allocations unit links to each other with the convolutional encoding unit, and described data allocations unit is used for the modulo 2 adder of described precoding unit is sent into corresponding convolution coder in the convolutional encoding unit respectively in the data that difference obtains constantly; Described convolutional encoding unit comprises one or more convolution coder, described convolution coder is used for the described data of its reception are encoded, generate and the described information sequence corresponding check of LDPC sign indicating number sequence, wherein the quantity of convolution coder is determined according to the quantity of modulo 2 adder in the precoding unit.

A kind of method of low-density checksum LDPC parallel coding, the step that the device of employing LDPC parallel encoding is encoded comprises:

Information sequence is stored in the corresponding circulating register according to every group of information bit that comprises some, determines the quantity and the position of described circulating register tap, be specially:

When adopting a described device to encode, the quantity of the tap of described circulating register correspondence and position are determined according to the quantity and the numerical value of the non-negative element in the basic matrix respective column of LDPC code check matrix; When adopting more than one described device to carry out parallel encoding, the quantity of the tap of described circulating register correspondence determines that according to the quantity of the non-negative element in the basic matrix respective column of LDPC code check matrix the position of the tap of described circulating register correspondence is determined according to the numerical value of the non-negative element in the basic matrix respective column of LDPC code check matrix and the sequence number of described device;

Corresponding relation between the modulo 2 adder of using in the tap output of determining described circulating register according to the quantity and the position of described circulating register tap and the precoding process, and the nodulo-2 addition computing is carried out to finish the precoding of verification sequence in the information bit and the particular verified position that will participate in check equations, further finish the LDPC parallel encoding, the described step of further finishing the LDPC parallel encoding comprises: described modulo 2 adder is sent into respectively in the corresponding convolution coder in the data that difference obtains constantly encoded, described convolution coder is used for the described data of sending into are encoded, generate and the described information sequence corresponding check of LDPC sign indicating number sequence, wherein the quantity of convolution coder is determined according to the quantity of modulo 2 adder in the precoding unit, the quantity of described modulo 2 adder is determined by the line number of the basic matrix of LDPC code check matrix, imports the quantity of the bit of corresponding modulo 2 adder and is determined by the quantity of non-negative element in the first submatrix corresponding row of the basic matrix of LDPC check matrix.

As seen from the above technical solution provided by the invention, the invention provides a kind of device and method of low-density checksum LDPC parallel coding, code device of the present invention has adopted circulating register and modulo 2 adder, realize simple, avoid vector and multiplication of matrices computing, reduced the complexity of code device; Code device provided by the invention has very strong extensibility, adopt N basic encoding unit to carry out parallel encoding, make code efficiency bring up to N times of the single basic coding device of employing, thereby in the hardware complexity allowed band, can adopt parallel organization as much as possible, improve code efficiency greatly.

Description of drawings

Fig. 1 is the multiply each other basic principle of coding method of the minor matrix of prior art;

The basic coding apparatus structure schematic diagram of the LDPC that Fig. 2 provides for embodiments of the invention;

The basic encoding unit theory structure schematic diagram of LDPC among the IEEE802.16e that Fig. 3 provides for embodiments of the invention;

A kind of recursive convolutional encoder device theory structure schematic diagram that Fig. 4 adopts for embodiments of the invention;

Fig. 5 is the theory structure schematic diagram of the recursive convolutional encoder device of employing in the LDPC code coder (1/2 code check, code length are 2304) of embodiments of the invention;

Another recursive convolutional encoder device theory structure schematic diagram that Fig. 6 adopts for embodiments of the invention;

Fig. 7 adopts the LDPC parallel encoder apparatus structure schematic diagram of N basic coding unit for embodiments of the invention;

Fig. 8 adopts j the basic encoding unit apparatus structure schematic diagram that adopts in N the parallel encoder apparatus structure for embodiments of the invention;

Fig. 9 is LDPC code coder (1/2 code check, code length are 2304) the device schematic diagram of embodiments of the invention.

Embodiment

The substep Methods for Coding that embodiments of the invention adopt string and combine provides a kind of linear complexity that has, the cascade encoding scheme that adopts precoding and parallel-convolution coding structure to combine.The code device critical piece of realizing this encoding scheme comprises information memory cell, precoding unit and coding unit, also comprise v (0) the check bit generation unit of particular verified position just, coding unit comprises data allocations unit and convolutional encoding unit, the generation unit of v (0) check bit links to each other with information memory cell, information memory cell links to each other with precoding unit, precoding unit links to each other with data allocations unit in the coding unit, the data allocations unit links to each other with the convolution coder unit, as shown in Figure 2.

Need to prove at this: the H that mentions in the embodiments of the invention is the check matrix of LDPC sign indicating number, H _bBe the generator matrix of check matrix H, H _BmBasic matrix for check matrix H.

The principle that device and method utilized of the LDPC parallel encoding that embodiments of the invention provided is:

Information sequence s is divided into k according to one group of z bit _bGroup, k _b=n _b-m _b, n _bBasic matrix H for the described check matrix H of IEEE802.16e _BmColumns, m _bBasic matrix H for the described check matrix H of IEEE802.16e _BmLine number, the information sequence after the grouping is defined as u, u=[u (0) ^T, u (1) ^T..., u (k _b-1) ^T] ^T, each element among the u is the z dimensional vector, i.e. u (i)=[s _Izs _Iz+1S _{(i+1) z-1}] ^TTo also become m with information sequence s corresponding check sequence by z bit one component _bGroup, the verification sequence after the grouping is defined as v, v=[v (0) ^T, v (1) ^T..., v (m _b-1) ^T] ^T, each element among the v is the z dimensional vector, i.e. v (i)=[p _Izp _Iz+1P _{(i+1) z-1}] ^T

According to IEEE802.16e, the generator matrix H of check matrix _bCan be write as following form:

Because first group z check bit v (0) can be known by simple operation, thereby v (0) can be regarded as k _b+ 1 group of information bit that is to say at original k _bIncrease by one group of check bit v (0) on the basis of group information bit, and H in the formula (9) _bCan equivalence be another kind of form, i.e. formula (10), so that corresponding with this variation of information bit:

Basic matrix H with check matrix H, check matrix _BmWrite as and formula (10) similar forms, can be obtained:

H＝[H ₁H ₂] (11a)

With

(11b)

H wherein ₁, promptly first submatrix of H is m _bZ * (k _b+ 1) z dimension matrix; H ₂, promptly second submatrix of H is m _bZ * (m _b-1) z dimension matrix; H _Bm1, i.e. H _BmFirst submatrix, be m _b* (k _b+ 1) dimension matrix; H _Bm2, i.e. H _BmSecond submatrix, be m _b* (m _b-1) dimension matrix.Can obtain the c=[u (0) that H and LDPC sign indicating number information bit and check bit constitute by formula (11a) ^T..., u (k _b-1) ^T, v (0) ^T..., v (m _b-1) ^T] ^TBetween satisfy:

H·c＝0 (12)

Make c ₁=[u (0) ^T..., u (k _b-1) ^T, v (0) ^T] ^T, c ₂=[v (1) ^T..., v (m _b-1) ^T] ^T, then have:

H ₁·c ₁+H ₂·c ₂＝0(13)

According to The above results and formula (13), the cataloged procedure of LDPC sign indicating number among the IEEE 802.16e can be divided into for three steps:

The first step is computation of parity bits vector v (0);

Second step was by precoding compute vector H ₁C ₁Value, this computational process can realize by circulating register and modulo 2 adder;

The 3rd step was according to H ₁C ₁Value, utilize convolution coder to obtain check bit vector c ₂

Specify basic coding process, code device and the coding method of LDPC parallel encoding provided by the invention below in conjunction with Fig. 3 and Fig. 4, the just structure of encoder and method for designing, Figure 3 shows that the basic encoding unit theory structure schematic diagram of LDPC among the IEEE802.16e provided by the invention, a kind of recursive convolutional encoder device theory structure schematic diagram that Fig. 4 adopts for the present invention.

For finishing described basic coding process, the encoder of LDPC sign indicating number will be made up of five basic devices among the IEEE 802.16e, that is: v (0) maker (generation unit of particular verified bit just), information-storing device (information memory cell just), precoder (precoding unit just), data distributor (data allocations unit just) and convolutional encoding unit:

(1) function of v (0) maker is according to formula (4), calculates the value of vector v (0).

(2) function of information-storing device is that information bit is stored by every z one group, so that participate in the precoding computing.

The design process of information-storing device is:

The circulating register number and the size that comprise altogether at first definite information-storing device: because the present invention regards the verification vector v (0) that calculates as special information bit, thereby the number of circulating register is n _b-m _b+ 1=k _b+ 1, size is z, and promptly each circulating register comprises z binary storage cell;

Determine the quantity of the corresponding tap of extracting out of each circulating register and the position of tap then, the quantity of tap and the position of tap are by the basic matrix H of LDPC code check matrix _BmRespective column in the quantity of non-negative element and numerical value determine.Such as, work as H _BmI show three during more than or equal to zero value ai, bi and ci, then extract three taps successively out from ai memory cell, a bi memory cell and ci memory cell of i circulating register, and send into corresponding modulo 2 adder, so that participate in the precoding computing.

(3) function of precoder is that the information bit and the check digit v (0) that will participate in each check equations concurrently carries out mould 2 and computing generation check bit.According to the different analysis results to formula (13), precoder has two kinds of corresponding design processes, is respectively:

First kind of design process of precoder is:

At first according to LDPC sign indicating number H _BmLine number be m _bDetermine to comprise in the precoder m _b-1 modulo 2 adder; This is because analyze formula (13) as can be known, in the recursive convolutional encoder device shown in Figure 4, list entries can by

Be total to m _bIndividual bit is reduced to

Be total to m _b-1 bit can obtain equally Be total to m _b-1 check bit that is to say, if illustrate with concrete example, the present invention adopts recursive convolutional encoder device as shown in Figure 5, list entries by Be reduced to

The time, equally can obtain the output verification bit and be

Under this processing mode, the m among Fig. 3 _bIndividual modulo 2 adder and m _bIndividual convolution coder can remove, and under this processing mode, later on corresponding treatment step can only be with the m among Fig. 3 _bIndividual modulo 2 adder and m _b-1 convolution coder removes.

Determine the bit number of each modulo 2 adder of input then: this input bit number is H in the formula (11b) _Bm1The row of corresponding row is heavy, i.e. the number of non-negative element in the corresponding row;

Determine the corresponding relation between circulating register tap output and the modulo 2 adder at last: as the basic matrix H of LDPC code check matrix _BmI when showing three nonnegative value ai (being positioned at j 1 row of check matrix), bi (j2 that is positioned at check matrix is capable) and ci (j3 that is positioned at check matrix is capable), then the tap of drawing from ai memory cell of i circulating register will be sent into j1 modulo 2 adder, the tap that bi memory cell drawn will be sent into j2 modulo 2 adder, and the tap that ci memory cell drawn will be sent into j3 modulo 2 adder.

Second kind of design process of precoder is:

Analyze formula (13) as can be known, in the convolution coder structure shown in Figure 4, can also with

Be total to m _b-1 bit is imported the recursive convolutional encoder device successively, obtains check bit successively

As shown in Figure 6.Under this recursive convolutional encoder device theory structure, each relevant with recursive convolutional encoder in this case step need change accordingly.Under this processing mode, the 1st modulo 2 adder and m among Fig. 3 _b-1 convolution coder can remove.That is to say, under this processing mode, except the 1st modulo 2 adder among Fig. 3 removed, first kind of design process of other step and precoder is identical, that is to say in this design process that corresponding definite method of using in first kind of design process of definite method of the corresponding relation between definite method of bit number of each modulo 2 adder of input and circulating register tap output and the modulo 2 adder and precoder all is identical.

(4) at the design process of two kinds of different precoders, data distributor also has two kinds of different schemes, and these two kinds of schemes are respectively:

Design process at the data distributor of first kind of precoder design process: data distributor is with m _b-1 data that modulo 2 adder obtains constantly in difference Send in the recursive convolutional encoder device and encode, generate the check bit c of LDPC sign indicating number ₂

The corresponding relation of modulo 2 adder dateout bit and recursive convolutional encoder device is: as t mod (m _b-1)=during j, then will Be total to m _b-1 bit is sent into j recursive convolutional encoder successively and is encoded, and obtains

Be total to m _b-1 check bit.

Design process at the data distributor of second kind of precoder design process: data distributor is with m _b-1 data that modulo 2 adder obtains constantly in difference

Send in the recursive convolutional encoder device and encode, generate the check bit c of LDPC sign indicating number ₂

The corresponding relation of modulo 2 adder dateout bit and recursive convolutional encoder device is: as t mod (m _b-1)=during j, then will Be total to m _b-1 bit is sent into j recursive convolutional encoder successively and is encoded, and obtains

Be total to m _b-1 check bit.

(5) convolution coder is to carry out convolutional encoding according to the data distributor output sequence, generates the pairing check bit of LDPC sign indicating number.At the design process of two kinds of different precoders, convolution coder also has two kinds of different schemes, and these two kinds of schemes are respectively:

At first kind of precoding design process, the design process of this convolution coder is:

At first, the number of determining the recursive convolutional encoder device is m _b-1, remove the m among Fig. 3 accordingly _bIndividual convolution coder;

Then, according to H among the IEEE 802.16e _BmCharacteristics, the recurrence multinomial of determining each recursive convolutional encoder device is 1/ (1+D), wherein D represents time of delay;

At last, the initial value of determining j recursive convolutional encoder device is

J=t modm wherein _b-1, j=0,1 ..., m _b-2.

At second kind of precoding design process, the design process of this convolution coder is:

At first, the number of determining the recursive convolutional encoder device is m _b-1, remove the m among Fig. 3 accordingly _bIndividual recursive convolutional encoder device;

Then, according to H among the IEEE 802.16e _BmCharacteristics, the recurrence multinomial of determining each recursive convolutional encoder device is 1/ (1+D), wherein D represents time of delay;

At last, the initial value of determining j recursive convolutional encoder device is

J=t modm wherein _b-1, j=0,1 ..., m _b-2.

(6) by described coding principle, determine the output bit of recursive convolutional encoder device and formula (13) the LDPC verification of giving vector c ₂Corresponding relation be:

$c_2={[{v\left(1\right)}^T,\&CenterDot;\&CenterDot;\&CenterDot;,{v(m_b-1)}^T]}^T={[{\left[\begin{array}{c}{p}_z\\ p_{z+1}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{2z-1}\end{array}\right]}^T{\left[\begin{array}{c}{p}_{2z}\\ p_{2z+1}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{3z-1}\end{array}\right]}^T\&CenterDot;\&CenterDot;\&CenterDot;{\left[\begin{array}{c}{p}_{(m_b-1)z}\\ p_{(m_b-1)z+1}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{m_{b}z-1}\end{array}\right]}^T]}^T={\left[{\left[\begin{array}{c}{p}_0^1\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">p</figure-callout>}}_1^1\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{z-1}^1\end{array}\right]}^T{\left[\begin{array}{c}{p}_0^2\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">p</figure-callout>}}_1^2\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{z-1}^2\end{array}\right]}^T{\&CenterDot;\&CenterDot;\&CenterDot;\left[\begin{array}{c}{p}_0^{m_b-1}\\ p_1^{m_b-1}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{z-1}^{m_b-1}\end{array}\right]}^T\right]}^T---\left(14\right)$

Thereby, vector v (0) and c ₂The common check bit v=[v (0) that determines the LDPC sign indicating number of giving among the IEEE 802.16e ^T, v (1) ^T..., v (m _b-1) ^T] ^T

By described coder structure and cataloged procedure,, illustrate that the corresponding relation between output verification bit and the clock cycle t was when the present invention adopted described coder structure to carry out the LDPC coding in conjunction with Fig. 3 and Fig. 4:

(1) when t=0, at the design process of first kind of precoder, precoding unit produces m _b-1 intermediate bit

Wherein

Directly send in the shift register of the 0th recursive convolutional encoder device, and as first check bit Output, promptly in first clock cycle, described encoder is exported a check bit

At the design process of second kind of precoder, precoding unit produces m _b-1 intermediate bit

Wherein

Directly send in the shift register of the 0th recursive convolutional encoder device, and as first check bit

Output, promptly in first clock cycle, described encoder is exported a check bit

(2) when t=1, at the design process of first kind of precoder, precoding unit produces m _b-1 intermediate bit

Wherein

Directly send in the shift register of the 1st recursive convolutional encoder device, and as first check bit

Output, simultaneously, second check bit of the 0th recursive convolutional encoder device output Promptly in second clock cycle, described encoder is exported two check bits simultaneously

With

At the design process of second kind of precoder, precoding unit produces m _b-1 intermediate bit Wherein Directly send in the shift register of the 1st recursive convolutional encoder device, and as first check bit

Output, simultaneously, second check bit of the 0th recursive convolutional encoder device output

Promptly in second clock cycle, described encoder is exported two check bits simultaneously

With

(3) when t=2, at the design process of first kind of precoder, precoding unit produces m _b-1 intermediate bit

Wherein

Directly send in the shift register of the 2nd recursive convolutional encoder device, and as first check bit Output, simultaneously, the 0th and the 1st recursive convolutional encoder device respectively exported a check bit With Promptly in the 3rd clock cycle, described encoder is exported three check bits simultaneously

With

At the design process of second kind of precoder, precoding unit produces m _b-1 intermediate bit

Wherein

Directly send in the shift register of the 2nd recursive convolutional encoder device, and as first check bit Output, simultaneously, the 0th and the 1st recursive convolutional encoder device respectively exported a check bit

With Promptly in the 3rd clock cycle, described encoder is exported three check bits simultaneously With

(4) the rest may be inferred, works as t=m _b-2 o'clock, at the design process of first kind of precoder, precoding unit produced m _b-1 intermediate bit

Wherein

Directly send into m _bIn the shift register of-2 recursive convolutional encoder devices, and as first check bit

Output, simultaneously, the 0th～the m _b-3 recursive convolutional encoder devices are respectively exported a check bit, and correspondence is respectively

Promptly at m _bIn-1 clock cycle, described encoder is exported m simultaneously _b-1 check bit

At the design process of second kind of precoder, precoding unit produces m _b-1 intermediate bit

Wherein

Directly send into m _bIn the shift register of-2 recursive convolutional encoder devices, and as-individual check bit

Output, simultaneously, the 0th～the m _b-3 recursive convolutional encoder devices are respectively exported a check bit, and correspondence is respectively

Promptly at m _bIn-1 clock cycle, described encoder is exported m simultaneously _b-1 check bit

(5) at the design process of these two kinds of precoders, as t 〉=(m _b-2) time, because all m _b-1 recursive convolutional encoder device all can be exported a check bit, and therefore described encoder will be exported m simultaneously _b-1 check bit;

Can find out by described process: remove initial m _bOutside-2 clock cycle, the generation m that can in each clock cycle, walk abreast of the LDPC coder structure by the present invention design _b-1 check bit has been avoided complicated vector sum matrix multiplication operation simultaneously.

On the basis of described coder structure, can realize parallel encoding by adopting N parallel organization, and then code efficiency is improved N doubly.

From above-mentioned coder structure and check bit generative process as can be seen, the verification vector c that is generated ₂In (m _b-1) z element can be divided into the z group and generate every group of (m that produces _b-1) can't influence each other between the individual check bit, thereby, can adopt a N same as shown in Figure 3 structure to carry out parallel encoding, thereby code efficiency is improved N doubly, wherein require N to satisfy z mod N=0.

Describedly adopt structure that N parallel encoder encode as shown in Figure 7, wherein the structure of j basic encoding unit as shown in Figure 8.The characteristics of this parallel encoder structure are:

(1) precoding unit in the N that the is adopted coder structure, data allocations unit and convolutional encoding unit structure all same as shown in Figure 3;

(2) number of memory cells that comprises in the number of the circulating register in N parallel encoder structure and each circulating register is also identical, and different is the sequence number difference of being drawn the memory cell of tap by each circulating register.Specifically, work as H _BmIn i show three nonnegative value a _{0, i}, b _{0, i}And c _{0, i}, then:

A in i the circulating register from first coder structure _{0, i}, b _{0, i}And c _{0, i}Memory cell is respectively drawn a tap;

The sequence number of drawing the memory cell of tap in i the circulating register from second coder structure is respectively (a _{0, i}+ z/N) mod z, (b _{0, i}+ z/N) mod z and (c _{0, i}+ z/N) mod z;

The sequence number of drawing the memory cell of tap in i the circulating register from the 3rd coder structure is respectively (a _{0, i}+ 2z/N) mod z, (b _{0, i}+ 2z/N) mod z and (c _{0, i}+ 2z/N) mod z;

The rest may be inferred, and the sequence number of drawing the memory cell of tap in i the circulating register from N coder structure is respectively (a _{0, i}+ (N-1) z/N) mod z, (b _{0, i}+ (N-1) z/N) mod z and (c _{0, i}+ (N-1) z/N) mod z.

(3) in (N-1) individual coder structures that increase in the circulating register, the tap of being drawn by memory cell is identical with first coding structure with the corresponding relation between the modulo 2 adder more.Specifically, work as H _BmIn three nonnegative value a of i row _{0, i}, b _{0, i}And c _{0, i}, correspond respectively to H _BmJ1, j2 and j3 when capable, then:

In first coding structure, a in i the circulating register _{0, i}, b _{0, i}And c _{0, i}Three taps that memory cell is drawn are make a gift to someone j1, j2 and j3 modulo 2 adder of correspondence respectively;

In second coder structure, (a in i the circulating register _{0, i}+ z/N) mod z, (b _{0, i}+ z/N) mod z and (c _{0, i}+ z/N) three taps of drawing of mod z memory cell respectively correspondence send into j1, j2 and j3 modulo 2 adder;

In the 3rd coder structure, (a in i the circulating register _{0, i}+ 2z/N) mod z, (b _{0, i}+ 2z/N) mod z and (c _{0, i}+ 2z/N) three taps of drawing of mod z memory cell respectively correspondence send into j1, j2 and j3 modulo 2 adder;

The rest may be inferred, in N the coder structure, and (a in i the circulating register _{0, i}+ (N-1) z/N) mod z, (b _{0, i}+ (N-1) z/N) mod z and (c _{0, i}+ (N-1) z/N) three taps of drawing of mod z memory cell respectively correspondence send into j1, j2 and j3 modulo 2 adder.

(4) by shown in Figure 7, the output bit of recursive convolutional encoder device and formula (13) the LDPC verification of giving vector c ₂Corresponding relation be:

Thereby, vector v (0) and c ₂The common check bit v=[v (0) that determines the LDPC sign indicating number of giving among the IEEE 802.16e ^T, v (1) ^T..., v (m _b-1) ^T] ^T

By described coder structure and cataloged procedure, (, remove the m in the precoder among Fig. 8 at the design process of first kind of precoder in conjunction with Fig. 7 and Fig. 8 _bM in individual modular two addition device and the acoustic convolver unit _b-1 recursive convolutional encoder device; At the design process of second kind of precoder, remove the 1st modular two addition device in the precoder among Fig. 8 and the m in the acoustic convolver unit _b-1 recursive convolutional encoder device), illustrate that the present invention adopts when coder structure carries out the LDPC coding as shown in Figure 7 and Figure 8, the corresponding relation between output verification bit and the clock cycle t is:

(1) when t=0, at the design process of first kind of precoder, the precoding unit in corresponding with it each basic encoding unit structure respectively produces m _b-1 intermediate bit

Remove the m in the precoder among Fig. 5 _bM in individual modular two addition device and the acoustic convolver unit _b-1 recursive convolutional encoder device, wherein

Directly send in the shift register of the 0th recursive convolutional encoder device in the 1st the basic encoding unit structure, and as first check bit

Output,

Directly send in the shift register of the 0th recursive convolutional encoder device in the 2nd the basic encoding unit structure, and as first check bit

Output, the rest may be inferred, Directly send in the shift register of the 0th recursive convolutional encoder device in N the basic encoding unit structure, and as first check bit

Output, thereby, in first clock cycle, described encoder will and each and every one check bit of line output N

At the design process of second kind of precoder, the precoding unit in corresponding with it each basic encoding unit structure respectively produces m _b-1 intermediate bit

Wherein Directly send in the shift register of the 0th recursive convolutional encoder device in the 1st the basic encoding unit structure, and as first check bit

Output,

Directly send in the shift register of the 0th recursive convolutional encoder device in the 2nd the basic encoding unit structure, and as first check bit

Output, the rest may be inferred,

Directly send in the shift register of the 0th recursive convolutional encoder device in N the basic encoding unit structure, and as first check bit

Output, thereby, in first clock cycle, described encoder will and each and every one check bit of line output N

(2) when t=1, at the design process of first kind of precoder, the precoding unit in corresponding with it each basic encoding unit structure respectively produces m _b-1 intermediate bit

Wherein

Directly send in the shift register of the 1st recursive convolutional encoder device in the 1st the basic encoding unit structure, and as first check bit

Output,

Directly send in the shift register of the 1st recursive convolutional encoder device in the 2nd the basic encoding unit structure, and as first check bit

Output, the rest may be inferred,

Directly send in the shift register of the 1st recursive convolutional encoder device in N the basic encoding unit structure, and as first check bit

Output, simultaneously, the 0th recursive convolutional encoder device in all basic encoding unit structures respectively exported a check bit Thereby in second clock cycle, described encoder will be exported 2N check bit simultaneously With

At the design process of second kind of precoder, the precoding unit in corresponding with it each basic encoding unit structure respectively produces m _b-1 intermediate bit

Wherein

Directly send in the shift register of the 1st recursive convolutional encoder device in the 1st the basic encoding unit structure, and as first check bit Output, Directly send in the shift register of the 1st recursive convolutional encoder device in the 2nd the basic encoding unit structure, and as first check bit

Output, the rest may be inferred, Directly send in the shift register of the 1st recursive convolutional encoder device in N the basic encoding unit structure, and as first check bit

Output, simultaneously, the 0th recursive convolutional encoder device in all basic encoding unit structures respectively exported a check bit

Thereby in second clock cycle, described encoder will be exported 2N check bit simultaneously

With

(3) the rest may be inferred, works as t=m _b-2 o'clock, described encoder will be exported N (m simultaneously _b-1) individual check bit;

(4) at the design process of these two kinds of precoders, as t 〉=m _b-2 o'clock, owing to the m in all N the basic encoding unit structures _b-1 recursive convolutional encoder device all can be exported a check bit, and therefore described encoder will be exported N (m simultaneously _b-1) individual check bit.

Can find out by described process: remove initial m _bOutside-2 clock cycle, the generation N (m that can in each clock cycle, walk abreast of the LDPC parallel encoder structure by the present invention design _b-1) individual check bit.

By described encoder principle and cataloged procedure, adopt N parallel encoding structure, can guarantee in each clock cycle, to produce N group check bit, thereby code efficiency is N times of employing single encoded device structure shown in Figure 3.

Specific embodiment:

Be example with 1/2 code rate LDPC code among the IEEE P802.16e below, the specific implementation process of coding is described.Table one is the pairing basic matrix H of the check matrix of LDPC sign indicating number _Bm, n wherein _b=24, m _b=12, z=96, code length n=2304,1～12 row corresponding informance bit of matrix, the corresponding check bit of 13～24 row ,-1 corresponding z * z null matrix, other corresponding z * z unit matrix figure place that circulates to the right.

The basic matrix of table one 1/2 code check LDPC check matrix

Annotate: for convenience of explanation, first row of form and first row have been represented the columns and the line number of check matrix respectively.

Basic coding process and coder structure that embodiments of the invention provide are as follows:

Embodiment 1: according to described technical scheme, at first kind of precoder design process, H _BmRemove last column, remove the m of back again _b-1 row promptly remove 11 row that remove the back in the table one behind the 12 row again, constitute H " _B1Be 11x13, i.e. the H that gives in the formula (11b) _Bm1Remove last column, H _BmBack 11 row that remove after last column constitute H _B2Be 11x11, i.e. the H ' that gives in the formula (11b) _Bm2Remove last column, corresponding encoder comprises information memory cell as shown in Figure 9, precoding unit, and four main devices in data allocations unit and convolutional encoding unit wherein comprise 13 circulating registers in the information memory cell, comprise m in the precoding unit _b-1=11 modulo 2 adder, convolutional encoding comprises m in the unit _b-1=11 recursive convolutional encoder device.At the design process of second kind of precoder, H _BmRemove first row in the table one, remove the m of back again _b-1 row promptly remove 11 row that remove the back behind the 12 row again, constitute H _B1Be 11x13, i.e. the H that gives in the formula (11b) _Bm1Remove first row, H _BmBack 11 row that remove behind first row constitute H _B2Be 11x11, i.e. the H that gives in the formula (11b) _Bm2Remove last column.Below being that example illustrates specific implementation at first kind of precoder.The input bit number of each modulo 2 adder is by H _B1The row of middle corresponding row is heavily definite: H _B1Have 5 more than or equal to 0 number in first row, thereby the input bit number of first modulo 2 adder is 5; H _B1Have 5 more than or equal to 0 number in second row, thereby the input bit number of second modulo 2 adder is 5; H _B1Have 5 in the third line more than or equal to 0 number, thereby the input bit number of the 3rd modulo 2 adder is 5; H _B1Have 4 in the fourth line more than or equal to 0 number, thereby the input bit number of the 4th modulo 2 adder is 4; H _B1Have 4 in the fifth line more than or equal to 0 number, thereby the input bit number of the 5th modulo 2 adder is 4; H _B1Have 5 more than or equal to 0 number in the 6th row, thereby the input bit number of the 6th modulo 2 adder is 5; H " _B1Have 4 more than or equal to 0 number in the 7th row, thereby the input bit number of the 7th modulo 2 adder is 4; H " _B1Have 4 more than or equal to 0 number in the 8th row, thereby the input bit number of the 8th modulo 2 adder is 4; H " _B1Have 5 more than or equal to 0 number in the 9th row, thereby the input bit number of the 9th modulo 2 adder is 5; H " _B1Have 4 more than or equal to 0 number in the tenth row, thereby the input bit number of the tenth modulo 2 adder is 4; H " _B1Have 4 in the tenth delegation more than or equal to 0 number, thereby the input bit number of the 11 modulo 2 adder is 4.

The principle of utilizing encoder shown in Figure 9 to encode is:

(1) matrix can obtain only to contain the check equations of the 13rd row check digit by the row addition, calculates verification vector v (0) thus, and v (0) is deposited in the circulating register 13;

(2) 1152 information bits are become 12 groups according to every z=96 bit one component, send into respectively in circulating register 1～circulating register 12;

(3) according to the basic matrix of check matrix shown in the table one after the change, determine the quantity and the position of the tap of being drawn by each circulating register: basic matrix first row of check matrix contain 61 and 12 two more than or equal to zero value, thereby the 61st memory cell and the 12nd memory cell from circulating register 1 are drawn a tap respectively; The basic matrix secondary series of check matrix contains 94,27 and 11 3 more than or equal to zero value, thereby the 94th memory cell from circulating register 2, the 27th memory cell and the 11st memory cell are drawn a tap respectively; The rest may be inferred, contain 7 and 0 two more than or equal to zero value in check matrix the 13rd row, thereby the 7th memory cell and the 0th memory cell from circulating register 13 drawn a tap respectively;

(4) according to the basic matrix of check matrix shown in the table one after the change, determine the tap and the corresponding relation of 11 modulo 2 adders that circulating register is drawn: basic matrix first row of check matrix contain two lay respectively at matrix H more than or equal to zero values 61 and 12 _BmThe 4th row and the 9th capable, thereby send into the 4th modulo 2 adder by the tap that the 61st memory cell is drawn, the 9th modulo 2 adder sent in the 12nd tap that memory cell is drawn; Three values 94,27 and 11 more than or equal to zero that the basic matrix secondary series of check matrix contains lay respectively at H _BmThe 1st row, the 2nd row and eighth row, thereby the 94th tap that memory cell is drawn send into the 1st modulo 2 adder, the 2nd modulo 2 adder sent in the 27th tap that memory cell is drawn, the 8th modulo 2 adder sent in the 11st tap that memory cell is drawn; Six values 73,47,39,95,73 and 7 more than or equal to zero that basic matrix the 3rd row of check matrix contain lay respectively at H _BmThe 1st the row, the 4th the row, the 5th the row, the 7th the row, eighth row and the 11st the row, thereby the 1st and the 8th modulo 2 adder are sent in two taps that the 73rd memory cell drawn respectively, the 4th modulo 2 adder sent in the 47th tap that memory cell is drawn, the 5th modulo 2 adder sent in the 39th tap that memory cell is drawn, the 7th modulo 2 adder sent in the 95th tap that memory cell is drawn, and the 11st modulo 2 adder sent in the 7th tap that memory cell is drawn; The rest may be inferred, the basic matrix H of check matrix _BmThree values 7 and 0 more than or equal to zero that the 13 row contain lay respectively at H _BmThe 1st row and the 5th capable, thereby the 1st and the 5th modulo 2 adder are sent in the tap that the 7th memory cell and the 0th memory cell are drawn respectively respectively;

(5), determine precoding module output bit according to present clock

Corresponding relation with 11 recursive convolutional encoder devices: when t mod 11=j, then will

Totally 11 bit correspondences are sent into j recursive convolutional encoder device and are encoded, j=0, and 1 ..., m _b-2, wherein

Directly determine the initial condition of corresponding recursive convolutional encoder device, obtain

Totally 11 check bits.

(6) by described coding principle, determine the output bit of recursive convolutional encoder device and formula (13) the LDPC verification of giving vector c ₂Relation be:

$c_2={[{v\left(1\right)}^T,\&CenterDot;\&CenterDot;\&CenterDot;,{v(m_b-1)}^T]}^T={[{\left[\begin{array}{c}{p}_{96}\\ p_{97}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{191}\end{array}\right]}^T{\left[\begin{array}{c}{p}_{192}\\ p_{193}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{287}\end{array}\right]}^T\&CenterDot;\&CenterDot;\&CenterDot;{\left[\begin{array}{c}{p}_{1056}\\ p_{1057}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{1151}\end{array}\right]}^T]}^T={\left[{\left[\begin{array}{c}{p}_0^1\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">p</figure-callout>}}_1^1\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{95}^1\end{array}\right]}^T{\left[\begin{array}{c}{p}_0^2\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">p</figure-callout>}}_1^2\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{95}^2\end{array}\right]}^T{\&CenterDot;\&CenterDot;\&CenterDot;\left[\begin{array}{c}{p}_0^{111}\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">p</figure-callout>}}_1^{11}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{95}^{11}\end{array}\right]}^T\right]}^T$

Thereby, vector v (0) and c ₂The common check bit v=[v (0) that determines the LDPC sign indicating number of giving among the IEEE 802.16e ^T, v (1) ^T..., v (11) ^T] ^T

For further improving code efficiency, adopt and carry out parallel encoding with N identical as shown in Figure 9 structure, code efficiency can be improved N doubly, wherein require Z mod N ≡ 0, in the present embodiment, select N=2.

The characteristics of the parallel encoder of N=2 structure of described employing are:

(1) precoding module, data allocations module and convolutional encoding module in two basic encoding units that adopted are all identical with structure shown in Figure 9;

The memory module number that comprises in the number of the circulating register in (2) two basic encoding unit structures and each circulating register is also identical, and different is the sequence number difference of being drawn the memory module of tap by each circulating register.Specifically:

When the 61st and 12 memory modules were respectively drawn a tap in the 1st circulating register from first coding structure, the sequence number of then drawing the memory module of three taps in the 1st circulating register in second coding structure was respectively (63+96/2) mod 96=15 and (12+96/2) mod 96=60;

When the 94th, 27 and 11 memory modules were respectively drawn a tap in the 2nd circulating register from first coding structure, the sequence number of then drawing the memory module of three taps in the 2nd circulating register in second coding structure was respectively (94+96/2) mod 96=46, (27+96/2) mod 96=75 and (11+96/2) mod 96=59;

The rest may be inferred, when the 7th and 0 memory module was respectively drawn a tap in the 13rd circulating register from first coding structure, the sequence number of then drawing the memory module of two taps in the 13rd circulating register in second coding structure was respectively (7+96/2) mod 96=55 and (0+96/2) mod96=48.

(3) in (N-1)=1 coder structure that increase in the circulating register, the tap of being drawn by memory module is identical with first basic encoding unit structure with the corresponding relation between the modulo 2 adder more.Specifically:

Work as H _BmIn the 1st row two nonnegative values 61 and 12 correspond respectively to H _BmThe 4th and 9 whens row, then in first coding structure, the 4th and 9 modulo 2 adder sent in three taps that the 61st and 12 memory modules are drawn in first circulating register correspondence respectively; In second coder structure, in first circulating register, by (63+96/2) mod 96=15 and (12+96/2) two taps of drawing of mod 96=60 memory module send into the 4th and 9 modulo 2 adder respectively;

Work as H _BmIn the 2nd row three nonnegative values 94,27 and 11 correspond respectively to H _BmThe 1st, 2 and 8 whens row, then in first coding structure, the 1st, 2 and 8 modulo 2 adder sent in three taps that the 94th, 27 and 11 memory modules are drawn in second circulating register correspondence respectively; In second coder structure, by (94+96/2) mod 96=46, (27+96/2) mod96=75 in second circulating register and (11+96/2) three taps of drawing of mod 96=59 memory module send into the 1st, 2 and 8 modulo 2 adder respectively;

The rest may be inferred, works as H _BmIn the 13rd row three nonnegative values 7 and 0 correspond respectively to H _BmThe 1st and 6 whens row, then in first coding structure, the 1st and 6 modulo 2 adder sent in two taps that the 7th and 0 memory module is drawn in the 13rd circulating register correspondence respectively; In second coder structure, in the 13rd circulating register (7+96/2) mod 96=55 and (0+96/2) mod 96=48 memory module draw three taps respectively correspondence send into the 1st and 6 modulo 2 adder;

Embodiment 2: at second kind of precoder design process, after the basic matrix of check matrix removes in the table one first row, remove 11 row of back again, constitute H ' " _B1Be 11x13, promptly remove preceding 13 row of the basic matrix of LDPC code check matrix shown in first table one of going in the table one, the submatrix H that gives in the make-up formula (11b) _Bm1Remove first row, the matrix H that gives in all the other 11 row make-up formulas (11b) _Bm2Remove first row, corresponding encoder comprises information memory cell as shown in Figure 9, precoding unit, and four main devices in data allocations unit and convolutional encoding unit wherein comprise 13 circulating registers in the information memory cell, comprise m in the precoding unit _b-1=11 modulo 2 adder, convolutional encoding comprises m in the unit _b-1=11 recursive convolutional encoder device.At the design process of second kind of precoder, after the basic matrix of check matrix removes in the table one first row, remove 11 row of back again, constitute H ' " _B1Be 11x13,

The input bit number of each modulo 2 adder is by H ' " _B1The row of middle corresponding row is heavily definite: H ' " _B1First row, just have 5 more than or equal to 0 number in second row in the table one, thereby the input bit number of first modulo 2 adder is 5; H ' " _B1Second row just have 5 in the table one in the third line more than or equal to 0 number, thereby the input bit number of second modulo 2 adder is 5; H ' " _B1Have 4 in the third line more than or equal to 0 number, thereby the input bit number of the 3rd modulo 2 adder is 4; H ' " _B1Have 4 in the fourth line more than or equal to 0 number, thereby the input bit number of the 4th modulo 2 adder is 4; H ' " _B1Have 5 in the fifth line more than or equal to 0 number, thereby the input bit number of the 5th modulo 2 adder is 5; H ' " _B1Have 4 more than or equal to 0 number in the 6th row, thereby the input bit number of the 6th modulo 2 adder is 4; H ' " _B1Have 4 more than or equal to 0 number in the 7th row, thereby the input bit number of the 7th modulo 2 adder is 4; H ' " _B1Have 5 more than or equal to 0 number in the 8th row, thereby the input bit number of the 8th modulo 2 adder is 5; H ' " _B1Have 4 more than or equal to 0 number in the 9th row, thereby the input bit number of the 9th modulo 2 adder is 4; H ' " _B1Have 4 more than or equal to 0 number in the tenth row, thereby the input bit number of the tenth modulo 2 adder is 4; H ' " _B1Have 5 in the tenth delegation more than or equal to 0 number, thereby the input bit number of the 11 modulo 2 adder is 5.

The principle of utilizing encoder shown in Figure 9 to encode is:

(1) matrix can obtain only to contain the check equations of the 13rd row check digit by the row addition, calculates verification vector v (0) thus, and v (0) is deposited in the circulating register 13;

(2) 1152 information bits are become 12 groups according to every z=96 bit one component, send into respectively in circulating register 1～circulating register 12;

(3) according to the basic matrix of check matrix shown in the table one, determine the quantity and the position of the tap of being drawn by each circulating register: basic matrix first row of check matrix contain 61,12 and 43 3 more than or equal to zero value, thereby the 61st memory cell from circulating register 1, the 43rd memory cell and the 12nd memory cell are drawn a tap respectively; The basic matrix secondary series of check matrix contains 27 and 11 two more than or equal to zero value, thereby the 27th memory cell and the 11st memory cell are drawn a tap respectively from circulating register 2; The rest may be inferred, contain 0 and 7 two more than or equal to zero value in basic matrix the 13rd row of check matrix, thereby the 7th memory cell and the 0th memory cell from circulating register 13 respectively drawn a tap;

(4) according to the basic matrix of check matrix shown in the table one, determine the tap that circulating register is drawn and the corresponding relation of 11 modulo 2 adders: three values 61,12 and 43 more than or equal to zero that basic matrix first row of check matrix contain lay respectively at H _BmThe 3rd row, eighth row and the 11st row, thereby send into the 3rd modulo 2 adder by the tap that the 61st memory cell is drawn, the 8th modulo 2 adder sent in the 12nd tap that memory cell is drawn, the 11st modulo 2 adder sent in the 43rd tap that memory cell is drawn; Two values 27 and 11 more than or equal to zero that the basic matrix secondary series of check matrix contains lay respectively at H _BmThe 1st row and the 7th capable, thereby the 27th tap that memory cell is drawn send into the 1st modulo 2 adder, the 7th modulo 2 adder sent in the 11st tap that memory cell is drawn; Five values 47,39,95,73 and 7 more than or equal to zero that basic matrix the 3rd row of check matrix contain lay respectively at H _BmThe 3rd the row, the 4th the row, the 6th the row, the 7th the row and the 10th the row, thereby the 3rd modulo 2 adder sent in the 47th tap that memory cell is drawn, the 4th modulo 2 adder sent in the 39th tap that memory cell is drawn, the 6th modulo 2 adder sent in the 95th tap that memory cell is drawn, the 7th modulo 2 adder sent in the 73rd tap that memory cell is drawn, and the 10th modulo 2 adder sent in the 7th tap that memory cell is drawn; The rest may be inferred, and two values 0 and 7 more than or equal to zero that basic matrix the 13 row of check matrix contain lay respectively at H _BmThe 4th row and the 11st capable, thereby the 0th tap that memory cell is drawn send into the 4th modulo 2 adder, the 11st modulo 2 adder sent in the 7th tap that memory cell is drawn;

(5), determine precoding module output bit according to present clock

Corresponding relation with 11 recursive convolutional encoder devices: when t mod 11=j, then will

Totally 11 bit correspondences are sent into j recursive convolutional encoder device and are encoded, j=0, and 1 ..., m _b-2, wherein

Directly determine the initial condition of corresponding recursive convolutional encoder device, obtain

Totally 11 check bits.

(6) by described coding principle, determine the output bit of recursive convolutional encoder device and formula (13) the LDPC verification of giving vector c ₂Relation be:

$c_2={[{v\left(1\right)}^T,\&CenterDot;\&CenterDot;\&CenterDot;,{v(m_b-1)}^T]}^T={[{\left[\begin{array}{c}{p}_{96}\\ p_{97}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{191}\end{array}\right]}^T{\left[\begin{array}{c}{p}_{192}\\ p_{193}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{287}\end{array}\right]}^T\&CenterDot;\&CenterDot;\&CenterDot;{\left[\begin{array}{c}{p}_{1056}\\ p_{1057}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{1151}\end{array}\right]}^T]}^T={\left[{\left[\begin{array}{c}{p}_0^1\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">p</figure-callout>}}_1^1\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{95}^1\end{array}\right]}^T{\left[\begin{array}{c}{p}_0^2\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">p</figure-callout>}}_1^2\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{95}^2\end{array}\right]}^T{\&CenterDot;\&CenterDot;\&CenterDot;\left[\begin{array}{c}{p}_0^{111}\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H061E4891320061205E000021.png,H061E4891320061205E000033.png"\; state="\{\{state\}\}">p</figure-callout>}}_1^{11}\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{95}^{11}\end{array}\right]}^T\right]}^T$

Thereby, vector v (0) and c ₂The common check bit v=[v (0) that determines the LDPC sign indicating number of giving among the IEEE 802.16e ^T, v (1) ^T..., v (11) ^T] ^T

For further improving code efficiency, adopt N identical as shown in Figure 9 structure to carry out parallel encoding, code efficiency can be improved N doubly, wherein require Z mod N=0, in the present embodiment, select N=2.

The characteristics of the parallel encoder of N=2 structure of described employing are:

(1) precoding module, data allocations module and convolutional encoding module in two basic encoding units that adopted are all identical with structure shown in Figure 9;

The memory module number that comprises in the number of the circulating register in (2) two basic encoding unit structures and each circulating register is also identical, and different is the sequence number difference of being drawn the memory module of tap by each circulating register.Specifically:

When the 61st, 12 and 43 memory modules were respectively drawn a tap in the 1st circulating register from first coding structure, the sequence number of then drawing the memory module of three taps in the 1st circulating register in second coding structure was respectively (63+96/2) mod 96=15, (12+96/2) mod 96=60 and (43+96/2) mod 96=91;

When the 27th and 11 memory modules were respectively drawn a tap in the 2nd circulating register from first coding structure, the sequence number of then drawing the memory module of two taps in the 2nd circulating register in second coding structure was respectively (27+96/2) mod 96=75 and (11+96/2) mod 96=59;

The rest may be inferred, when the 0th and 7 storage modules in the 13rd circulating register from first coding structure when respectively drawing a tap, the sequence number of then drawing the memory module of two taps in the 13rd circulating register in second coding structure is respectively (0+96/2) mod 96=48 and (7+96/2) mod96=55.

(3) in (N-1)=1 coder structure that increase in the circulating register, the tap of being drawn by memory module is identical with first basic encoding unit structure with the corresponding relation between the modulo 2 adder more.Specifically:

Basic matrix H when check matrix _BmIn the 1st row three nonnegative values 61,12 and 43 correspond respectively to H _BmThe 3rd row, eighth row and the 11st when row, then in first coding structure, the 3rd, 8 and 11 modulo 2 adder sent in three taps that the 61st, 12 and 43 memory modules are drawn in first circulating register correspondence respectively; In second coder structure, in first circulating register, by (61+96/2) mod96=15, (12+96/2) mod 96=60 and (43+96/2) three taps of drawing of mod 96=91 memory module send into the 3rd, 8 and 11 modulo 2 adder respectively;

Basic matrix H when check matrix _BmIn the 2nd row two nonnegative values 27 and 11 correspond respectively to H _BmThe 1st and 7 whens row, then in first coding structure, the 1st and 7 modulo 2 adder sent in two taps that the 27th and 11 memory modules are drawn in second circulating register correspondence respectively; In second coder structure, by (27+96/2) mod 96=75 in second circulating register and (11+96/2) two taps of drawing of mod 96=59 memory module send into the 1st and 7 modulo 2 adder respectively;

The rest may be inferred, as the basic matrix H of check matrix _BmIn the 13rd row three nonnegative values 0 and 7 correspond respectively to H _BmThe 5th and 11 whens row, then in first coding structure, the 5th and 11 modulo 2 adder sent in two taps that the 0th and 7 memory modules are drawn in the 13rd circulating register correspondence respectively; In second coder structure, in the 13rd circulating register (0+96/2) mod 96=48 and (7+96/2) the mod96=55 memory module draw three taps respectively correspondence send into the 5th and 11 modulo 2 adder;

(4) by shown in Figure 9, the output bit of recursive convolutional encoder device and formula (13) the LDPC verification of giving vector c ₂Relation be:

Thereby, vector v (0) and c ₂The common check bit v=[v (0) that determines the LDPC sign indicating number of giving among the IEEE 802.16e ^T, v (1) ^T..., v (11) ^T] ^T

In sum, embodiments of the invention provide a kind of device and method of low-density checksum LDPC parallel coding, LDPC code device provided by the invention adopts circulating register and modulo 2 adder, realize simple, avoided the computing of vector sum multiplication of matrices, complexity is relatively low, and the coding time delay reduces; The present invention is decomposed into precoder and a plurality of convolution coder with the LDPC code device, can realize parallel encoding at an easy rate; Code device provided by the invention has very strong extensibility, adopt N basic encoding unit to carry out parallel encoding, make code efficiency bring up to N times of the single basic coding device of employing, thereby in the hardware complexity allowed band, can adopt parallel organization as much as possible, improve code efficiency greatly.

So far, the present invention is that example has illustrated code device and the cataloged procedure that the present invention is concrete with 1/2 code rate LDPC code only, but the present invention is not only limited to this embodiment, all are based on the device of LDPC parallel encoding, described device comprises information memory cell and precoding unit, information memory cell links to each other with precoding unit, letter

The breath memory cell comprises one or more circulating register, be used for the information bit position stored information sequence that comprises some according to one group, determine the quantity and the position of described circulating register tap, be convenient to the computing that described information sequence carries out precoding unit; Precoding unit comprises one or more modulo 2 adder; determine corresponding relation between described circulating register tap output and the described modulo 2 adder according to the quantity of circulating register tap in the information memory cell and position; be used for according to information bit position that participates in check equations and the precoding that verification sequence is finished in the particular verified position; be convenient to further finish the technical scheme of LDPC parallel encoding; no matter which kind of form of employing is all within protection scope of the present invention.

The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.

Claims (10)

1. the device of a low-density checksum LDPC parallel coding is characterized in that, comprises information memory cell, precoding unit and coding unit, and information memory cell links to each other with precoding unit, and precoding unit links to each other with coding unit, wherein,

Information memory cell comprises one or more circulating register, be used for information sequence is stored in corresponding circulating register according to every group of information bit that comprises some, determine the quantity and the position of described circulating register tap, be specially: when adopting a described device to encode, the quantity of the tap of described circulating register correspondence and position are determined according to the quantity and the numerical value of the non-negative element in the basic matrix respective column of LDPC code check matrix; When adopting more than one described device to carry out parallel encoding, the quantity of the tap of described circulating register correspondence determines that according to the quantity of the non-negative element in the basic matrix respective column of LDPC code check matrix the position of the tap of described circulating register correspondence is determined according to the numerical value of the non-negative element in the basic matrix respective column of LDPC code check matrix and the sequence number of described device;

Precoding unit comprises one or more modulo 2 adder, described precoding unit is used for determining corresponding relation between described circulating register tap output and the modulo 2 adder according to the quantity of information memory cell circulating register tap and position, and the nodulo-2 addition computing is carried out to finish the precoding of verification sequence in the information bit and the particular verified position that will participate in check equations, the quantity of described modulo 2 adder is determined by the line number of the basic matrix of LDPC code check matrix, imports the quantity of the bit of corresponding modulo 2 adder and is determined by the quantity of non-negative element in the first submatrix corresponding row of the basic matrix of LDPC check matrix;

Coding unit, the LDPC parallel encoding is further finished in the precoding that is used for finishing according to described precoding unit, coding unit comprises data allocations unit and convolutional encoding unit, wherein the data allocations unit links to each other with described precoding unit, the data allocations unit links to each other with the convolutional encoding unit, and described data allocations unit is used for the modulo 2 adder of described precoding unit is sent into corresponding convolution coder in the convolutional encoding unit respectively in the data that difference obtains constantly; Described convolutional encoding unit comprises one or more convolution coder, described convolution coder is used for the described data of its reception are encoded, generate and the described information sequence corresponding check of LDPC sign indicating number sequence, wherein the quantity of convolution coder is determined according to the quantity of modulo 2 adder in the precoding unit.

2. the device of a kind of LDPC parallel encoding according to claim 1, it is characterized in that, described information sequence is stored in the corresponding circulating register by group, the quantity of described circulating register determines that according to described group number the size of described circulating register is determined according to the quantity of described group of information bit that comprises;

Described group number is determined according to the quantity that one group of information bit that comprises some is divided into the group of specifying number by described information sequence.

3. the device of a kind of LDPC parallel encoding according to claim 1, it is characterized in that, described device also comprises the generation unit of particular verified position, the generation unit of particular verified position links to each other with described information memory cell, is used for generating the particular verified position according to the relation between check matrix and the LDPC information bit.

4. the device of a kind of LDPC parallel encoding according to claim 1 is characterized in that, the numbering of the modulo 2 adder of described non-negative element is determined to receive in the position of being expert at according to the non-negative element in the respective column in the basic matrix of LDPC check matrix.

5. the device of a kind of LDPC parallel encoding according to claim 1 is characterized in that,

According to the characteristics of the basic matrix of check matrix, determine the multinomial of each convolution coder; Determine the structure of described convolution coder according to described multinomial.

6. the method for a low-density checksum LDPC parallel coding is characterized in that, the step that the device of employing LDPC parallel encoding is encoded comprises:

Information sequence is stored in the corresponding circulating register according to every group of information bit that comprises some, determine the quantity and the position of described circulating register tap, be specially: when adopting a described device to encode, the quantity of the tap of described circulating register correspondence and position are determined according to the quantity and the numerical value of the non-negative element in the basic matrix respective column of LDPC code check matrix; When adopting more than one described device to carry out parallel encoding, the quantity of the tap of described circulating register correspondence determines that according to the quantity of the non-negative element in the basic matrix respective column of LDPC code check matrix the position of the tap of described circulating register correspondence is determined according to the numerical value of the non-negative element in the basic matrix respective column of LDPC code check matrix and the sequence number of described device;

Corresponding relation between the modulo 2 adder of using in the tap output of determining described circulating register according to the quantity and the position of described circulating register tap and the precoding process, and the nodulo-2 addition computing is carried out to finish the precoding of verification sequence in the information bit and the particular verified position that will participate in check equations, further finish the LDPC parallel encoding, the described step of further finishing the LDPC parallel encoding comprises: described modulo 2 adder is sent into respectively in the corresponding convolution coder in the data that difference obtains constantly encoded, described convolution coder is used for the described data of sending into are encoded, generate and the described information sequence corresponding check of LDPC sign indicating number sequence, wherein the quantity of convolution coder is determined according to the quantity of modulo 2 adder in the precoding unit, the quantity of described modulo 2 adder is determined by the line number of the basic matrix of LDPC code check matrix, imports the quantity of the bit of corresponding modulo 2 adder and is determined by the quantity of non-negative element in the first submatrix corresponding row of the basic matrix of LDPC check matrix.

7. the method for a kind of LDPC parallel encoding according to claim 6 is characterized in that, described information sequence is comprised according to the step that every group of information bit that comprises some is stored in the corresponding circulating register:

Described information sequence is stored in the corresponding circulating register by group, and the quantity of described circulating register determines that according to described group number the size of described circulating register is determined according to the quantity of described group of information bit that comprises;

Described group number is determined according to the quantity that one group of information bit that comprises some is divided into the group of specifying number by described information sequence.

8. the method for a kind of LDPC parallel encoding according to claim 6, it is characterized in that, also comprise before the quantity of described definite described circulating register tap and the step of position: generate the particular verified position according to the relation between check matrix and the LDPC information bit.

9. the method for a kind of LDPC parallel encoding according to claim 6 is characterized in that, wherein receives the position that the numbering of the modulo 2 adder of described non-negative element is expert at according to non-negative element in the basic matrix respective column of LDPC check matrix and determines.

10. the method for a kind of LDPC parallel encoding according to claim 6 is characterized in that, the described step of further finishing the LDPC parallel encoding specifically comprises:

According to the characteristics of specifying check matrix, determine the multinomial of each convolution coder; Determine the structure of described convolution coder according to described multinomial.

Images