CN1937413A - Double-turbine structure low-density odd-even check code decoder - Google Patents

Abstract

It includes the verification node processing unit (VeNP) array, the variable node processing unit (VaNP) array, the verification node output info memory, the variable node output info memory, the original info memory, the convergence test unit, the iterative control unit, etc. According to the code verification matrix, the decoder splits the variable node and the verification node into blocks. All VANP and VeNP work simultaneously, interact info via memories and handle iterative decoding. Meanwhile, they optimize the original position of processing variable node blocks and verification node blocks, enlarge the proportion of using soft info in advance during the iterative decoding progress. This improves further the feature of the decoder. This synchronization parallel iterative decoder possesses feature of rapidly converging, good performance and durability and suits for various low density odd-even correcting code with sub-circular structure.

Description

Double-turbine structure low-density parity check code decoder

Technical Field

The invention provides a low-density parity check code decoder with a double-turbine structure, belonging to the technical field of decoding of channel error correction coding.

Background

Low Density Parity Check Codes (LDPC) are linear block Codes based on a sparse Check matrix, which have performance close to Shannon Limit (Shannon Limit) and Low Error Floor effect (Error Floor), and have been widely used in recent years. LDPC codes are generally described by bipartite graphs corresponding to check matrices thereof, and the bipartite graphs include check nodes and variable nodes respectively corresponding to rows and columns of the check matrices.

The matrix obtained by performing Gaussian elimination on the check matrix of the LDPC code is not sparse any more, so that the encoding complexity of the LDPC code is higher, and the hardware implementation is more difficult. In a practical system, in order to facilitate coding, a class of LDPC codes with a quasi-cyclic structure is generally used, and coding thereof can be implemented by a simple shift register, and complexity is low. The decoder in the invention is designed aiming at the LDPC code with the structure and is suitable for regular and irregular quasi-cyclic LDPC codes.

Decoding of the LDPC code generally employs a soft-decision iterative decoding algorithm based on a bipartite graph, such as a sum-product algorithm, a minimum sum algorithm, and various modifications of the minimum sum algorithm. In the iteration process, the information related to the check nodes and the variable nodes is alternately updated and is transmitted through the edges in the bipartite graph. The algorithm is easy to implement in parallel, but due to the limitation of hardware resources, a full parallel scheme is not feasible, and a partial parallel method is generally adopted for implementation. The performance of an LDPC code decoder depends on the one hand on the decoding algorithm employed and on the other hand on the number of iterations. For a certain decoding algorithm, the performance is better as the iteration number is larger, but the decoding delay is increased and the decoding rate is low as the iteration number is increased, namely, a contradiction exists between the rate and the performance of a decoder. Modern communication systems have increasingly stringent requirements with respect to transmission rate and transmission quality, which requires simultaneous improvements in the rate and performance of the decoder. The method is a reasonable method for fully and effectively utilizing the existing hardware resources to accelerate the convergence rate of iteration and improve the performance under the limited iteration times, and the dual-turbine structure decoder provided by the invention has the characteristic.

Disclosure of Invention

The technical problem is as follows: the invention aims to provide a double-turbine structure low-density parity check code decoder, which improves the decoding rate and performance of the low-density parity check code, and accelerates the iterative convergence speed by fully and effectively using hardware resources so as to obtain better performance. The method is suitable for various quasi-cyclic structured LDPC codes (regular and irregular) and has high working robustness.

The technical scheme is as follows: the low-density parity check code decoder with the double Turbo structure divides variable nodes and check nodes into blocks according to a code word check matrix, each variable node processing unit and each check node processing unit of the decoder work simultaneously, and information is interacted among the variable node processing units and the check node processing units through a memory to perform iterative decoding. Meanwhile, in order to further accelerate the convergence speed of iterative decoding, the initial positions of processing of each variable node block and check node block are optimized, and the performance of the decoder is improved.

The decoder includes:

check node processing unit array: the system comprises a plurality of check node processing units, a variable node processing unit and a data processing unit, wherein the check node processing units are used for calculating output information from corresponding check nodes to adjacent variable nodes;

variable node processing unit array: the device comprises a plurality of variable node processing units, a plurality of bit selection units and a plurality of bit selection units, wherein the variable node processing units are used for calculating output information from a corresponding variable node to a neighboring check node, simultaneously completing the calculation of the posterior probability of a code word bit corresponding to the variable node and giving the estimation of a corresponding bit value;

check node output information memory: the variable node is used for storing the information output by the check node to the variable node connected with the check node;

variable node output information memory: the variable node is used for storing the information output by the variable node to the check node connected with the variable node;

an initial information memory: the decoder is used for storing initial information of a current frame and a next frame input into the decoder;

a convergence testing unit: for checking whether a given sequence is a codeword;

an iteration control unit: control for iterative processes, including memory access, individual module work scheduling, and early termination of iterations;

the variable node information input end of the check node processing unit array is connected with the variable node output information memory, and the information is output to the check node output information memory after the processing is finished; according to the structure of a code word check matrix, partitioning according to columns, wherein each block corresponds to one unit in a variable node processing unit array, a check node information input end and an initial likelihood ratio information input end of the variable node processing unit array are respectively connected with a check node output information memory and an initial information memory, information is output to the variable node output information memory after processing is completed, and a code word sequence obtained in an iteration process is estimated and output to a convergence testing unit; the iteration control unit is respectively connected with the check node processing unit array, the variable node processing unit array and the convergence testing unit to control the whole iterative decoding process.

The decoding method of the low-density parity check code decoder with the double-turbine structure comprises the following steps: dividing the check nodes and the variable nodes into blocks according to the structure of the code word check matrix, wherein each block corresponds to one processing unit; in the iterative decoding process, the check node processing unit array and the variable node processing unit array work simultaneously, read information from the variable node output information memory and the check node output information memory respectively, calculate output information according to an information propagation rule, write the output information into the corresponding output information memories respectively, and complete the updating of the information; and when the check node processing unit array and the check node processing unit array work, the convergence testing unit checks the sequence obtained in the iteration, if the sequence is a code word, the iteration is terminated in advance, and if the sequence is not a code word, the next iteration is carried out until the maximum iteration number is reached.

The specific decoding method is as follows:

let the check matrix H of the low-density parity check code be a matrix of M rows and N columns, composed of a sub-matrix H of J X L blocks Z X Z_jlThe structure is that J is M/Z, L is N/Z; the decoder performs parallel decoding by using J check node processing units and L variable node processing units respectively using R_mn ^k，z、Q_nm ^k，z(0. ltoreq. Z < Z) denotes the Z-th beat check node c at the k-th iteration_mOutput to variable node v_nInformation, variable node v of_nOutput to check node c_mBy Q_n ^kRepresenting variable node v_nA posteriori probability information of, with y_nSum variable node v representing input decoder_nInitial likelihood ratio information of corresponding codeword bits, and using d_nIs represented according to Q_n ^kEstimating the current bit of the code word sequence obtained by hard decision; wherein R is_mn ^k，z、Q_nm ^k，zRespectively storing the information in a check node output information memory and a variable node output information memory; in the decoding process, each iteration of the initial position vector components of the blocks corresponding to the check node processing units and the variable node processing unitsIs other than S ═ S₀，S₁，…，S_J-2，S_J-1]、T＝[t₀，t₂，…，t_L-2，t_L-1 ]The decoder operates as follows:

1.) initializing;

initializing iteration times k: k is 0;

initializing a check node output information memory: for all m, n ∈ B (m), ${\mathrm{<figure-callout\; id="0"\; label="R\; mn"\; filenames="A20061009653500171.png,A20061009653500211.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{mn}}^{}=0;$

initializing a variable node output information memory: for all n, m ∈ A (n), ${\mathrm{<figure-callout\; id="0"\; label="Q\; nm"\; filenames="A20061009653500171.png,A20061009653500211.png"\; state="\{\{state\}\}">Q</figure-callout>}}_{\mathrm{nm}}^{}=y_n,$ wherein y is_nIs the initial likelihood ratio information of the input decoder;

2.) iterative decoding;

adding 1 to the number of iterations: k is k + 1;

for the Z (Z is more than or equal to 0 and less than or equal to Z-1) beat of the current iteration, the following processing is carried out:

the J check node processing units simultaneously read information from the variable node output information memory to calculate information output to corresponding variable nodes, specifically: for J (J is more than or equal to 0 and less than or equal to J-1) th check node processing unit, processing m ═ j.Z +(s) by the current beat_j+ z) mod Z check nodes, for all n ∈ B (m), according toThe minimum sum algorithm of the corrections is used,

<math> <mrow> <msubsup> <mi>R</mi> <mi>mn</mi> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> </mrow> </msubsup> <mo>=</mo> <mi>&beta;</mi> <mo>&CenterDot;</mo> <munder> <mi>&Pi;</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mo>&Element;</mo> <mi>B</mi> <mrow> <mo>(</mo> <mi>m</mi> <mo>)</mo> </mrow> <mo>\</mo> <mi>n</mi> </mrow> </munder> <mi>sgn</mi> <mrow> <mo>(</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>)</mo> </mrow> <mo>&CenterDot;</mo> <munder> <mi>min</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mo>&Element;</mo> <mi>B</mi> <mrow> <mo>(</mo> <mi>m</mi> <mo>)</mo> </mrow> <mo>\</mo> <mi>n</mi> </mrow> </munder> <mo>|</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>|</mo> </mrow> </math>

wherein the beta is a correction factor, and the correction factor is, <math> <mrow> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>=</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>-</mo> <mn>1</mn> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>;</mo> </mrow> </math>

the L variable node processing units simultaneously read information from the check node output information memoryCombining the initial likelihood ratio information input to the decoder, and calculating the information output to the corresponding check node, specifically: for the L (L is more than or equal to 0 and less than or equal to L-1) variable node processing unit, the current beat processes the n ═ l.Z + (t)₁+ z) mod Z variable nodes, calculating the posterior information of the node

<math> <mrow> <msubsup> <mi>Q</mi> <mi>n</mi> <mi>k</mi> </msubsup> <mo>=</mo> <msub> <mi>y</mi> <mi>n</mi> </msub> <mo>+</mo> <munder> <mi>&Sigma;</mi> <mrow> <mi>m</mi> <mo>&Element;</mo> <mi>A</mi> <mo>{</mo> <mi>n</mi> <mo>}</mo> </mrow> </munder> <msubsup> <mi>R</mi> <mi>mn</mi> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> </mrow> </math>

To Q_n ^kHard decision yields d_n(ii) a Then for all m e.g. A { n },

$Q_{\mathrm{nm}}^{k,z}=Q_n^k-R_{\mathrm{mn}}^{k,z-1}$

wherein $R_{\mathrm{mn}}^{k,-1}=R_{\mathrm{mn}}^{k-1,z-1};$

The processes of the first step and the second step are carried out simultaneously;

3.) the convergence test module obtains a sequence d for the iteration_nChecking, if all the check formulas are satisfied, ending decoding, and converting the sequence d_nOutputting as a final codeword; otherwise, turning to the step 2) to continue iteration until the maximum iteration number is reached or the result of a certain iteration meets all check equations.

In iterative decoding, some information read by each check node processing unit from the variable node output information memory or each variable node processing unit from the check node output information memory is updated by the current iteration, and some information is obtained by the last iteration, namely the information obtained by the current iteration is used in advance; the condition of information use in advance is related to the initial position of the corresponding block of each processing unit in the iterative process, and the initial position needs to be optimized; specifically, the initial position of each block is used as a variable to be optimized, the quantity of information obtained by using the iteration in one iteration is used as an objective function, and an optimal initial position vector can be obtained by adopting a differential evolution method.

Has the advantages that:

the beneficial effects of the invention are mainly embodied in the following aspects:

(1) in the decoder, the check node processing unit and the variable node processing unit work simultaneously, and both use soft information updated in advance, so that the information updating speed in the iteration process is accelerated.

(2) By optimizing the initial positions of each check node processing unit and each variable node processing unit, the proportion of the soft information used in advance is increased, and the performance is further improved.

(3) Compared with other decoders with similar hardware resources, the decoder has higher convergence speed and better performance.

Drawings

FIG. 1 is a schematic diagram of a LDPC code bipartite graph connection.

Fig. 2 is a schematic diagram of a check matrix of a quasi-cyclic LDPC code, where J is 4 and L is 24.

Fig. 3 is a block diagram of the overall structure of a decoder.

Fig. 4 is a schematic diagram of a decoder check node processing unit.

Fig. 5 is a schematic diagram of a decoder variable node processing unit.

Fig. 6 is a general flow chart of the operation of the decoder.

Fig. 7 is a schematic diagram of the operation of the decoder pipeline.

FIG. 8 shows a simulation curve of the performance of a code word with a length of 960/6 code rate in a WiMAX system.

The above figures include a check node processing unit array 1, a variable node processing unit array 2, a check node output information memory 3, a variable node output information memory 4, an initial information memory 5, a convergence testing unit 6 and an iteration control unit 7;

Detailed Description

Let the check matrix H of LDPC code be an M × N matrix composed of J × L blocks Z × Z sub-matrix H_jlThe structure is that J is M/Z, and L is N/Z. Each sub-matrix is a unit matrix or a cyclic shift matrix I of the unit matrix_p(each row of the unit matrix is circularly moved by p bits to the right), or all 0 matrix O. The set of bipartite graph variable node core check nodes corresponding to the check matrix H is respectively V ═ V_n，1 ≤n≤N}、C＝{c_mAnd M is more than or equal to 1 and less than or equal to M }. Definition of B (m) ═ n: H _mn1 is check node c_mCorresponding variable node set, A (n) { m }∶H _mn1 is variable node v_nCorresponding check node set, represented by B (m) \ n and check node c_mConsecutive division v_nCollection of extra variable nodes, denoted by A (n) \ m and variable node v_nConnected dust remover

c_mAnd (4) collecting the check nodes.

The whole decoder mainly comprises the following parts:

check node processing unit array: for calculating the output information of the corresponding check node to its neighboring variable nodes.

Variable node processing unit array: the method is used for calculating the output information from the corresponding variable node to the adjacent check node, and meanwhile, the calculation of the posterior probability of the code word bit corresponding to the variable node is completed, and the estimation of the value of the corresponding bit is given.

Check node output information memory: the variable node is used for storing the information output by the check node to the variable node connected with the check node.

Variable node output information memory: the variable node is used for storing the information output by the variable node to the check node connected with the variable node.

An initial information memory: for storing initial information of the current frame and the next frame input to the decoder.

A convergence testing unit: for checking whether a given sequence is a code word.

An iteration control unit: control for the iterative process, including memory access, individual module work scheduling, and early termination of the iteration.

The whole decoder uses J check node processing units and L variable node processing units to perform parallel decoding, and R is used for decoding_mn ^k，z、Q_nm ^k，z(0. ltoreq. Z < Z) denotes the Z-th beat check node c at the k-th iteration_mOutput to variable node v_nInformation, variable node v of_nOutput to check node c_mBy Q_n ^kRepresenting variable node v_nA posteriori probability information of, with y_nSum variable node v representing input decoder_nInitial likelihood ratio information of corresponding codeword bits, and using d_nIs represented according to Q_n ^kAnd estimating the current bit of the code word sequence obtained by hard decision. Wherein R is_mn ^k，z、Q_nm ^k，zAnd respectively storing the data in a check node output information memory and a variable node output information memory. In the decoding process, the initial position vectors of the blocks corresponding to each check node processing unit and each variable node processing unit in each iteration are respectively S ═ S [ -S [ ]₀，S₁，…，S_J-2，S_J-1]、T＝[t₀，t₂，…，t_L-2，t_L-1]。

The following describes in detail the steps of the decoder operation:

(1) initialization

Initializing iteration times: k is 0;

initializing a check node output information memory: for all m, n ∈ B (m), ${\mathrm{<figure-callout\; id="0"\; label="R\; mn"\; filenames="A20061009653500171.png,A20061009653500211.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{mn}}^{}=0;$

initializing a variable node output information memory: for all n, m ∈ A (n), ${\mathrm{<figure-callout\; id="0"\; label="Q\; nm"\; filenames="A20061009653500171.png,A20061009653500211.png"\; state="\{\{state\}\}">Q</figure-callout>}}_{\mathrm{nm}}^{}=y_n,$ wherein y is_nIs the initial likelihood ratio information of the input decoder.

(2) Iterative decoding

Adding 1 to the number of iterations: k is k + 1;

for the Z (Z is more than or equal to 0 and less than or equal to Z-1) beat of the current iteration, the following processing is carried out:

the J check node processing units simultaneously read information from the variable node output information memory to calculate information output to corresponding variable nodes, specifically:

for J (J is more than or equal to 0 and less than or equal to J-1) th check node processing unit, processing m ═ j.Z +(s) by the current beat_j+ z) modZ check nodes, for all n ∈ B (m), according to a modified minimum sum algorithm,

<math> <mrow> <msubsup> <mi>R</mi> <mi>mn</mi> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> </mrow> </msubsup> <mo>=</mo> <mi>&beta;</mi> <mo>&CenterDot;</mo> <munder> <mi>&Pi;</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mo>&Element;</mo> <mrow> <mo>(</mo> <mi>m</mi> <mo>)</mo> </mrow> <mo>\</mo> <mi>n</mi> </mrow> </munder> <mi>sgn</mi> <mrow> <mo>(</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>)</mo> </mrow> <mo>&CenterDot;</mo> <munder> <mi>min</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mo>&Element;</mo> <mi>B</mi> <mrow> <mo>(</mo> <mi>m</mi> <mo>)</mo> </mrow> <mo>\</mo> <mi>n</mi> </mrow> </munder> <mo>|</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>|</mo> </mrow> </math>

wherein the beta is a correction factor, and the correction factor is, <math> <mrow> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>=</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>-</mo> <mn>1</mn> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>.</mo> </mrow> </math>

l variable node processing units simultaneously read information from the check node output information memory, and calculate information output to corresponding check nodes by combining initial likelihood ratio information input into a decoder, specifically:

for the L (L is more than or equal to 0 and less than or equal to L-1) variable node processing unit, the current beat processes the n ═ l.Z + (t)₁+ z) mod Z variable nodes, calculating the posterior information of the node

<math> <mrow> <msubsup> <mi>Q</mi> <mi>n</mi> <mi>k</mi> </msubsup> <mo>=</mo> <msub> <mi>y</mi> <mi>n</mi> </msub> <mo>+</mo> <munder> <mi>&Sigma;</mi> <mrow> <mi>m</mi> <mo>&Element;</mo> <mi>A</mi> <mo>{</mo> <mi>n</mi> <mo>}</mo> </mrow> </munder> <msubsup> <mi>R</mi> <mi>mn</mi> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> </mrow> </math>

To Q_n ^kHard decision yields d_n(ii) a Then for all m e.g. A { n },

$Q_{\mathrm{nm}}^{k,z}=Q_n^k-R_{\mathrm{mn}}^{k,z-1}$

wherein <math> <mrow> <msubsup> <mi>R</mi> <mi>mn</mi> <mrow> <mi>k</mi> <mo>,</mo> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>=</mo> <msubsup> <mi>R</mi> <mi>mn</mi> <mrow> <mi>k</mi> <mo>-</mo> <mn>1</mn> <mo>,</mo> <mi>Z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>&CenterDot;</mo> </mrow> </math>

The above processes (i) and (ii) are performed simultaneously.

(3) The convergence test module performs a sequence d on the iteration_nChecking, if all the check formulas are satisfied, ending decoding, and converting the sequence d_nOutputting as a final codeword; otherwise, go to (2) to continue iteration until the maximum number of iterations is reached or the result of a certain iteration satisfies all the check equations.

The following takes LDPC codes adopted in WiMAX system with IEEE 802.16e as standard as an example, and the specific operation of the decoder proposed by the present invention is described with reference to the accompanying drawings.

The LDPC code adopted by the WiMAX system is an irregular quasi-cyclic code, and its check matrix has 24 sub-blocks in each row, and the number J of sub-blocks in each column is different according to the code rate. The system has four code rates of 1/2, 2/3, 3/4 and 5/6, and the number of corresponding column sub-blocks is respectively 12, 8, 6 and 4. At various code rates, the length N of the code word varies with the size Z of each sub-block, and is 19 from 576 to 2304. Fig. 2 shows a schematic diagram of a code word check matrix with a code rate of 5/6, and the following description is about a code word with a code rate of 5/6.

Fig. 3 shows a schematic structural diagram of the whole decoder, which includes a check node processing unit, a variable node processing unit, a check node output information memory, a variable node output information memory, an initial information memory, a convergence testing module, an iteration control unit, and the like. The structure and function of each part will be described in detail below.

Fig. 4 presents a schematic view of a check node processing unit. In fig. 4(a), the check node processing unit reads the information transmitted from the variable node connected to the variable node from the variable node output information memory, performs corresponding processing, and writes the processed information into the check node output information memory. The minimum sum algorithm of correction is adopted, the minimum value and the second minimum value are obtained by a segmented and layered comparison method, and then the minimum value and the second minimum value are multiplied by a correction factor and then written into a check node output information memory. The correction factor β can be obtained by a simulation method or a density evolution method. For the code word with 5/6 code rate, after simulation, the performance is better when beta is about 0.8, and for the convenience of hardware realization, beta is 0.8125, and the method can be realized by a shifting method. Fig. 4(b) shows a circuit diagram for finding the minimum value and the next-smallest value from the information input to the check node processing unit. The degree of each check node is 20, a minimum value and a secondary minimum value are obtained by adopting a hierarchical grouping comparison method, the first layer is divided into 5 groups, and each group obtains the minimum value and the secondary minimum value from 4 numerical values; the second layer compares 5 minimum values obtained by the comparison of the first layer with 5 secondary minimum values in groups, and the 5 minimum values are compared to obtain the minimum value of 20; and the third layer compares the secondary minimums obtained by comparing the 5 last minimums with the 5 last minimums, and the obtained minimums are output as the secondary minimums in 20 numbers. Fig. 4(c) shows a comparison and decoding circuit for obtaining the minimum value and the second minimum value from 4 numbers, and the case of 5 numbers is similar thereto. In fig. 4(c), 6 subtractors are used to compare 4 numbers two by two, and the result of comparison is decoded by a decoding circuit to obtain a minimum value and a second minimum value; the internal logic of the decoding circuit is also shown, where no 0 or 1 is labeled to indicate any value.

Fig. 7 shows a schematic diagram of a variable node processing unit. The variable node processing unit reads out the related information from the check node output information memory and the initial information memory, sums and subtracts the related information respectively and outputs the sum, and obtains the estimation of the current bit of the code word according to the symbol of the sum. Because the data in the memory is expressed according to the form of the original code and is not beneficial to addition and subtraction operation, the data is firstly converted into the complement code form for operation, and finally converted into the original code form and sent back to the memory. The degree of the variable node in the graph is 3, and the processing method of the nodes with other degrees is similar.

The structure of the memory in the decoder is explained below. In the entire decoder, the memories are divided into three categories: the system comprises an initial information memory, a check node output information memory and a variable node output information memory. In order to keep the decoder working continuously, two rams are used in the decoder to work in a ping-pong mode, one for a current frame and one for a next frame. The information stored in the check node output information memory and the variable node output information memory corresponds to the edges of the code word bipartite graph one by one, and in order to enable a plurality of check node operation units and variable node operation units to work simultaneously in parallel, the memories need to be partitioned, and dual-port Ram is adopted, so that a plurality of groups of data can be read and written simultaneously. Here the memory is partitioned according to non-all-zero sub-blocks in the check matrix, each block Ram stores Z data, and the check node output information memory and the variable node output information memory operate in a ping-pong manner, alternating between adjacent iterations. In the iterative decoding process, the check node processing unit reads information from the variable node output information memory, and writes back the originally read address after the processing is finished for the following iteration; the processing mode of the variable node processing unit is similar, information is read from the check node output information memory, and after the processing is finished, the originally read address is written back for the following iteration.

Convergence test unit verificationSequence d generated by a certain iteration_nWhether all the check formulas are met or not, and the test result is fed back to the iteration control unit. The convergence testing module is easy to realize, J multiple-input exclusive-OR gates are adopted for parallel testing, J rows of the check matrix correspond to each time, the output of the J multiple-input exclusive-OR gates is connected into one J input NOR gate and used for judging whether the corresponding J rows in the check matrix are met, and therefore Z beats can be completed. If the output of a certain beat NOR gate is 0, d is indicated_nNot satisfying the check matrix; if the outputs of the NOR gates in Z beats are all 1, d is illustrated_nAll rows that satisfy the check matrix are one codeword.

Fig. 6 shows a flow chart of the operation of the decoder, implemented by the iteration control unit. Under the control of the iteration control unit, the check node processing unit and the variable node processing unit respectively read data from the corresponding memories, and write back the data to the memories after the processing is finished, so that the iterative decoding is finished. At the same time, the convergence test unit pairs the sequence d obtained from the last iteration_nAnd checking to decide to stop decoding or continue iteration. In order to increase the decoding rate and the utilization efficiency of the device, each unit of the decoder adopts a pipeline working mode, as shown in fig. 7 in particular.

Because the check node processing unit and the variable node processing unit in the decoder work simultaneously, in the same iteration, some information input into a certain node processing unit is updated in the iteration, and some information is obtained in the last iteration, namely soft information is used in advance. This is an important feature of the decoder proposed by the present invention, and the convergence rate of the iteration is increased by the advanced use of the soft information, thereby improving the performance of the decoder.

In the decoder, each processing unit processes the Z rows or Z columns of the check matrix, and the starting positions of the processing units are different, so that the soft information is used in advance in different situations in the iterative process, and the final performances are different, which requires optimization of the starting positions. The optimization method has various methods, wherein a differential evolution method is adopted, the initial position of each block is used as a vector to be optimized, and an objective function is defined as the number of likelihood ratio information input into each node processing unit in one iteration and updated by the current iteration. For the code words with the length of 960 of the 5/6 code rate in the WiMAX system, the method is adopted to optimize and obtain the following initial position vectors:

checking the nodes: s-4, 23, 38, 16

Variable node: t [3, 30, 35, 37, 24, 7, 19, 1, 6, 37, 24, 30, 13, 32, 29, 22, 13, 4, 22, 8, 22, 22, 37]

Specific results are given in fig. 8, where (a) is the frame error rate curve, while the performance curve of the standard sum-product decoder is given. Because the time required for completing one iteration of the double-Turbo structure decoder provided by the patent is half of that of a standard and product algorithm decoder, the maximum iteration time of the standard and product algorithm decoder in the figure is set to be 20, and the maximum iteration time of the double-Turbo structure decoder is set to be 40. It can be seen that at the frame error rate of 1 × 10^-4The dual Turbo structure decoder has a performance gain of approximately 0.25dB compared to the standard sum-product decoder. The average iteration times under different signal-to-noise ratios are shown in the diagram (b), and for convenience of comparison, the iteration times of the standard and product algorithms are taken as a reference in the diagram, and the one-time iteration calculation of the double-Turbo structure decoder is 0.5 time, so that the average iteration times of the double-Turbo structure decoder is smaller than that of the standard and product algorithm decoder. In summary, the dual Turbo structure decoder is superior to the standard sum-product decoder in both performance and rate.

The decoder disclosed in this patent uses a minimum sum algorithm for multiplicative correction in check node processing, and it should be noted that this structure may also be used when check nodes use a sum-product algorithm, a minimum sum algorithm for offset, and so on. Meanwhile, the decoder can be used together with a channel estimator, an equalizer, a soft demodulator and the like at the front end of the system, all modules mutually transmit information, and the performance of the whole system is improved through iteration.

Claims (4)

1. A dual-turbo low-density parity-check code decoder, comprising:

check node processing unit array (1): the system comprises a plurality of check node processing units, a variable node processing unit and a data processing unit, wherein the check node processing units are used for calculating output information from corresponding check nodes to adjacent variable nodes;

variable node processing unit array (2): the device comprises a plurality of variable node processing units, a plurality of bit selection units and a plurality of bit selection units, wherein the variable node processing units are used for calculating output information from a corresponding variable node to a neighboring check node, simultaneously completing the calculation of the posterior probability of a code word bit corresponding to the variable node and giving the estimation of a corresponding bit value;

check node output information memory (3): the variable node is used for storing the information output by the check node to the variable node connected with the check node;

variable node output information memory (4): the variable node is used for storing the information output by the variable node to the check node connected with the variable node;

initial information memory (5): the decoder is used for storing initial information of a current frame and a next frame input into the decoder;

convergence test unit (6): for checking whether a given sequence is a codeword;

an iteration control unit (7): control for iterative processes, including memory access, individual module work scheduling, and early termination of iterations;

the variable node information input end (a) in the check node processing unit array (1) is connected with a variable node output information memory (4), and information output to the variable node is connected with a check node output information memory (3) through a port (d); according to the structure of a code word check matrix, blocks are divided into blocks according to columns, each block corresponds to one unit in a variable node processing unit array (2), a check node information input end (c) and an initial likelihood ratio information input end (d) of the variable node processing unit array (2) are respectively connected with a check node output information memory (3) and an initial information memory (5), information output to a check node is connected with a variable node output information memory (4) through a port (e) and is connected with a convergence test unit (6) through a port (f), and estimation of a code word sequence obtained in an iteration process is output; the iteration control unit (7) is respectively connected with the check node processing unit array (1), the variable node processing unit array (2) and the convergence testing unit (6).

2. A decoding method of the double-turbine-structured low density parity check code decoder according to claim 1, characterized in that: dividing the check nodes and the variable nodes into blocks according to the structure of the code word check matrix, wherein each block corresponds to one processing unit; in the iterative decoding process, the check node processing unit array (1) and the variable node processing unit array (2) work simultaneously, read information from the variable node output information memory (4) and the check node output information memory (3), calculate output information according to an information propagation rule, write the output information into the corresponding output information memories, and complete information updating; when the check node processing unit array (1) and the check node processing unit array (2) work, the convergence testing unit (6) checks the sequence obtained in the iteration, if the sequence is a code word, the iteration is terminated in advance, otherwise, the next iteration is carried out until the maximum iteration number is reached.

3. The decoding method of the dual turbo structure ldpc code according to claim 2, wherein the decoding method is as follows:

let the check matrix H of the low-density parity check code be a matrix of M rows and N columns, composed of J × L blocksZ× ZSub-matrix H of_jlThe structure of the utility model is that the material,J＝ M/ Z， L＝ N/ Z(ii) a Decoder useJThe check node processing unit and the L variable node processing units perform parallel decoding respectivelyR _mn ^k，z、 Q _nm ^k，z(0≤ z＜ Z) Is shown inkThe first of the sub-iterationszBeat check nodec _mOutput to variable node v_nInformation, variable node v of_nOutput to check nodec _mInformation of (1) usingQ _n ^kRepresenting variable node v_nA posteriori probability information of, with y_nSum variable node v representing input decoder_nCorresponding codeword bit initial likelihood ratio information, and using d_nExpress according toQ _n ^kObtained by hard decisionEstimation of the current bit of the codeword sequence; wherein,R _mn ^k，z、 Q _nm ^k，zrespectively storing the information in a check node output information memory and a variable node output information memory; in the decoding process, the initial position vectors of the blocks corresponding to each check node processing unit and each variable node processing unit in each iteration are respectivelyS＝[ s ₀， s ₁，…， s _J-2 ， s _J-1 ]、 T＝[ t ₀， t ₂，…， t _L-2 ， t _L-1 ]The decoder operates as follows:

1.) initializing;

number of iterationskInitialization:k＝0；

initializing a check node output information memory: for allm， n∈ B( m)，

Initializing a variable node output information memory: for alln， m∈ A( n)，

Wherein y is_nIs the initial likelihood ratio information of the input decoder;

2.) iterative decoding;

adding 1 to the number of iterations:k＝ k+1；

to the first of the current iterationz(0≤ z≤ Z-1) beats, as followsProcessing:

① Jthe check node processing units simultaneously read information from the variable node output information memory to calculate information output to the corresponding variable nodes, specifically: to the firstj(0≤ j≤ J-1) check node processing units, the current beat processing mth ═ mj· Z+(s_j+ z)mod ZA check node for alln∈ B( m) The minimum sum of the values of the first and second parameters is calculated, according to a modified minimum sum algorithm, <math> <mrow> <msubsup> <mi>R</mi> <mi>mn</mi> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> </mrow> </msubsup> <mo>=</mo> <mi>&beta;</mi> <mo>&CenterDot;</mo> <munder> <mi>&Pi;</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mo>&Element;</mo> <mi>B</mi> <mrow> <mo>(</mo> <mi>m</mi> <mo>)</mo> </mrow> <mo>\</mo> <mi>n</mi> </mrow> </munder> <mi>sgn</mi> <mrow> <mo>(</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>)</mo> </mrow> <mo>&CenterDot;</mo> <munder> <mi>min</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mo>&Element;</mo> <mi>B</mi> <mrow> <mo>(</mo> <mi>m</mi> <mo>)</mo> </mrow> <mo>\</mo> <mi>n</mi> </mrow> </munder> <mo>|</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>|</mo> </mrow> </math>

whereinβIn order to correct the factor(s), <math> <mrow> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>,</mo> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>=</mo> <msubsup> <mi>Q</mi> <mrow> <mi>n</mi> <mo>&prime;</mo> <mi>m</mi> </mrow> <mrow> <mi>k</mi> <mo>-</mo> <mn>1</mn> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo>;</mo> </mrow> </math>

② Lthe variable node processing unit reads information from the check node output information memory at the same time, and calculates information output to the corresponding check node by combining the initial likelihood ratio information input to the decoder, specifically: to the firstl(0≤ l≤ L-1) variable node processing units, the current beat processing the firstn＝ l· Z+(t_l+ z)mod ZA variable node, calculating the posterior information of the node

<math> <mrow> <msubsup> <mi>Q</mi> <mi>n</mi> <mi>k</mi> </msubsup> <mo>=</mo> <msub> <mi>y</mi> <mi>n</mi> </msub> <mo>+</mo> <munder> <mi>&Sigma;</mi> <mrow> <mi>m</mi> <mo>&Element;</mo> <mi>A</mi> <mo>{</mo> <mi>n</mi> <mo>}</mo> </mrow> </munder> <msubsup> <mi>R</mi> <mi>mn</mi> <mrow> <mi>k</mi> <mo>,</mo> <mi>z</mi> <mo>-</mo> <mn>1</mn> </mrow> </msubsup> <mo></mo> </mrow> </math>

To Q_n ^kHard decision yields d_n(ii) a Then to allm∈ A{ n}，

$Q_{\mathrm{nm}}^{k,z}=Q_n^k-R_{\mathrm{mn}}^{k,z-1}$

Wherein $R_{\mathrm{mn}}^{k,-1}=R_{\mathrm{mn}}^{k-1,z-1};$

The processes of the first step and the second step are carried out simultaneously;

3.) the convergence test module obtains a sequence d for the iteration_nChecking, if all the check formulas are satisfied, ending decoding, and converting the sequence d_nOutputting as a final codeword; otherwise, turning to the step 2) to continue iteration until the maximum iteration number is reached or the result of a certain iteration meets all check equations.

4. The decoding method of the dual turbine structure low density parity check code according to claim 2 or 3, wherein:

in iterative decoding, some information read by each check node processing unit from the variable node output information memory or each variable node processing unit from the check node output information memory is updated by the current iteration, and some information is obtained by the last iteration, namely the information obtained by the current iteration is used in advance; the condition of information use in advance is related to the initial position of the corresponding block of each processing unit in the iterative process, and the initial position needs to be optimized; specifically, the initial position of each block is used as a variable to be optimized, the quantity of information obtained by using the iteration in one iteration is used as an objective function, and an optimal initial position vector can be obtained by adopting a differential evolution method.

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