CN103618556A - Partially parallel quasi-cyclic low-density parity-check (QC-LDPC) decoding method based on row message passing (RMP) scheduling - Google Patents
Partially parallel quasi-cyclic low-density parity-check (QC-LDPC) decoding method based on row message passing (RMP) scheduling Download PDFInfo
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Abstract
The invention relates to a partially parallel quasi-cyclic low-density parity-check (QC-LDPC) decoding method based on row message passing (RMP) scheduling and belongs to the technical field of communication. According to the method, a partially parallel decoding structure is formed in a QC-LDPC decoder adopting a min-sum decoding algorithm based on the RMP scheduling; in the process of iterative decoding each time, iterative delayed time is nearly halved compared with that of the min-sum decoding algorithm; according to the quasi-cyclic characteristic of a QC-LDPC check matrix, the partially parallel processing decoding structure is adopted, the check matrix is partitioned, the parallel iterative decoding is carried out in partitions, the decoding delay is in linear inverse proportion to the degree of parallelism of decoding in each partition, the throughput of the decoder is improved exponentially, and a parallel mode and a serial RMP mode have the same performance, so that the LDPC decoder meets requirements on high-speed data processing.
Description
Technical field
The present invention relates to a kind of part parallel QC-LDPC interpretation method of transmitting (RMP) scheduling based on row message, belong to communication technical field.
Background technology
Low density parity check code (LDPC) is a kind of coding that approaches shannon limit, and its decoding complexity is low, flexible structure, is widely used in Modern Communication System, by a plurality of Communication and Broadcast standards, is adopted.As digital satellite television (DVB-S2), WLAN (wireless local area network) (WLAN) and China Digital TV terrestrial broadcasting transmission standard (DTMB) etc.Along with the development of wireless communication technology, cordless communication network need possess data, services ability and the comprehensive real-time multimedia traffic of higher rate, and the fast decoding of chnnel coding becomes active demand.
The many minimum-sum algorithms (Min-Sum Algorithm) based on standard message transmission (SMP) of ldpc decoder design realization, this algorithm is the approximate shortcut calculation of a kind of log-likelihood ratio (Log-LLR) belief propagation algorithm, although can lose on decoding performance, but hardware implementation complexity is very low, in decode procedure, only there is numeric ratio and plus and minus calculation, be suitable for Project Realization.
Its decoder mainly comprises following functions module: the soft information memory cell RAM_Q of variable node, with variable node i corresponding stored; The soft information memory cell RAM_R of check-node, with check-node j corresponding stored; Receive information memory cell RAM_Y, with variable node i corresponding stored; Check-node updating block CNU, j is corresponding with check-node, completes the computing that check-node upgrades, and result is returned to control unit; Variable node updating block VNU, j is corresponding with variable node, completes the computing that variable node upgrades, and result is returned to control unit; Control unit, for generation of the read/write address of various control signals control decoders, coordinates the work of unit.
In decode procedure, first the soft information that decoder receives be stored into and receive in information memory cell RAM_Y, starts subsequently initialized process: by the soft information receiving in information memory cell RAM_Y, the soft information memory cell RAM_Q of variable node is upgraded; Then, carry out check-node renewal: the reading address that the data in the soft information memory cell RAM_Q of variable node are produced according to control unit reads in check-node updating block CNU, complete computing, the memory address providing according to control unit is stored into operation result in the soft information memory cell RAM_R of check-node; Then, carry out variable node renewal: the reading address that the data in the soft information memory cell RAM_R of check-node are produced according to control unit reads in variable node updating block VNU, complete computing, detect and whether reach maximum iteration time, if it is adjudicate and result is exported, otherwise the memory address providing according to control unit is stored into operation result in the soft information memory cell RAM_Q of variable node, and proceeds check-node and upgrade until reach maximum iteration time.
Radosavljevic (" Optimized message passing schedules for LDPC decoding " in 2005, Signals, Systems and Computers, 2005:591-595) a kind of decoding algorithm that transmits (RMP) based on row message proposed.
The decoder of above-mentioned decode procedure mainly comprises following functions module: the soft information memory cell RAM_N of variable node, with variable node n corresponding stored; The soft information memory cell RAM_M of check-node, with check-node m corresponding stored; Iterative decoding updating block ICU, completes the computing of iterative decoding, and result is returned to control unit; Control unit, for generation of the read/write address of various control signals control decoders, coordinates the work of unit.
In decode procedure, the soft information that decoder receives starts initialized process: the soft information receiving is stored in the soft information memory cell RAM_N of variable node, the soft information memory cell RAM_M of check-node is carried out to initialization zero setting simultaneously; Then, carry out iteration renewal: the reading address that the data in the soft information memory cell RAM_N of variable node and the soft information memory cell RAM_M of check-node are produced according to control unit reads in iterative decoding updating block ICU, complete computing, the memory address providing according to control unit is stored into operation result in the soft information memory cell RAM_N of check-node and the soft information memory cell RAM_M of check-node; Then, detect decoding iteration and whether reach maximum iteration time, if it is adjudicate and by result output, otherwise proceed check-node, upgrade until reach maximum iteration time.
But all there are some problems in the decoder of two kinds of above-mentioned algorithm design:
1. the result after the last iteration that the each more new capital of the minimum-sum algorithm based on SMP is use, the result of each node updates cannot pass to other nodes at once, need to wait until next iteration, causes convergence of algorithm speed slow.And each iteration need to be carried out respectively check-node renewal and variable node upgrades, the each iteration of decoder all will be carried out twi-read and write operation to memory.These have caused the larger decoding delay of decoding needs.
2. although the Min-Sum decoding algorithm based on RMP can solve the problem of some minimum-sum algorithms based on SMP, but, from above to finding out the introduction of the Min-Sum decoding algorithm based on RMP, when this Min-Sum decoding algorithm based on RMP upgrades, the guild of rear renewal uses the data of upgrading in the row first upgrading, so can only carry out the renewal of serial, cannot adopt parallel decoding mode to improve decoding delay.
Summary of the invention
The object of the invention is in order to have reduced the decoding delay of QC-LDPC code decoder and to have adopted QC-LDPC code as the communication delay of the communication system of chnnel coding, a kind of part parallel LDPC interpretation method based on RMP scheduling is proposed, for QC-LDPC code, the decoding of the ldpc decoder based on RMP scheduling is processed to structure and be optimized.
The present invention realizes the decoding architecture of part parallel in the QC-LDPC decoder that adopts the Min-Sum decoding algorithm based on RMP scheduling, is specifically achieved through the following technical solutions:
(1) find the minimal circulation submatrix of QC-LDPC code check matrix, and obtain its size for I * I, I is constant;
(2), under the prerequisite that is 1 at the column weight that guarantees each subregion, with subregion of every J behavior, check matrix is divided into K subregion, I=nJ wherein, M=KJ, n is integer, generally n=1, i.e. I=J;
(3) determine that in subregion, number P is processed in multidiameter delay decoding, have Pl=J, l is the line number that in each subregion, each road decoding is processed.
The soft information memory cell RAM_ of variable node λ, for the initialization information of iterative decoding process and the soft information of variable node are stored, wherein comprises P block RAM memory block M λ p; P block RAM memory block M λ p, has stored the soft information of the corresponding variable node of nonzero element in the row that the p road decoding iteration in each subregion comprises;
The soft information memory cell RAM_ of check-node Λ, stores for the soft information of check-node that iterative decoding process is upgraded, and wherein comprises P block RAM memory block M Λ
p; P block RAM memory block M Λ wherein
p, stored the soft information of the corresponding check-node of nonzero element in the row that the p road decoding iteration in each subregion comprises;
Storage address generation module ADU, for generation of the soft information memory cell of variable node used in QC-LDPC decoder and the soft information memory cell of check-node; By RAM_ λ storage address generation submodule and RAM_ Λ storage address, produce submodule and form, each submodule is comprised of P initial address memory and P address offset calculator; Each submodule has P integrated signal output port, its output by initial address memory from P initial address memory sum counter; ADU has 2P output port, is connected respectively with RAM_ λ module with the read/write address port of P reading-writing port of RAM_ Λ module.
Iteration decoding module IDU, for the soft information of the check-node of iterative process and the soft information of variable node are walked abreast and upgrades computing, wherein comprises P CNU computing module;
Decoding judging module DJU, carries out decision process for the soft information memory cell of variable node being about to the information of output;
Soft information exchange module INU, for will delivering to corresponding CNU computing module from the data of the different RAM memory blocks of RAM_ λ module when the iterative decoding, and will be accordingly more new data return to RAM memory block; INU has 2P input port and 2P output port, wherein P input port and output port are connected with output port and the input port of RAM in RAM_ λ module, and P input port and output port are connected with output port and the input port of RAM in P CNU computing module; By INU module synthesis signal, P the soft information distribution of output in RAM_ λ module, in P CNU module, and stored into the soft information of the output of P CNU module in RAM_ λ module in the RAM of correspondence.
Decoding process control module PCU, for generation of the control signal of whole decoding flow process, comprising INU module synthesis signal.
Described every block RAM memory block M λ p and M Λ
pcontain two reading-writing port, its read-write mode is all " write-after-reads ", and each reading-writing port is all connected with p piece CNU computing module, and each is responsible for the read-write of a circuit-switched data each port;
Step 4.a) p CNU computing module in iteration decoding module IDU carries out iterative decoding calculating to the p road parallel information in k subregion, the information of module input is from variable node soft information memory cell RAM_ λ and the soft information memory cell RAM_ of check-node Λ, and the result of iterative decoding is saved on these two corresponding positions of memory cell;
Wherein, when upgrading the capable information of this road i, the RAM memory block of the variable node soft information memory cell RAM_ λ corresponding with p CNU computing module, be that read the address that p RAM canned data wherein provides according to storage address generation module ADU, the address that RAM_ λ obtains can be according to calculating as follows: k subregion p road decoding initialization address addr_kp0>+<i-1> of <;
When upgrading the capable information of this road i, the RAM memory block of the check-node soft information memory cell RAM_ Λ corresponding with p CNU computing module is that read the address that p RAM canned data wherein provides according to storage address generation module ADU, the address that RAM_ Λ obtains is according to a of memory block order continuous address, and a is that the row of QC-LDPC code is heavy;
Step 4.b) result that CNU computing module calculates is saved in respectively in variable node soft information memory cell RAM_ λ and memory block corresponding to the soft information memory cell RAM_ of check-node Λ by soft information exchange module INU, and the address writing is that the delay of carrying out a clock by corresponding reading address obtains;
Step 4.c) repeating step 4.a)-step 4.b), until complete the renewal of all row in each subregion;
Step 4.d), repeating step 4.a)～step 4.c), until complete the renewal of all subregions in whole check matrix;
Step 5, repeating step four, until reach maximum iteration time, and the data in each memory block in the soft information memory cell RAM_ of variable node λ are adjudicated according to calling over of storage, obtain decode results.
Beneficial effect
Compare with traditional decoder, the decoder of the present invention design has adopted the decoding algorithm based on RMP, in the process of each iterative decoding, compared with Min-Sum decoding algorithm, has reduced nearly half iteration time delay; In addition, the standard circulation feature having for QC-LDPC check matrix, the decoding architecture that has adopted part parallel to process, check matrix is carried out to subregion, in subregion, carry out Parallel Iteration Decoding Method, in decoding delay and each subregion, decoding degree of parallelism is linear inverse relation, thereby has improved exponentially the throughput of decoder, and guaranteed that this parallel mode has identical performance with the RMP mode of serial, made ldpc decoder adapt to the requirement that high-speed data is processed.Apply design of encoder of the present invention, can make ldpc decoder adapt to the communication applications of more high-throughputs.
Accompanying drawing explanation
Fig. 1 is LDP{Calderbank of the present invention, 1999#38}C interpretation method flow chart;
Fig. 2 is the structural representation of the ldpc decoder that adopts in embodiment;
Fig. 3 is the storage address control module key diagram of ldpc decoder in embodiment;
Fig. 4 is the address distribution method key diagram in embodiment.
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described in detail.
With reference to Fig. 2 part parallel QC-LDPC decoder based on RMP provided by the invention, be mainly divided into 6 parts, be respectively the soft information memory cell RAM_ of variable node λ, the soft information memory cell RAM_ of check-node Λ, iteration decoding module IDU, decoding judging module DJU, decoding process control module PCU.Wherein, the soft information memory cell RAM_ of variable node λ, for the initialization information of iterative decoding process and the soft information of variable node are stored, wherein comprises P block RAM memory block M λ p; The soft information memory cell RAM_ of check-node Λ, stores for the soft information of check-node that iterative decoding process is upgraded, and wherein comprises P block RAM memory block M Λ
p; Storage address generation module ADU, for generation of the soft information memory cell of variable node used in QC-LDPC decoder and the soft information memory cell of check-node; Iteration decoding module IDU, for the soft information of the check-node of iterative process and the soft information of variable node are walked abreast and upgrades computing, wherein comprises P CNU computing module; Decoding judging module DJU, carries out decision process for the soft information memory cell of variable node being about to the information of output; Decoding process control module PCU, for generation of the control signal of whole decoding flow process.Wherein, p block RAM memory block in RAM_ λ and RAM_ Λ module, has stored the corresponding variable joint of nonzero element and the soft information of check-node in the row that the p road decoding iteration in each subregion comprises; Every block RAM memory block contains two reading-writing port, and its read-write mode is all " write-after-reads ", and each reading-writing port is all connected with p piece CNU computing module, and each is responsible for the read-write of a circuit-switched data each port; Storage address generation module ADU, produces submodule by RAM_ λ storage address generation submodule and RAM_ Λ storage address and forms, and each submodule is comprised of P initial address memory and P address offset calculator; Storage address generation module ADU, has 2P output port, is connected respectively with RAM_ λ module with the read/write address port of P reading-writing port of RAM_ Λ module.
Annexation between the modules of decoder is as follows:
Each block RAM in RAM_ λ module all contains two reading-writing port, be responsible for respectively reading and writing of the soft information of iterative decoding, its pattern is all " first read afterwards and write " pattern, " reading " port of p block RAM is connected with p input port, the decoding judging module DJU input port of INU module simultaneously, and " writing " port of p block RAM is connected with p input port of INU module, the input port of decoder simultaneously; Each block RAM in RAM_ Λ module all contains two reading-writing port, be responsible for respectively reading and writing of the soft information of iterative decoding, its pattern is all " first read afterwards and write " pattern, and two ports of p block RAM are connected with the input/output port of p iterative decoding computing unit CNU_p simultaneously; A wherein P output port of INU module is connected with output port with the input port of P iterative decoding computing unit CNU respectively with input port, and P output port and input port are connected with output port with the input port of P block RAM in RAM_ λ module respectively in addition; The 2p of an ADU module output port is connected with p RAM read/write address port in RAM_ λ module and RAM_ Λ module respectively, is responsible for the control of read/write address.
With reference to Fig. 1, the method for iterative decoding provided by the invention, its step is as follows:
Each computing unit CNU_p in iteration decoding module IDU upgrades the information in the p block RAM of the RAM_ λ that is attached thereto and RAM_ Λ module one by one with the order of row, P computing unit carries out parallel decoding to the P road in subregion of check matrix simultaneously;
Each computing module CNU_p in described iteration decoding module IDU is divided into three steps: CNU_p to the renewal of the information in each RAM and from the p block RAM of RAM_ λ and RAM_ Λ module, reads first respectively the needed soft information of upgrading; CNU_p carries out iterative decoding according to the soft information reading again and upgrades calculating; The external information finally renewal being calculated writes back in the p block RAM of RAM_ λ and RAM_ Λ module;
Described iteration decoding module IDU carries out information updating to every block RAM of RAM_ λ and RAM_ Λ module, need to the soft information in every block RAM be read and be write, wherein the reading and writing data of every block RAM adopts a kind of address read-write management method of circulation, with reference to Fig. 4, its address distribution method is as follows:
A) the soft information storage module RAM_ of check-node Λ is saved in the soft information of the verification of p road parallel processing in p block RAM _ p according to the row order of each subregion, 1≤p≤P(P is parallel processing way, P=4 in figure), the address bit of each RAM be 0～(aJ-1);
B) each subunit matrix is sequentially divided into P part according to row, p the soft information of variable node corresponding to part of each submatrix is saved in the p block RAM _ p of RAM_ λ module, 1≤p≤P(P is parallel processing way, P=4 in figure), the address bit of every block RAM is 0～J-1;
C) under above-mentioned prerequisite, ADU module is carried out calculations of offset by the initial address of each submatrix, obtain the soft information of check-node corresponding to the soft information of variable node that in the soft information storage module of variable node, each block RAM is stored, and result is delivered in INU module, the soft information of the variable node obtaining from P block RAM is delivered to corresponding computing module CNU and carried out iterative decoding renewal.
For example, an if circular matrix being obtained by the circulation of 64 * 64 unit matrix, its first address is 23, carry out 4 road parallel decodings, 8 soft information of check-node of each RAM storage in RAM_ Λ module, address is 0～15, similarly, 8 soft information of check-node of each RAM storage in RAM_ λ module, address is 0～15; Soft message address and the relation between computing module of in every block RAM, storing are as shown in the table:
Step 5, repeating step 2, to step 4, until iterations iter_time reaches maximum iter_MAX, and is adjudicated the data in each memory block in the soft information memory cell RAM_ of variable node λ according to calling over of storage, obtain decode results.
Compare with adopting the ldpc decoder of SMP Min-Sum decoding algorithm, iterations with and line number identical in the situation that, decoder of the present invention can reduce closely half decoding delay; Compare with adopting the ldpc decoder of RMP, under the identical condition of iterations, decoder of the present invention can will reduce the decoding delay of half in the situation that not affecting decoding performance.
The above is preferred embodiment of the present invention, and the present invention should not be confined to the disclosed content of this embodiment and accompanying drawing.Everyly do not depart from the equivalence completing under spirit disclosed in this invention or revise, all falling into the scope of protection of the invention.
Claims (1)
1. the part parallel QC-LDPC interpretation method of dispatching based on RMP, is characterized in that: specifically comprise the following steps:
Step 1, is heavily a to row, and the check matrix H (M, N) of the QC-LDPC code that column weight is b is carried out subregion, and concrete grammar is:
(1) find the minimal circulation submatrix of QC-LDPC code check matrix, and obtain its size for I * I, I is constant;
(2), under the prerequisite that is 1 at the column weight that guarantees each subregion, with subregion of every J behavior, check matrix is divided into K subregion, I=nJ wherein, M=KJ, n is integer, generally n=1, i.e. I=J;
(3) determine that in subregion, number P is processed in multidiameter delay decoding, have Pl=J, l is the line number that in each subregion, each road decoding is processed;
Step 2, on the basis of subregion, sets up the QC-LDPC code decoder based on RMP scheduling, and its composition comprises:
The soft information memory cell RAM_ of variable node λ, for the initialization information of iterative decoding process and the soft information of variable node are stored, wherein comprises P block RAM memory block M λ p; P block RAM memory block M λ p, has stored the soft information of the corresponding variable node of nonzero element in the row that the p road decoding iteration in each subregion comprises;
The soft information memory cell RAM_ of check-node Λ, stores for the soft information of check-node that iterative decoding process is upgraded, and wherein comprises P block RAM memory block M Λ
p; P block RAM memory block M Λ wherein
p, stored the soft information of the corresponding check-node of nonzero element in the row that the p road decoding iteration in each subregion comprises;
Storage address generation module ADU, for generation of the soft information memory cell of variable node used in QC-LDPC decoder and the soft information memory cell of check-node; By RAM_ λ storage address generation submodule and RAM_ Λ storage address, produce submodule and form, each submodule is comprised of P initial address memory and P address offset calculator; Each submodule has P integrated signal output port, its output by initial address memory from P initial address memory sum counter; ADU has 2P output port, is connected respectively with RAM_ λ module with the read/write address port of P reading-writing port of RAM_ Λ module;
Iteration decoding module IDU, for the soft information of the check-node of iterative process and the soft information of variable node are walked abreast and upgrades computing, wherein comprises P CNU computing module;
Decoding judging module DJU, carries out decision process for the soft information memory cell of variable node being about to the information of output;
Soft information exchange module INU, for will delivering to corresponding CNU computing module from the data of the different RAM memory blocks of RAM_ λ module when the iterative decoding, and will be accordingly more new data return to RAM memory block; INU has 2P input port and 2P output port, wherein P input port and output port are connected with output port and the input port of RAM in RAM_ λ module, and P input port and output port are connected with output port and the input port of RAM in P CNU computing module; By INU module synthesis signal, P the soft information distribution of output in RAM_ λ module, in P CNU module, and stored into the soft information of the output of P CNU module in RAM_ λ module in the RAM of correspondence;
Decoding process control module PCU, for generation of the control signal of whole decoding flow process, comprising INU module synthesis signal;
Described every block RAM memory block M λ p and M Λ
pcontain two reading-writing port, its read-write mode is all " write-after-reads ", and each reading-writing port is all connected with p piece CNU computing module, and each is responsible for the read-write of a circuit-switched data each port;
Step 3, the iterative decoder of the QC-LDPC code decoder based on RMP scheduling that step 2 is set up carries out initialization: by the soft information of a frame channel likelihood ratio receiving, according to the subregion in check matrix, channel information is stored in the P block RAM memory block M λ p of the soft information memory cell RAM_ of variable node λ, the data of p piece memory block M λ p are carried out corresponding with address according to the row at the nonzero element place in row corresponding to the p road in subregion, the memory address scope of each memory block is 0～aJ-1, a is that the row of QC-LDPC code is heavy, J is each line number corresponding to subregion p road, meanwhile, the data of storing in the soft information memory cell RAM_ of check-node Λ are all initialized as to 0, and iterations iter_time is initialized as 0 time,
Step 4, carries out iterative decoding computing: iteration decoding module IDU and soft information storage module described in decoding process control module PCU and storage address generation module ADU co-controlling carry out computing renewal;
Step 4.a) p CNU computing module in iteration decoding module IDU carries out iterative decoding calculating to the p road parallel information in k subregion, the information of module input is from variable node soft information memory cell RAM_ λ and the soft information memory cell RAM_ of check-node Λ, and the result of iterative decoding is saved on these two corresponding positions of memory cell;
Wherein, when upgrading the capable information of this road i, the RAM memory block of the variable node soft information memory cell RAM_ λ corresponding with p CNU computing module, be that read the address that p RAM canned data wherein provides according to storage address generation module ADU, the address that RAM_ λ obtains can be according to calculating as follows: k subregion p road decoding initialization address addr_kp0>+<i-1> of <;
When upgrading the capable information of this road i, the RAM memory block of the check-node soft information memory cell RAM_ Λ corresponding with p CNU computing module is that read the address that p RAM canned data wherein provides according to storage address generation module ADU, the address that RAM_ Λ obtains is according to a of memory block order continuous address, and a is that the row of QC-LDPC code is heavy;
Step 4.b) result that CNU computing module calculates is saved in respectively in variable node soft information memory cell RAM_ λ and memory block corresponding to the soft information memory cell RAM_ of check-node Λ by soft information exchange module INU, and the address writing is that the delay of carrying out a clock by corresponding reading address obtains;
Step 4.c) repeating step 4.a)-step 4.b), until complete the renewal of all row in each subregion;
Step 4.d), repeating step 4.a)～step 4.c), until complete the renewal of all subregions in whole check matrix;
Step 5, repeating step four, until reach maximum iteration time, and the data in each memory block in the soft information memory cell RAM_ of variable node λ are adjudicated according to calling over of storage, obtain decode results.
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