CN117375636B - Method, device and equipment for improving throughput rate of QC-LDPC decoder - Google Patents
Method, device and equipment for improving throughput rate of QC-LDPC decoder Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
Abstract
The invention relates to a method, a device and equipment for improving throughput rate of QC-LDPC decoder, belonging to the technical field of communication, comprising the following steps: initializing variable node and check node information; reading a non-zero element column index number, and reading check node information and variable node information of a position corresponding to the column index number; calculating and storing updated variable nodes, and reading the cyclic shift submatrix value and the number of each non-zero element; calculating and updating check nodes and variable nodes and storing; and verifying or judging the calculated variable node information according to the verification rule of the decoding result of the LDPC code, and ending decoding if the verification or judgment requirement is met. The invention adopts the mode of storing the non-zero element values of the cyclic shift submatrices of the check matrix, the corresponding column index numbers and the number of the non-zero elements in each row of the check matrix, reduces the processing clock consumed by each decoding iterative operation, improves the throughput rate of the decoder and reduces the consumption of storage resources.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, and a device for improving throughput of a QC-LDPC decoder.
Background
The check matrix of the QC-LDPC code can be identified by a plurality of cyclic shift sub-matrices and the sub-matrix size, for example, the LDPC code in the 5G standard, the sub-matrix size being 384 at maximum; the general decoding process is as follows: step 1, initializing check nodes and variable nodes; step 2, updating variable nodes according to the received signals, the experience matrix and the check nodes; step 3, calculating an updated check node according to the variable nodes and the check matrix, and calculating the updated variable nodes until all check nodes are calculated; and step 4, repeating the steps 2 to 3 until the decoding verification is correct or the maximum iteration number operation is completed. According to the LDPC decoding algorithm, step 3 in the decoding process needs to calculate check nodes by using variable node information corresponding to non-zero element positions in the check matrix, so that the check matrix needs to be stored; reading check matrix values row by row during decoding, and calculating check nodes when the values are non-zero; therefore, an iterative operation in the decoding process is completed, and the complete check matrix must be traversed row by row; therefore, the size of the check matrix used by the LDPC code block determines the throughput and the memory size of the decoding operation process.
Usually, the LDPC check matrix is larger, for example, in the 5G standard, the maximum check matrix of the LDPC is 46×68 submatrices, and each submatrix has a maximum size of 384; when the LDPC decoding process is realized by adopting the FPGA, if the check matrix is stored and decoded according to a conventional method, a large number of FPGA clocks (1 FPGA clock is needed for each element in each check matrix) are consumed for finishing one iteration operation, and the decoding throughput rate is difficult to improve.
The prior patent CN113612575A discloses a QC-LDPC decoding method and system oriented to Wimax protocol, the method adopts a general LDPC decoding method, variable node variables, check node information and check matrix information are stored, and the decoding operation process is completed under the control of a decoder. However, the technical scheme is not mentioned in its entirety about the process of storing the check matrix and check node information. Patent CN103684474a discloses a method for implementing a high-speed LDPC decoder, where the method performs simultaneous operation by selecting check node information and variable node information that can be processed simultaneously, thereby improving throughput rate; however, the QC-LPDC code itself has the feature that the size of each sub-matrix divided into a plurality of cyclic shift sub-matrices is the number of check nodes and variable nodes that can be processed simultaneously, so that the method can not improve the decoding throughput rate any more in response to the QC-LDPC code. Patent CN111211790a discloses a high throughput rate LDPC decoding algorithm and architecture for a 5G terminal, where the algorithm also uses a general LDPC decoder structure, and the number of check nodes and variable nodes updated each time is equal to the expansion factor, i.e. the decoding parallelism is equal to the expansion factor; however, each iterative decoding operation process needs to traverse the cyclic shift submatrices of the check matrix row by row and column by column.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a method for improving the throughput rate of a QC-LDPC decoder, and solves the defects existing in the prior art.
The aim of the invention is achieved by the following technical scheme: a method of improving throughput of a QC-LDPC decoder, the method comprising:
step 1, initializing variable node and check node information;
step 2, reading column index numbers from a non-zero element column index number storage ROM of the check matrix according to the processing clock period of the decoder, and reading check node information and variable node information of positions corresponding to the column index numbers;
and step 3, calculating and updating variable nodes, storing, and reading non-zero element values of the check matrix and the number of non-zero elements in each row of the check matrix.
Step 4, calculating and updating check nodes and variable nodes and storing;
and 5, verifying or judging the variable node information obtained by calculation in the step 4 according to the verification rule of the decoding result of the LDPC code, if the verification or judgment requirement is met, ending the decoding, otherwise, repeating the steps 2 to 4 until the verification or judgment requirement is met.
The initializing variable node and check node information comprises: storing the information frame to be decoded into RAM as initial value of variable node, setting another RAM to store check node information, when the check node is used for the first time, using initial value as 0, otherwise using value read out from RAM for storing check node information.
The reading of the check node information and the variable node information of the corresponding position of the column index number comprises the following steps: according to the column index number read from the non-zero element column index number storage ROM of the check matrix, the column position number of the non-zero element in the check matrix is obtained, the reading address and the reading enabling of the RAM storing the check node information and the variable node information are generated, and corresponding information is read from the check node RAM and the variable node RAM.
The calculating and updating variable nodes in the step 3 and storing include: and according to the calculation mode of the new variable node information = old variable node information-old check node information, calculating to obtain new variable node information, and storing the new variable node information into a storage space of the old variable node information.
The reading of the non-zero element value of the check matrix and the number of the non-zero elements in each row of the check matrix comprises the following steps: and (3) according to the frequency and the sequence of the column index numbers read in the step (2), sequentially reading the non-zero element values of the check matrix from the non-zero element storage ROM of the check matrix, and reading the non-zero element number values in each row of the check matrix from the non-zero element number storage ROM in each row of the check matrix.
The computing and updating check nodes and variable nodes and storing comprises: and (3) calculating the minimum value and the next minimum value of each row according to the LDPC decoding algorithm through the obtained non-zero element values of the check matrix, the number of the non-zero elements in each row and the new variable node information obtained by calculation in the step (3), calculating the check node information and the variable node information of each row, and finally storing the calculation result into a corresponding RAM.
The device for improving the throughput rate of the QC-LDPC decoder comprises an initialization module, a reading module, a calculation module and a verification judging module;
the initialization module: the method comprises the steps of storing an information frame to be decoded into a RAM (random access memory) as an initial value of a variable node, setting another RAM to store check node information, wherein the initial value is 0 when the check node is used for the first time, and otherwise, using the check node information value read out from the RAM;
the reading module is used for: the system comprises a check matrix, a variable node RAM, a non-zero element column index number, a Random Access Memory (RAM), a variable node RAM, a non-zero element column index number and a variable node RAM, wherein the non-zero element column index number is used for reading the non-zero element column index number in the check matrix, the non-zero element column index number is used for generating a reading address and a reading enable of the non-zero element column index number and the variable node RAM; according to the frequency and the sequence of the read column index numbers, sequentially reading the non-zero element values of the check matrix from the non-zero element value ROM of the check matrix, and reading the non-zero element number values in each row of the check matrix from the non-zero element number storage ROM in each row of the check matrix;
the calculation module is used for: the method comprises the steps of calculating new variable node information according to a calculation mode of new variable node information = old variable node information-old check node information, and storing the new variable node information in a storage space of the old variable node information; calculating the minimum value and the next minimum value of each row according to the LDPC decoding algorithm through the obtained non-zero element values of the check matrix, the number of the non-zero elements of each row and the calculated new variable node information, calculating the check node information and the variable node information of each row, and finally storing the calculation result into a corresponding RAM;
the verification judging module is used for: and verifying the variable node information obtained by calculation according to the verification rule of the decoding result of the LDPC code, and ending the decoding if the verification result is that the decoding is correct or the number of iterative operation is equal to the set maximum number of iterations.
A computer device, comprising: the system comprises a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor realizes the steps of the method when executing the computer program.
The invention has the following advantages: a method, device and equipment for improving throughput rate of QC-LDPC decoder, when decoding, adopt the mode of storing the non-zero element value of cyclic shift submatrix of check matrix and its corresponding column index number and non-zero element number of each line in check matrix, can greatly reduce the processing clock consumed by iterative operation of each decoding, thus improve throughput rate of decoder, and reduce the consumption of storage resources.
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FIG. 1 is a schematic flow chart of the present invention.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Accordingly, the following detailed description of the embodiments of the present application, provided in connection with the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application. The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, one embodiment of the present invention relates to a method for improving throughput of a QC-LDPC decoder, where, when decoding is implemented, only non-zero elements in a cyclic shift sub-matrix in a check matrix are stored, and a column index number of the non-zero elements and the number of the non-zero elements in each row of the check matrix are stored in another storage space. In the decoding process, each time according to the received signal, the check matrix and the check node, the variable node is updated or the operation process of updating the check node according to the variable node and the check matrix, the non-zero elements of the check matrix are read out from the storage space in sequence to participate in the operation.
The implementation processes of S2 to S6 can be carried out step by step in a pipeline mode. Therefore, the FPGA processing time period consumed by completing one decoding iterative operation process is determined by the continuous clock cycle number of reading the index number of the non-zero element column, namely the number of the non-zero elements in the check matrix.
Further, the specific operation of S1 is: storing the information frame to be decoded into a RAM as an initial value of a variable node; another RAM is designed for storing the check node information, with an initial value of 0 being used for the first time the check node is used, otherwise the value read out from the check node RAM is used.
Wherein the initialization process further comprises: initializing a non-zero element column index number ROM of the check matrix, a non-zero element value ROM of the check matrix and a non-zero element number ROM in each row of the check matrix.
The process mainly comprises traversing the value characteristic of each cyclic shift submatrix in the check matrix, and then respectively recording the column index (i.e. column number) of the non-zero elements, the non-zero element values and the number of the non-zero elements in each row. Wherein the non-zero element refers to an element whose cyclic shift submatrix value is non-1.
The specific operation of S2 is as follows: and sequentially reading out the column index numbers from the non-zero element column index number storage ROM of the check matrix according to the processing clock period of the decoder. The values in the ROM are initialized in advance, column index numbers corresponding to all non-zero elements of the check matrix are stored, a line-by-line storage mode is adopted during storage, namely, the values of the non-zero elements of the first line of the check matrix are stored in advance, the values of the non-zero elements of the second line of the check matrix are stored in advance, and the like.
The specific operation process of S3 is as follows: and generating a storage RAM reading address and reading enabling of the check node information and the variable node information according to the read column index number, namely the column position number of the non-zero element in the check matrix, and reading corresponding information from the check node RAM and the variable node RAM. The check node information and the variable node information are respectively stored in different RAMs.
S4, the specific operation process is as follows: new variable node information = old variable node information-old check node information. In the formula, the old variable node signal and the old check node information are obtained by S2. And storing the calculated new variable node information into a storage space of the old variable node information.
S5, the specific operation process is as follows: and sequentially reading non-zero element values of the check matrix from the cyclic shift submatrix ROM and non-zero element values of each row of the check matrix from the non-zero element value ROM of each row according to the frequency and the sequence of reading the column index numbers in the S3.
S6, the specific operation process is as follows: and (3) calculating the minimum value and the next minimum value of each row according to the LDPC decoding algorithm by using the check matrix non-zero element values obtained in the process 5, the number of non-zero elements in each row and the new variable node information obtained in the process 4, calculating the check node information and the variable node information of each row, and storing the calculation result into a corresponding RAM.
The specific operation of S7 is as follows: and (3) verifying the variable information obtained by the calculation in the step (S6) according to the verification rule of the decoding result of the LDPC code, if the verification result is that the decoding is correct or the number of iterative operation is equal to the set maximum iterative number, exiting the decoding process, otherwise, performing the next iterative operation, namely repeating the processes from the step (S2) to the step (S6).
Taking a decoding process when the scene set index is 0 and the base graph of the LDPC code defined by 5G as an example, wherein the base graph is an LDPC code pattern defined by 5G; the LDPC pattern defined by 5G includes both base pattern 1 and base pattern 2. The check matrix used by the LDPC code of the base figure 1 is a large matrix, and the check matrix used by the LDPC code of the base figure 2 is a small matrix; scene set index: the rule used when defining the LDPC code for 5G can be understood as that different scene set indexes correspond to different LDPC code check matrixes; the present invention is described below.
According to the 5G protocol, the check matrix of the LDPC code represents a 46×68 two-dimensional matrix in a cyclic shift sub-matrix manner. The value x of each element in the cyclic shift submatrix represents that the submatrix corresponding to the element is obtained by cyclic right shift x bits of a unit matrix of Zc×Zc, wherein Zc is an expansion factor, and the maximum value is 384.
The number of non-zero elements in the cyclic shift sub-matrix is 316. When the method is implemented, the 316 non-zero element values, column index numbers corresponding to the 316 non-zero elements and the number of the non-zero elements in each row of the check matrix are respectively stored. In this scenario, if the FPGA is used to implement LDPC decoding, only 316 processing clock cycles are required to complete one decoding iteration operation, and a minimum number of processing clock cycles required for read-write memory delay and control state transitions are added, and each clock cycle completes the decoding operation of one submatrix. If the decoding process does not use a way of storing non-zero elements and non-zero element column index numbers, but rather uses a way of storing the entire cyclic shift submatrix, then at least 46×68=3128 processing clock cycles are required for one iterative decoding operation.
And 46 x 68 = 3128 memory cells will be consumed in a manner that stores the entire cyclic shift sub-matrix, while 316+46 = 678 memory cells will be consumed in a manner that is consistent with the present invention.
As can be seen from the embodiment, the invention can increase the operation rate by approximately 9 times per decoding iteration operation compared with the conventional decoding method, and the consumed storage resource is reduced by 3/4. However, employing the present invention only adds a certain degree of control complexity.
The invention relates to an implementation device for improving throughput rate of QC-LDPC decoder, which comprises an initialization module, a reading module, a calculation module and a verification judging module;
further, the initialization module: the method comprises the steps of storing an information frame to be decoded into a RAM (random access memory) as an initial value of a variable node, setting another RAM to store check node information, wherein the initial value is 0 when the check node is used for the first time, and otherwise, using the check node information value read out from the RAM;
the reading module is used for: the system comprises a check matrix, a variable node RAM, a non-zero element column index number, a Random Access Memory (RAM), a variable node RAM, a non-zero element column index number and a variable node RAM, wherein the non-zero element column index number is used for reading the non-zero element column index number in the check matrix, the non-zero element column index number is used for generating a reading address and a reading enable of the non-zero element column index number and the variable node RAM; according to the frequency and the sequence of the read column index numbers, sequentially reading the non-zero element values of the check matrix from the non-zero element value ROM of the check matrix, and reading the non-zero element number values in each row of the check matrix from the non-zero element number storage ROM in each row of the check matrix;
the calculation module is used for: the method comprises the steps of calculating new variable node information according to a calculation mode of new variable node information = old variable node information-old check node information, and storing the new variable node information in a storage space of the old variable node information; calculating the minimum value and the next minimum value of each row according to the LDPC decoding algorithm through the obtained non-zero element values of the check matrix, the number of the non-zero elements of each row and the calculated new variable node information, calculating the check node information and the variable node information of each row, and finally storing the calculation result into a corresponding RAM;
the verification judging module is used for: and verifying the variable node information obtained by calculation according to the verification rule of the decoding result of the LDPC code, and ending the decoding if the verification result is that the decoding is correct or the number of iterative operation is equal to the set maximum number of iterations.
Yet another embodiment of the present invention is directed to a computer device comprising: the method comprises the steps of realizing the realization method for improving the throughput rate of the QC-LDPC decoder when the processor executes the computer program.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (6)
1. The method for improving the throughput rate of the QC-LDPC decoder is characterized by comprising the following steps of: the method comprises the following steps:
step 1, initializing variable node and check node information;
step 2, reading column index numbers from a non-zero element column index number storage ROM of the check matrix according to the processing clock period of the decoder, and reading check node information and variable node information of positions corresponding to the column index numbers;
step 3, calculating and updating variable nodes, storing, and reading non-zero element values of the check matrix and the number of non-zero elements in each row of the check matrix;
step 4, calculating and updating check nodes and variable nodes and storing;
step 5, verifying or judging the variable node information obtained by calculation in the step 4 according to the verification rule of the decoding result of the LDPC code, if the verification or judgment requirement is met, ending the decoding, otherwise, repeating the steps 2 to 4 until the verification or judgment requirement is met;
the reading of the check node information and the variable node information of the corresponding position of the column index number comprises the following steps: obtaining the column position number of the non-zero element in the check matrix according to the column index number read from the non-zero element column index number storage ROM of the check matrix, generating the reading address and the reading enabling of the RAM for storing the check node information and the variable node information, and reading corresponding information from the check node RAM and the variable node RAM;
the reading of the non-zero element value of the check matrix and the number of the non-zero elements in each row of the check matrix comprises the following steps: and (3) according to the frequency and the sequence of the column index numbers read in the step (2), sequentially reading the non-zero element values of the check matrix from the non-zero element storage ROM of the check matrix, and reading the non-zero element number values in each row of the check matrix from the non-zero element number storage ROM in each row of the check matrix.
2. A method of improving throughput of a QC-LDPC decoder as claimed in claim 1, wherein: the initializing variable node and check node information comprises: storing the information frame to be decoded into RAM as initial value of variable node, setting another RAM to store check node information, when the check node is used for the first time, using initial value as 0, otherwise using value read out from RAM for storing check node information.
3. A method of improving throughput of a QC-LDPC decoder as claimed in claim 1, wherein: the calculating and updating variable nodes in the step 3 and storing include: and calculating new variable node information according to the calculation mode of the new variable node information = old variable node information-old check node information, and storing the new variable node information into a storage space of the old variable node information.
4. A method of improving throughput of a QC-LDPC decoder as claimed in claim 1, wherein: the computing and updating check nodes and variable nodes and storing comprises: and (3) calculating the minimum value and the next minimum value of each row according to the LDPC decoding algorithm through the obtained non-zero element values of the check matrix, the number of the non-zero elements in each row and the new variable node information obtained by calculation in the step (3), calculating the check node information and the variable node information of each row, and finally storing the calculation result into a corresponding RAM.
5. The device for improving throughput rate of QC-LDPC decoder is characterized in that: the system comprises an initialization module, a reading module, a calculation module and a verification judging module;
the initialization module: the method comprises the steps of storing an information frame to be decoded into a RAM (random access memory) as an initial value of a variable node, setting another RAM to store check node information, wherein the initial value is 0 when the check node is used for the first time, and otherwise, using the check node information value read out from the RAM;
the reading module is used for: the system comprises a check matrix, a variable node RAM, a non-zero element column index number, a Random Access Memory (RAM), a variable node RAM, a non-zero element column index number and a variable node RAM, wherein the non-zero element column index number is used for reading the non-zero element column index number in the check matrix, the non-zero element column index number is used for generating a reading address and a reading enable of the non-zero element column index number and the variable node RAM; according to the frequency and the sequence of the read column index numbers, sequentially reading the non-zero element values of the check matrix from the non-zero element value ROM of the check matrix, and reading the non-zero element number values in each row of the check matrix from the non-zero element number storage ROM in each row of the check matrix;
the calculation module is used for: the method comprises the steps of calculating new variable node information according to a calculation mode of new variable node information = old variable node information-old check node information, and storing the new variable node information in a storage space of the old variable node information; calculating the minimum value and the next minimum value of each row according to the LDPC decoding algorithm through the obtained non-zero element values of the check matrix, the number of the non-zero elements of each row and the calculated new variable node information, calculating the check node information and the variable node information of each row, and finally storing the calculation result into a corresponding RAM;
the verification judging module is used for: and verifying the variable node information obtained by calculation according to the verification rule of the decoding result of the LDPC code, and ending the decoding if the verification result is that the decoding is correct or the number of iterative operation is equal to the set maximum number of iterations.
6. A computer device, characterized by: comprising the following steps: a memory and a processor, the memory having stored thereon a computer program which, when executed by the processor, implements the steps of the method of any of claims 1-4.
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