CN112187286A - Multi-mode LDPC decoder applied to CCSDS satellite deep space communication - Google Patents
Multi-mode LDPC decoder applied to CCSDS satellite deep space communication Download PDFInfo
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
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Abstract
The invention belongs to the technical field of wireless digital communication and broadcasting, and particularly relates to a multi-mode LDPC decoder applied to CCSDS satellite deep space communication. The DPC decoder structure of the invention comprises: the system comprises a central controller, a check matrix information memory (Hbase), a Check Node Memory (CNM), a variable node parity memory group (VNM), a check node processor, a variable node processor and a read-write bypass and cross controller; the decoder adopts a TDMP algorithm with two-phase overlapping, and under the premise of adding a small amount of combinational logic, the updating sequence of the non-zero submatrix is changed to ensure that the updating process of the variable node and the updating process of the check node are mutually overlapped, thereby reducing the time required by decoding and increasing the decoding throughput rate by about 80 percent; meanwhile, the decoder has stronger universality.
Description
Technical Field
The invention belongs to the technical field of wireless digital communication and broadcasting, and particularly relates to an LDPC decoder.
Background
Satellite communication has good coverage area and can make up the defect that the traditional mobile communication is limited by geographical conditions. In order to meet the increasing data transmission requirements in satellite communication, the transmission rate and reliability of the satellite communication system need to be improved. The channel coding and decoding technology can enhance the anti-interference capability of data and improve the reliability of a communication system. The LDPC code of the CCSDS deep space communication standard is widely applied to the satellite communication field by virtue of good performance.
LDPC codes have been proposed by Gallager in 1962, and have been widely applied in many communication standards as a channel error correction code with performance approaching shannon limit, for example, DTMB, CMMB, WLAN, WiMAX, CCSDS, and fifth generation mobile communication technology (5G) all adopt LDPC codes as their channel error correction codes. The reason is that the well-designed LDPC code has stronger error correction performance and lower complexity of hardware implementation than other channel error correction codes. In hardware implementation, the parallelism of the decoder can be flexibly selected according to different communication standards.
The early LDPC decoder mostly adopts a full-parallel TPMP algorithm, and along with the increase of the LDPC code length and the increase of the check matrix scale, the chip power consumption and the area are increased due to the large occupation of hardware resources by the TPMP algorithm. Meanwhile, in order to meet different channel environments, a plurality of communication standards all provide multi-mode requirements, and a TDMP algorithm LDPC decoder based on a layered decoding idea gradually becomes mainstream. However, the decoder throughput rate of the TDMP algorithm with the parallelism of a single non-zero submatrix is low, and especially when the check matrix contains a large number of non-zero submatrixes, the one-time iteration time of the TDMP algorithm is 2t (t is the number of the non-zero submatrixes), and the throughput rate problem needs to be solved urgently.
The two-phase overlapping technology is a new technology after the TDMP algorithm is improved, and changes the node updating sequence by mining the correlation among different nodes in the check matrix, so that the updating process of the variable nodes and the updating process of the check nodes are carried out simultaneously and are overlapped with each other. The problem of low time utilization rate of the TDMP algorithm to hardware resources is solved, and compared with an LDPC decoder of a common TDMP algorithm, the decoder adopting the two-phase overlapping technology has the advantage that the decoding speed can be improved by about 80%.
Disclosure of Invention
The invention aims to provide an LDPC multi-mode decoder which is based on a two-phase overlapping technology, has high throughput rate and low complexity and is applied to a CCSDS deep space communication standard.
The LDPC multi-mode decoder applied to the CCSDS deep space communication standard is based on a two-phase overlapping technology, and the updating process of the variable nodes and the updating process of the check nodes are simultaneously carried out and are overlapped with each other by rearranging the updating sequence of the non-zero submatrixes in the check matrix. The structure includes: a central controller, a check matrix information memory (noted Hbase), a Check Node Memory (CNM), a variable node parity memory bank (VNM), a check node processor, a variable node processor, and a read-write bypass and cross controller.
Wherein, the data flow in the primary decoding process is as follows: firstly, reading matrix information from an Hbase memory, and carrying out overall configuration on a decoder through a central controller module, wherein the configuration is kept unchanged in the whole decoding process; after receiving LLR information from a channel after passing through a demodulator, a decoder firstly stores the LLR information in an input buffer temporarily and then enters a VNM memory group, and a variable node processor and a check node processor simultaneously read, calculate and write back data to the VNM memory group; meanwhile, the check node processor also needs to read, calculate and write the CNM memory; when the decoding is completed, the data is read out from the VNM memory bank to the output buffer module, and then the data is output.
The state machine of the two-phase overlapping decoder of the present invention, as shown in fig. 2, has a total of 4 states, which are idle state, initialization state, decoding state, and output state. After the system is powered on or one frame of data is decoded, the decoder is in an idle state, and when the data amount stored in the input buffer reaches one frame, the decoder enters an initialization state; in an initialization state, a decoder reads data in an input buffer into a VNM memory, and simultaneously initializes the data in the CNM memory to 0; after the initialization is finished, entering a decoding state and starting decoding; if the set iteration times are not reached in the decoding process, the decoding state is kept to continue decoding until the maximum iteration times are reached or the checker passes the check, and the decoding enters an output state; and outputting the decoding result in an output state. And automatically entering an idle state after the output is finished, and waiting for finishing the buffering of the next frame data.
In the invention, the check node processor is a group of 128 general computing units in total and is mainly used for checkingThe structure of one computing unit of the computation of information update is shown in fig. 3, and the computation unit is divided into 3 stages of pipelines, and comprises 4 sub-operators: information restorer, information replacer, adder, minimum searcher. The specific working mode is as follows: when the check node is updated, the posterior information Pos of the kth iteration stored in the VNM is firstly storedkPerforming cyclic shift by the information replacer while compressing the outer information Exi in CNMkRecovering the data through the information restorer; then, the information after cyclic shift and the recovered information are summed through an adder to obtain prior information Pri of the kth iterationkMeanwhile, the prior information is updated through a minimum searcher to obtain Exi external information compressed by the check node after the (k + 1) th iterationk+1。
In the invention, the variable node processor is a group of 128 general calculation units in total, and is mainly used for calculating variable information updating, wherein the structure of one calculation unit is shown in fig. 4, and the calculation unit is divided into 3 stages of pipelines in total and comprises 4 sub-operators: information restorer, adder, checker, and information replacer. The specific working mode is as follows: when a variable node is updated, firstly, the compressed external information Exi in the CNM is usedk+1Recovering the data through the information restorer; the recovered information is then compared with the prior information Pri of the kth iteration stored in the VNMkSumming by an adder to obtain posterior information Pos of the (k + 1) th iterationk+1(ii) a The information of the later verification passes through a checker to carry out parity check, and the information of the later verification passes through an information replacer to carry out cyclic shift and is stored in the VNM.
In the present invention, the variable node parity memory (VNM) is composed of a set of two dual-port RAMs in total, as shown in fig. 5. The system consists of an odd node memory BANK1 and an even node memory BANK 0; the variable node processor is mainly used for storing a calculation result of the check node processor for updating check information and a calculation result of the variable node processor for updating variable information; the storage of the check information and the variable information is divided into the following 4 cases: firstly, if the sequence of the nodes for updating the current checking information is an even number, the nodes are stored in the BANK 0; if the sequence of the nodes for updating the current checking information is odd, the nodes are stored into the BANK 1; if the sequence of the current nodes for updating the variable information is even, the current nodes are stored in the BANK 0; if the sequence of the nodes for updating the variable information is odd, the nodes are stored in the BANK1, the variable nodes are divided into odd-even sets, the requirement that two sets of read-write ports work simultaneously can be met, and the read-write bandwidth of the memory is increased by using the memory odd-even set division technology under the condition that the total capacity of the memory is equal.
In the invention, the check matrix information memory (Hbase) is a single-port ROM memory with read-only data and is mainly used for storing the information of the update sequence of the non-zero submatrix of the check matrix after being optimized by a two-phase overlapping algorithm. And rearranging the nodes which conflict when the variable nodes are updated and the check nodes are updated, so that most of the variable node updates and the check nodes can be simultaneously updated, and the nodes which cannot be simultaneously updated are subjected to pipeline bubble processing. The non-zero submatrix update order table is shown in fig. 7, the optimized non-zero submatrix update order can avoid the correlation problem of the node update order, and meanwhile, the access times of the variable node memory module are reduced through a read-write bypass technology.
The LDPC decoder provided by the invention supports the CCSDS deep space communication standard. The decoder adopts a two-phase overlapped decoding algorithm, and deeply excavates the throughput rate upper limit of the algorithm by rearranging the updating sequence of the non-zero submatrixes in the check matrix, so that the updating process of the variable nodes and the updating process of the check nodes are carried out simultaneously and are overlapped with each other. Thereby improving the time utilization rate of hardware resources. The throughput of the decoder can be improved by about 80% at the cost of increasing a small amount of combinational logic circuit area.
Drawings
FIG. 1 is a two-phase overlapping LDPC decoder architecture.
Fig. 2 is a decoder state machine.
FIG. 3 is a check node processor.
FIG. 4 is a variable node processor.
FIG. 5 is a variable node parity memory with read and write bypass and crossover controllers.
FIG. 6 illustrates a two-phase overlap technique and a node update sequence.
Fig. 7 is an optimized node update sequence diagram.
Fig. 8 is a graph of decoder BER from the test.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a designed LDPC decoder based on the two-phase overlapping technique, in which important modules of the LDPC decoder based on the two-phase overlapping technique are shown, including a central controller module, and a state machine shown in fig. 2 performs decoding flow control of the decoder, a matrix information memory, a Check Node Memory (CNM), a variable node parity memory (VNM), a check node processor, a variable node processor, and a read-write bypass and cross controller module (bypass and cross). The data flow in the primary decoding process is that firstly, the matrix information is read from the Hbase memory, and the overall configuration of the decoder is carried out through the central controller module, and the configuration is kept unchanged in the whole decoding process. After receiving LLR information from a channel after passing through a demodulator, a decoder firstly stores the LLR information in an input buffer temporarily and then enters a VNM memory group, and a variable node processor and a check node processor simultaneously read, calculate and write back data to the VNM memory group; meanwhile, the check node processor also needs to perform reading, calculating and writing operations on the CNM memory. When the decoding is completed, the data is read out from the VNM memory bank to the output buffer module, and then the data is output.
The state machine of the two-phase overlapping decoder, as shown in fig. 2, has a total of 4 states, which are idle state, initialization state, decoding state, and output state. After the system is powered on or one frame of data is decoded, the decoder is in an idle state, and when the data amount stored in the input buffer reaches one frame, the decoder enters an initialization state; in an initialization state, a decoder reads data in an input buffer into a VNM memory, and simultaneously initializes the data in the CNM memory to 0; after the initialization is finished, entering a decoding state and starting decoding; if the set iteration times are not reached in the decoding process, the decoding state is kept to continue decoding until the maximum iteration times are reached or the checker passes the check, and the decoding enters an output state; and outputting the decoding result in an output state. And automatically entering an idle state after the output is finished, and waiting for finishing the buffering of the next frame data.
The invention provides 128 check node processors, the specific structure of which is shown in FIG. 3, 3 stages of pipelines are divided, and the total number of the pipelines comprises 4 sub-operation modules which comprise an information restorer, an information replacer, an adder and a minimum searcher. The function of each operational submodule is as follows: the first stage pipeline includes a data restorer for indexing the position cur _ loc of the currently scanned submatrix and the required extrinsic information Exi and an information replacement networkkRecovering from the Check Node Memory (CNM); meanwhile, data among different nodes are interconnected by an information replacement network. The second stage pipeline performs subtraction of corresponding data. The third stage pipeline comprises a minimum searcher for inputting prior information PrikAnd searching the serial minimum value and the secondary minimum value, and storing the compressed information into a check node memory module.
The invention provides a variable node processor with 128 total, the concrete structure is given in figure 4, 3-stage production line is divided totally, and the variable node processor comprises 4 sub-operation modules, including: information restorer, adder, checker, and information replacer. The function of each operational submodule is as follows: the first stage pipeline contains a data restorer which is used for indexing the position cur _ loc of the currently scanned sub-matrix as an address and for adding the required extrinsic information Exik+1Recovering from the check node processor; the second stage pipeline performs addition operations of corresponding data. The third stage pipeline includes an information permuter for circular shifting of information. Meanwhile, the system comprises a checker, and posterior information Pos generated by the (k + 1) th iterationk+1A parity check is performed.
The variable node parity memory proposed by the present invention is as shown in fig. 5 (b). An odd-even set memory is composed of an odd node memory BANK1 and an even node memory BANK 0. In the CNU or VNU calculation process, modulo-2 operation is first performed on a memory address (vnm _ addr) signal to be accessed, and data at odd addresses is written into BANK1 and data at even addresses is written into BANK 0. Similarly, at the time of data reading, data of even-numbered nodes is read from BANK0, and data of odd-numbered nodes is read from BANK 1. Because the odd node memory BANK1 and the even node memory BANK0 can perform respective data read-write operations simultaneously, the data processing capacity of the overall variable node memory block is doubled. The data input and output of the odd and even nodes are controlled by the read/write bypass and cross controller module shown in fig. 5 (a). Meanwhile, when the bypass signal is 1, the input information of the variable node can be directly transmitted to the check node for output, and a process of storing and reading the information out of the VNM is avoided.
The method for rearranging and optimizing the updating sequence of the non-zero submatrices in the check matrix, which is provided by the invention, is as shown in figure 6: wherein (a) indicates a node update order when two-phase overlap is not employed; (b) indicating the node update order after the two phases overlap. (c) And showing the updating sequence of the nodes after rearrangement optimization. In the graph (a), firstly, Check Node Update (CNU) is carried out, then Variable Node Update (VNU) is carried out, and the two processes are processed in a time-sharing mode. In order to improve the processing efficiency, the two-phase overlap technique shown in fig. (b) is adopted, and the check node update of the block in the next row and the variable node update of the block in the current row are overlapped and processed at the same time. This leads to two types of errors: one is that for the node 7, the i +1 CNU update process precedes the i VNU update process, which results in the i +1 sub-iteration process being performed when the i sub-iteration result is not completed, so that the decoding result is erroneous; secondly, for the node 17, CNU update and VNU update operations are performed simultaneously in the same clock cycle, which results in the memory reading and writing the same address and decoding errors. After rearrangement, the update sequence shown in (c) is obtained, so that the same node is ensured to firstly perform the ith VNU update and then perform the (i + 1) th CNU update, and the nodes are ensured to have correct correlation relationship.
The matrix information memory provided by the invention records the updating sequence of the non-zero submatrices in the check matrix, and obtains the optimized node sequence updating diagram shown in fig. 7 after the node updating sequence of the whole matrix is rearranged according to the two-phase overlapping optimization algorithm. The optimized non-zero submatrix updating sequence can avoid the correlation problem of the node updating sequence, and meanwhile, the access times of the variable node memory module are reduced through a read-write bypass technology.
Claims (6)
1. An LDPC multi-mode decoder applied to CCSDS deep space communication standard is characterized in that based on a two-phase overlapping technology, the updating process of variable nodes and the updating process of check nodes are simultaneously carried out and overlapped with each other by rearranging the updating sequence of non-zero submatrices in a check matrix; the structure includes: the system comprises a central controller, a check matrix information memory (Hbase), a Check Node Memory (CNM), a variable node parity memory group (VNM), a check node processor, a variable node processor and a read-write bypass and cross controller;
the data flow in one decoding process is as follows: firstly, reading matrix information from an Hbase memory, and carrying out overall configuration on a decoder through a central controller, wherein the configuration is kept unchanged in the whole decoding process; after receiving LLR information from a channel after passing through a demodulator, a decoder firstly stores the LLR information in an input buffer temporarily and then enters a VNM memory group, and a variable node processor and a check node processor simultaneously read, calculate and write back data to the VNM memory group; meanwhile, the check node processor also needs to read, calculate and write the CNM memory; when the decoding is completed, the data is read out from the VNM memory bank to the output buffer module, and then the data is output.
2. The LDPC multimode decoder of claim 1, wherein the state machine of the decoder has a total of 4 states, which are idle state, initialization state, decoding state, and output state; after the system is powered on or one frame of data is decoded, the decoder is in an idle state, and when the data amount stored in the input buffer reaches one frame, the decoder enters an initialization state; in an initialization state, a decoder reads data in an input buffer into a VNM memory, and simultaneously initializes the data in the CNM memory to 0; after the initialization is finished, entering a decoding state and starting decoding; if the set iteration times are not reached in the decoding process, the decoding state is kept to continue decoding until the maximum iteration times are reached or the checker passes the check, and the decoding enters an output state; outputting the decoding result in an output state; and automatically entering an idle state after the output is finished, and waiting for finishing the buffering of the next frame data.
3. LDPC multi-mode decoder according to claim 1, wherein the variable node parity memory (VNM) is comprised of two dual port RAMs; comprises an odd node memory BANK1 and an even node memory BANK 0; the variable node processor is mainly used for storing a calculation result of the check node processor for updating check information and a calculation result of the variable node processor for updating variable information; the storage of the check information and the variable information is divided into the following 4 cases: firstly, if the sequence of the nodes for updating the current checking information is an even number, the nodes are stored in the BANK 0; if the sequence of the nodes for updating the current checking information is odd, the nodes are stored into the BANK 1; if the sequence of the current nodes for updating the variable information is even, the current nodes are stored in the BANK 0; and fourthly, if the sequence of the nodes which are currently updated by the variable information is odd, storing the nodes into the BANK 1.
4. The LDPC multimode decoder according to claim 1, wherein the check matrix information memory (Hbase) is a single-port ROM memory for data read only, and is mainly used for storing information of the update order of the non-zero submatrices of the check matrix after being optimized by a two-phase overlapping algorithm.
5. The LDPC multimode decoder according to claim 1, wherein the check node processor is a group of 128 general purpose computing units, and is mainly used for computation of check information update;wherein, a computational unit divides into 3 grades of assembly lines altogether, contains 4 sub-arithmetic units: the system comprises an information restorer, an information replacer, an adder and a minimum searcher; the specific working mode is as follows: when the check node is updated, the posterior information Pos of the kth iteration stored in the VNM is firstly storedkPerforming cyclic shift by the information replacer while compressing the outer information Exi in CNMkRecovering the data through the information restorer; then, the information after cyclic shift and the recovered information are summed through an adder to obtain prior information Pri of the kth iterationkMeanwhile, the prior information is updated through a minimum searcher to obtain Exi external information compressed by the check node after the (k + 1) th iterationk+1。
6. The LDPC multimode decoder according to claim 1, wherein the variable node processor is a group of 128 general purpose computing units mainly used for computation of variable information update, wherein one computing unit is divided into 3 stages of pipelines and comprises 4 sub-operators: the system comprises an information restorer, an adder, a checker and an information replacer; the specific working mode is as follows: when a variable node is updated, firstly, the compressed external information Exi in the CNM is usedk+1Recovering the data through the information restorer; the recovered information is then compared with the prior information Pri of the kth iteration stored in the VNMkSumming by an adder to obtain posterior information Pos of the (k + 1) th iterationk+1(ii) a The information of the later verification passes through a checker to carry out parity check, and the information of the later verification passes through an information replacer to carry out cyclic shift and is stored in the VNM.
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