CN101854177A - LDPC decoder with high throughput rate - Google Patents
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Abstract
The invention discloses a high-throughput rate low-density parity check code decoder, which comprises an input cache, a check node operation unit, a variable node operation unit, an output cache, a control logic unit and an interconnection network, wherein: the decoder adopts a partial parallel decoding structure, and uses x variable node operation units and y check node operation units, wherein x and y are the column number and the row number of a basic matrix of H, 1 input cache and 1 output cache respectively; each variable node operation unit is composed of a channel information accessor and an external information memory, and each check node operation unit is composed of 1 operation unit for calculating an input minimum value and an input next minimum value. The invention realizes the simultaneous input and output of the decoding without increasing the hardware consumption, thereby greatly improving the throughput rate of the decoder. The decoder may be adapted for regular/irregular LDPC codes; especially for code words with longer code length, the improvement effect of the throughput rate is more obvious.
Description
Technical field
The present invention relates to high-speed radio digital communication, technical field of optical fiber communication, be specifically related to a kind of low density parity check code (LDPC) decoder of high-throughput.
Background technology
Data always can be introduced various noises, for example synchronization loss in random noise, the demodulating process, and the multipath effect in the wireless transmission etc. in the process of transmission and storage.Because the existence of these noises has limited message transmission rate and transmission quality under certain bandwidth greatly.
Along with the continuous progress of modern communication technology, communication system direction higher to throughput gradually, that capacity is bigger and reliability is higher develops, and error control coding also thereby obtained widely using.Low density parity check code (LDPC) is a very important class sign indicating number in the error control code, added glug (RobertGallager) at [R.G.Gallager in 1963 by the Robert, Low-Density Parity-Check Codes.Cambridge, MA:MIT Press, 1963.] propose.Empirical tests, the LDPC sign indicating number can reach the error performance apart from shannon limit 0.0045dB, and simultaneously ldpc decoder is because check matrix structural, and has intrinsic decoding concurrency, can satisfy the requirement of high speed high-throughput.Thereby at aspects such as expansion new generation of wireless communication system service range, raising video broadcast system throughputs, the LDPC code table has revealed excellent performance and application prospect.
Ldpc decoder is the structure according to check matrix H, finishes decoding by iterative decoding algorithm.Because the H matrix is huge and sparse usually, thereby the structure of LDPC decoding is complicated usually, and hardware consumption is bigger.And the decoding delay of iterative algorithm is also bigger, so improve the emphasis that the throughput of LDPC decoding always is research.
For improving throughput, [Part 16:Air Interface for Fixed and Mobile BroadbandWireless AccessSystems Amendment for Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands, IEEE P802.16e-2005,2005] once used full parallel organization to make throughput reach 1Gb/s, but the hardware consumption of this method is very big; The relative complex that connects up simultaneously causes the congested problem of wiring for the bigger code word regular meeting of code length.
And famous hierarchical algorithm (is also referred to as the TDMP algorithm, with reference to M.M.Mansour and N.R.Shanbhag, " High-throughput LDPC decoders; " IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol.11, no.6, pp.976-996, Dec.2003.), though the fine use that reduces memory, total iterations also reduces to some extent, but a traditional iteration is divided into the little iteration of several times, thereby decoding delay is formed doubly with the increase of the little number of iterations of cutting apart increase, simultaneously since in its decode procedure be spreading factor with basis matrix as degree of parallelism, thereby the raising of the throughput of decoding is to increase hardware spending as cost.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of ldpc decoder, to be implemented on the basis that increases any hardware spending hardly, improves the throughput of ldpc decoder.
(2) technical scheme
For achieving the above object, the invention provides a kind of low-density parity code transcoder, this decoder comprises input-buffer, check-node arithmetic element, variable node arithmetic element, output buffers, control logic unit and internet, wherein: this decoder adopts the part parallel decoding architecture, use x variable node arithmetic element, a y check-node arithmetic element, x and y are respectively the columns and the line number of the basis matrix of H, 1 input-buffer, 1 output buffers; Each variable node arithmetic element is made of channel information memory access and external information memory, and each check-node arithmetic element is made of 1 arithmetic element of calculating input minimum value and input sub-minimum.
In the such scheme, described check-node arithmetic element adopts minimum-sum algorithm, constitute by 1 arithmetic element of calculating input minimum value and input sub-minimum, each computing has the parallel input of a plurality of inputs, the check-node arithmetic element will calculate each input in the minimum input that does not comprise under the situation of itself, and by the internet check information be passed to described variable node arithmetic element.
In the such scheme, described variable node arithmetic element is made of 1 channel information memory and 1 external information memory, channel information by described input-buffer output is not directly to enter described channel information memory access, but enters the initial value of described external information memory as external information; When iteration begins, described external information memory transmits information by the internet to described check-node arithmetic element, and simultaneously channel information is deposited in the described channel information memory access, receive the information of the described check-node arithmetic element of process verification afterwards again by the internet, and by certain calculation renewal external information, thereby finish iterative decoding one time.
In the such scheme, described input-buffer and described output buffers are used to finish serial and parallel mutual conversion, constitute by several registers.
In the such scheme, described control logic unit is used to realize the entire decoder s operation control, realizes that by state machine its decode procedure specifically comprises:
Step 3, check-node arithmetic element and variable node arithmetic element replace computing;
In the such scheme, the channel information of described input-buffer input not only is stored in the described channel information memory access, and the while also is stored in the described external information memory as the initial value of external information; And the process iterative decoding is exported each bit by described output buffers hard decision information stores when finally finishing decoding, will be exported decode results by described output buffers by described channel information memory access in described channel information memory access.
In the such scheme, beginning when output decoding when previous code word, but next word input channel information to be decoded it only is stored in the external information memory, in the time of decoding output, can read in a new set of code words; Because the information bit code length of decoding output is necessarily short than total code length, so when new code word end of input, old code word has necessarily been finished output, thereby can carry out the iterative decoding of a new round.
In the such scheme, the decode procedure of this decoder specifically comprises:
Step 1: beginning enter code word;
Step 2: after the code word input is finished, enter the iterative decoding link;
Step 3: check-node arithmetic element and variable node arithmetic element replace computing;
Step 4: when decoding finishes, begin to export decode results;
Step 5: when output is carried out,, then will carry out input and output simultaneously if new enter code word is arranged;
Step 6: when input was finished, old code word output end already then entered the check-node arithmetic element and the variable node arithmetic element replaces computing;
Step 7: when output is carried out,, then return idle condition if do not have new enter code word until end of output.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, the present invention proposes this high-throughput ldpc decoder, the ldpc decoder that improves in the past can only be after a codeword decoding output be finished, just can carry out the sequential restriction of next code word input, when adding any hardware complexity hardly, finish the time-multiplexed of decoding input and output, make whole decode procedure will decipher output time fully and " hide ", thereby improved the throughput of decoder greatly.
2, this ldpc decoder structure of the present invention's proposition, when being applied in the certain system of throughput, traditional decoder can obtain better error performance by methods such as increase maximum iteration time.
3, ldpc decoder provided by the invention on the basis that does not increase hardware consumption, carries out when realizing the decoding input and output, thereby has improved the throughput of decoder greatly.This decoder goes for rule/irregular LDPC codes; Especially long to code length code word, the raising effect of throughput is more obvious.
Description of drawings
The present invention is further described below in conjunction with drawings and Examples:
Fig. 1 is the structural representation of the high-throughput ldpc decoder that provides according to the embodiment of the invention;
Fig. 2 is the structural representation of the variable node arithmetic element VNU in the high-throughput ldpc decoder that provides according to the embodiment of the invention;
Fig. 3 is the schematic diagram of the state of a control conversion of input and output traditional ldpc decoder that can not carry out simultaneously;
Fig. 4 is the state of a control transition diagram of high-throughput ldpc decoder provided by the invention, can realize the concurrency of input and output;
Fig. 5 is the sequential chart of input, iterative decoding and the output of input and output traditional ldpc decoder that can not carry out simultaneously;
Fig. 6 is the sequential chart of input, iterative decoding and the output of high-throughput ldpc decoder provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Shown in Figure 1 according to embodiments of the invention provide (9216,4608) rule ldpc decoder, wherein the row of check matrix heavily is 6, column weight is 3.This decoder is made of input-buffer, check-node arithmetic element (CNU), variable node arithmetic element (VNU), output buffers, control logic and internet.Present embodiment adopts the part parallel decoding architecture, uses 36 VNU, 18 CNU altogether, 1 output buffers, 1 output buffers.Each VNU is made of channel information memory access (in_mem) and external information memory (ex_mem); Each CNU is made of 1 arithmetic element of calculating input minimum value and input sub-minimum.
Shown in Figure 2 is the basic structure of the variable node arithmetic element (VNU) of present embodiment, is made of channel information memory and external information memory.For satisfying the needs of high-throughput, realize that decoding input decoding output carries out simultaneously, the interative computation in decode procedure finishes, and will export decode results to output buffers by in_mem; And if this is when importing the channel information of a new word to be decoded simultaneously, this input channel information is not directly to enter in_mem, but enters the initial value of ex_mem as external information.When iteration begins, ex_mem will transmit information to CNU by the internet, and deposit channel information in in_mem simultaneously, also store necessary channel information like this among the in_mem.After ex_mem finishes the renewal computing of a check-node, can carry out the renewal computing of variable node by the channel information in in_mem just, thereby finish iterative decoding one time.
The state transition diagram of the ldpc decoder that not use decoding input and output shown in Figure 3 are carried out simultaneously, the decode procedure of its decoder is as follows:
Step 3, check-node arithmetic element and variable node arithmetic element replace computing;
For reaching the requirement that improves data throughput, carry out when realizing the decoding input with output, present embodiment improves Fig. 3, be the state transition diagram that the control unit of present embodiment adopts when circuit is realized as shown in Figure 4, as can be seen from the figure, the decode procedure of the ldpc decoder of present embodiment:
Step 1: beginning enter code word;
Step 2: after the code word input is finished, enter the iterative decoding link;
Step 3: check-node arithmetic element and variable node arithmetic element replace computing;
Step 4: when decoding finishes, begin to export decode results;
Step 5: when output is carried out,, then will carry out input and output simultaneously if new enter code word is arranged;
Step 6: when input was finished, old code word output end already then entered the check-node arithmetic element and the variable node arithmetic element replaces computing;
Step 7: when output is carried out,, then return idle condition if do not have new enter code word until end of output.
Fig. 5 and Fig. 6 represent respectively be input and output traditional ldpc decoder that can not carry out simultaneously input, iterative decoding and output sequential chart and according to the sequential chart of input, iterative decoding and the output of embodiments of the invention ldpc decoder.Wherein because present embodiment adopts (9126,4608) 1/2 code check, all output times are half of input time, thereby in Fig. 6, the decoding input and output are carried out simultaneously, when new code word end of input, the output of a last code word finishes already, can carry out the iterative decoding computing of new code word.
Fig. 5 and Fig. 6 are compared as can be known, and present embodiment can greatly reduce decoding time, has only the output of last code word to take decoding time, and the decoding of other code word output is hidden fully.Make that in the regular hour mode more shown in Figure 5 can be finished the decoding of more code words, thereby improved the throughput of decoder greatly.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a low-density parity code transcoder is characterized in that, this decoder comprises input-buffer, check-node arithmetic element, variable node arithmetic element, output buffers, control logic unit and internet, wherein:
This decoder adopts the part parallel decoding architecture, uses x variable node arithmetic element, a y check-node arithmetic element, and x and y are respectively the columns and the line number of the basis matrix of H, 1 input-buffer, 1 output buffers; Each variable node arithmetic element is made of channel information memory access and external information memory, and each check-node arithmetic element is made of 1 arithmetic element of calculating input minimum value and input sub-minimum.
2. low-density parity code transcoder according to claim 1, it is characterized in that, described check-node arithmetic element adopts minimum-sum algorithm, constitute by 1 arithmetic element of calculating input minimum value and input sub-minimum, each computing has the parallel input of a plurality of inputs, the check-node arithmetic element will calculate each input in the minimum input that does not comprise under the situation of itself, and by the internet check information be passed to described variable node arithmetic element.
3. low-density parity code transcoder according to claim 1, it is characterized in that, described variable node arithmetic element is made of 1 channel information memory and 1 external information memory, channel information by described input-buffer output is not directly to enter described channel information memory access, but enters the initial value of described external information memory as external information; When iteration begins, described external information memory transmits information by the internet to described check-node arithmetic element, and simultaneously channel information is deposited in the described channel information memory access, receive the information of the described check-node arithmetic element of process verification afterwards again by the internet, and by certain calculation renewal external information, thereby finish iterative decoding one time.
4. low-density parity code transcoder according to claim 1 is characterized in that, described input-buffer and described output buffers are used to finish serial and parallel mutual conversion, constitute by several registers.
5. low-density parity code transcoder according to claim 1 is characterized in that, described control logic unit is used to realize the entire decoder s operation control, realizes that by state machine its decode procedure specifically comprises:
Step 1, beginning enter code word;
Step 2, after code word input is finished, enter the iterative decoding link;
Step 3, check-node arithmetic element and variable node arithmetic element replace computing;
Step 4, the decode results that when decoding finishes, begins to export;
Step 5, after decoding output is finished, the new code word of input was carried out the decoding of a new round when whole low-density parity code transcoder entered idle condition.
6. low-density parity code transcoder according to claim 1, it is characterized in that, the channel information of described input-buffer input not only is stored in the described channel information memory access, and the while also is stored in the described external information memory as the initial value of external information; And the process iterative decoding is exported each bit by described output buffers hard decision information stores when finally finishing decoding, will be exported decode results by described output buffers by described channel information memory access in described channel information memory access.
7. low-density parity code transcoder according to claim 1, it is characterized in that, when beginning decoding output when previous code word, but next word input channel information to be decoded, it only is stored in the external information memory, in the time of decoding output, can reads in a new set of code words; Because the information bit code length of decoding output is necessarily short than total code length, so when new code word end of input, old code word has necessarily been finished output, thereby can carry out the iterative decoding of a new round.
8. low-density parity code transcoder according to claim 1 is characterized in that, the decode procedure of this decoder specifically comprises:
Step 1: beginning enter code word;
Step 2: after the code word input is finished, enter the iterative decoding link;
Step 3: check-node arithmetic element and variable node arithmetic element replace computing;
Step 4: when decoding finishes, begin to export decode results;
Step 5: when output is carried out,, then will carry out input and output simultaneously if new enter code word is arranged;
Step 6: when input was finished, old code word output end already then entered the check-node arithmetic element and the variable node arithmetic element replaces computing;
Step 7: when output is carried out,, then return idle condition if do not have new enter code word until end of output.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106911336A (en) * | 2017-01-17 | 2017-06-30 | 清华大学 | The high-speed parallel low density parity check coding device and its interpretation method of multi-core dispatching |
| CN107124187A (en) * | 2017-05-05 | 2017-09-01 | 南京大学 | A kind of ldpc code decoder based on equal difference check matrix applied to flash memory |
| WO2019205313A1 (en) * | 2018-04-24 | 2019-10-31 | 成都吉纬科技有限公司 | Ldpc decoder based on random bitstream update |
| CN111211790A (en) * | 2020-02-25 | 2020-05-29 | 重庆邮电大学 | High-throughput-rate LDPC decoding algorithm and architecture for 5G terminal |
| CN112134570A (en) * | 2020-08-16 | 2020-12-25 | 复旦大学 | Multi-mode LDPC decoder applied to deep space communication |
| CN112187286A (en) * | 2020-09-24 | 2021-01-05 | 复旦大学 | Multi-mode LDPC decoder applied to CCSDS satellite deep space communication |
| CN113055028A (en) * | 2021-03-18 | 2021-06-29 | 北京得瑞领新科技有限公司 | LDPC decoding method, decoder, decoding device and storage medium |
| CN113612581A (en) * | 2021-08-03 | 2021-11-05 | 浙江极传信息技术有限公司 | Universal LDPC decoding method and system with high throughput rate |
| WO2022116799A1 (en) * | 2020-12-03 | 2022-06-09 | 重庆邮电大学 | Hierarchical semi-parallel ldpc decoder system having single permutation network |
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| CN100544212C (en) * | 2006-01-23 | 2009-09-23 | 南京大学 | The loe-density parity-check code decoder of minimizing storage demand at a high speed |
| CN100542049C (en) * | 2007-03-23 | 2009-09-16 | 北京航空航天大学 | A kind of decoder device and interpretation method of LDPC sign indicating number of multi code Rate of Chinese character |
| CN101350625B (en) * | 2007-07-18 | 2011-08-31 | 北京泰美世纪科技有限公司 | High-efficiency all-purpose decoder for QC-LDPC code and decoding method thereof |
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| CN106911336B (en) * | 2017-01-17 | 2020-07-07 | 清华大学 | High-speed parallel low-density parity check decoder with multi-core scheduling and decoding method thereof |
| CN106911336A (en) * | 2017-01-17 | 2017-06-30 | 清华大学 | The high-speed parallel low density parity check coding device and its interpretation method of multi-core dispatching |
| CN107124187A (en) * | 2017-05-05 | 2017-09-01 | 南京大学 | A kind of ldpc code decoder based on equal difference check matrix applied to flash memory |
| CN107124187B (en) * | 2017-05-05 | 2020-08-11 | 南京大学 | LDPC code decoder based on equal-difference check matrix and applied to flash memory |
| WO2019205313A1 (en) * | 2018-04-24 | 2019-10-31 | 成都吉纬科技有限公司 | Ldpc decoder based on random bitstream update |
| CN111211790B (en) * | 2020-02-25 | 2023-09-29 | 重庆邮电大学 | High throughput LDPC decoding algorithm and architecture for 5G terminal |
| CN111211790A (en) * | 2020-02-25 | 2020-05-29 | 重庆邮电大学 | High-throughput-rate LDPC decoding algorithm and architecture for 5G terminal |
| CN112134570A (en) * | 2020-08-16 | 2020-12-25 | 复旦大学 | Multi-mode LDPC decoder applied to deep space communication |
| CN112187286A (en) * | 2020-09-24 | 2021-01-05 | 复旦大学 | Multi-mode LDPC decoder applied to CCSDS satellite deep space communication |
| WO2022116799A1 (en) * | 2020-12-03 | 2022-06-09 | 重庆邮电大学 | Hierarchical semi-parallel ldpc decoder system having single permutation network |
| CN113055028A (en) * | 2021-03-18 | 2021-06-29 | 北京得瑞领新科技有限公司 | LDPC decoding method, decoder, decoding device and storage medium |
| CN113055028B (en) * | 2021-03-18 | 2022-05-17 | 北京得瑞领新科技有限公司 | LDPC decoding method, decoder, decoding device and storage medium |
| CN113612581A (en) * | 2021-08-03 | 2021-11-05 | 浙江极传信息技术有限公司 | Universal LDPC decoding method and system with high throughput rate |
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