CN101262230A - A design method for low-density odd/even check code matrix - Google Patents

Abstract

The invention pertains to the communication technical field, and particularly relates to a design method of a low density parity-check matrix. Aiming at distributing the storage, avoiding the read/write conflict and simplifying an encoder, the design method of the invention designs an H check matrix based on a layer scheduling algorithm decoding method, and conducts a beam-column transform to the check matrix and searches for the largest average ring to improve performances. By adopting the method of the layer scheduling Min-Sum algorithm to decode, the matrix can simultaneously meet the requirements of realizing high performances and low complexity hardware. The matrix produced by using the method of the invention can realize an LDPC decoding circuit with low complexity and high throughput rate.

Description

A kind of method for designing of low-density odd/even check code matrix

Technical field

The invention belongs to communication technical field, be specifically related to the method for designing of check matrix of a kind of channel coding/decoding-LDPC sign indicating number of communication system.

Background technology

The LDPC sign indicating number claims that again (Low Density Parity Check Code, LDPC), it is to have sparse parity check matrix by the class that Robert doctor G.Gallager proposed in 1963 to low density parity check code.LDPC not only has the superperformance of approaching the Shannon limit, and can adopt the transfer of data of the method realization high-throughput of parallel decoding.The integrated circuit technology that is limited to complicated decoding algorithm and fell behind at that time is difficult to realize with hardware configuration, does not cause people's attention.Along with the fast development of integrated circuit technology and updating of LDPC decoding algorithm, the LDPC code weight has newly caused people's attention in the early 1990s.Therefore, the LDPC code check matrix and the codec of research high-performance low complex degree become nearest academia and industrial quarters hot issue.

In recent years, the LDPC sign indicating number is widely used in the communication of satellite digital audio frequency and video, data in magnetic disk protection, fields such as optical fiber communication.As Wimax (IEEE 802.16e), DMB-T (Chinese DTB Digital Terrestrial Broadcasting), CMMB standards such as (China Mobile multimedia broadcasting) has all adopted the LDPC sign indicating number as channel coding/decoding, and academia is applied to the LDPC sign indicating number in UWB of future generation (ultra broadband) system to replace the convolution code scheme in the ECMA-368 standard in research in recent years.

The LDPC sign indicating number is that a kind of check matrix is the linear block codes of sparse matrix, so a common LDPC sign indicating number is to represent with its check matrix H, as accompanying drawing 1.The check matrix H correspondence of accompanying drawing 1 triplex row seven row, and expression has seven variable nodes, three check-nodes.It can also represent annexation, V1 with the Tanner figure shown in the accompanying drawing 2 simultaneously ... V7 is seven variable nodes, C1 ... C3 is 3 check-nodes.

Can obtain generator matrix (G) to be used for coding by the H matrix.If source message code element represents that with u the message behind the coding represents that with x the code element that receiver receives is r.Then the relation of x and u is suc as formula 1.If when the code element that receives equaled x, then the relation of r and H as shown in Equation 2.

x＝u·G (1)

r·H ^T＝0 (2)

The decoding algorithm of LDPC has Belief-Propagation, Sum-Product, and Min-Sum or the like, wherein the Min-Sum algorithm is with low complex degree, and more excellent characteristics such as performance more and more are subject to people's attention.Yet the complexity of decoder also is decided by different dispatching methods with throughput, wherein based on layer (Layered) dispatching algorithm owing to upgrade the information of variable node immediately, can restrain fast, and can simplify hardware complexity and become the focus of recent people research.Will be based on being described below that layer scheduling and Min-Sum algorithm combine:

[1] all L (Q of initialization _i)=L (c _i)

[2]L(q _ij)＝L(Q _i)-L(r _ji)

[3] upgrade L (r _Ji) value $L\left(r_{\mathrm{ji}}\right)=\underset{i^{\′}\∈V\left(j\right)\backslash i}{\mathrm{\Π}}\mathrm{sign}\left(L\left(q_{i^{\′}j}\right)\right)\·\underset{i^{\′}\∈V\left(j\right)\backslash i}{\mathrm{Min}}\left(\right|L\left(q_{i^{\′}j}\right)\left|\right)$

[4] upgrade L (q _Ij) value L (Q _i)=L (q _Ij)+L (r _Ji)

[5] ${\hat{c}}_i=\left\{\begin{array}{ccc}1& \mathrm{if}& L\left(Q_i\right)<0\\ 0& \mathrm{esle}& \end{array}\right.$

If finish the 5th step cH ^T=0 establishment or maximum iteration time arrive and just stop, otherwise go on foot since second again.

L (c wherein _i) be the maximum likelihood probability value (LLR) of i code element information receiving, L (Q _i) expression i variable node information, L (q _Ij) information of expression from variable node i to check-node j, L (r _Ji) information of expression from check-node j to variable node i.The sign function representation is asked symbol, and the Min function representation is minimized, || absolute value is asked in expression.I ' ∈ V (j) i represent to remove the variable nodes that is connected with j check-node all outside i the variable node.

But when weight d was big, convergence rate was not fairly obvious at the check matrix column that adopts for the algorithm that is based on layer scheduling, and this is designed to when just requiring high-ranking officers to test matrix be listed as to the less H matrix of weight.So this matrix is more sparse with respect to the check matrix of common dispatching algorithm, therefore be called the supersparsity matrix.When adopting the H check matrix of particular design, this dispatching algorithm adopts the hardware shown in the accompanying drawing 3 to compare as shown in Figure 4 with the common hardware configuration that dispatching algorithm realized when good integrated circuit technology, owing to save the switching network from the check-node to the variable node, and only needing one group of variable node information memory cell just can realize overlapping handles, saved 30% ~ 40% hardware cost, and layer scheduling algorithm only needs the iterations of half just can reach the performance same with common dispatching algorithm, promptly under same performance requirement, the data throughput of decoding circuit reaches 2 times of other algorithm nearly.

Summary of the invention

The objective of the invention is to propose a kind of method for designing of check matrix of the ldpc decoder that can realize low complex degree, high-throughput.

The method for designing of the check matrix of the ldpc decoder that the present invention proposes, be with memory distribution, to avoid the memory read write conflict and simplify encoder serve as that constraint designs the H check matrix based on layer scheduling algorithm decoding, and to the conversion of check matrix procession with seek maximum average ring to promote performance.This matrix is when adopting above-mentioned Min-Sum algorithm based on layer scheduling to decipher the hard-wired demand that can satisfy high-performance and low complex degree simultaneously.

Before design H check matrix, need following several concrete parameter:

Code length: C

Code check: R

Submatrix size: S.

The H rectangular array is to highest weighting: d _Max

The required memory piecemeal of H matrix variables node quantity: M _b

Above-mentioned parameter must have following mutual restriction relation:

1. code length C is necessary for the integral multiple of submatrix size S, and promptly the H matrix is total to C _M=C/S row;

2.C _MBe necessary for integer, C with the product of R _M* (1-R) equal the line number R of H matrix _M

3. submatrix is big more, and the structuring of matrix is strong more, and last hardware complexity is low more, but can cause performance decrease.

Row are to weight limit d _MaxCheck-node that will decision H matrix is divided into several subclass (being so-called Layer), and if to establish a minimum block storage degree of depth be D, then $d_{\max }>\frac{R_M}{D}.$ Can adopt like this and decipher, improve the throughput of data greatly based on layer scheduling algorithm.d _MaxBig more then decoding performance is good more, but can cause the memory read write conflict when adopting based on layer scheduling algorithm.All row equal all horizontal weight sums to the weight sum, and row are 2 to the weight minimum, so d _Max〉=3.

Because each variable node information all will be preserved, so what memory cell code length C need altogether to have determined, these memory cell will be stored in M respectively _bOn the block storage, M _bThe more little memory block number that then needs is few more, but can cause read/write conflict, can only reduce the data throughput of decoder for fear of conflict.But M _bThen can cause the memory number a lot of and the degree of depth each memory block is very little too greatly, it is very big to result in area.

Because the H matrix is the matrix of accurate circulation (QC), promptly matrix is made of a lot of subcycle matrixes, and accompanying drawing 5 will be used hereinafter for four kinds of forms of subcycle matrix.These four kinds of submatrixs are the square formation of the capable S row of S.Accompanying drawing 5-1 empty matrix claims null matrix again.Accompanying drawing 5-2 is a unit matrix, and it is 1 that the element on the diagonal is only arranged, and all the other positions are zero.Accompanying drawing 5-3 is that cyclic shift is the square formation of K, is about to unit matrix K the positions of elements that move right, and unit matrix can represent that empty matrix can be represented with K=-1 with this form of K=0.Accompanying drawing 5-4 represents that matrix is non-empty matrix for this reason.

The key step of design H matrix is as follows:

(1) fixed pattern of division of the memory piecemeal of matrix variables node and check information code element distributes.

The information memory cell of variable node can take the chip area about 30% ~ 50% in the hardware configuration that employing realizes based on layer scheduling algorithm.Because variable information memory cell total quantity equals C _MSo the piece number of working as the memory that needs is few more, when the degree of depth of every block storage was big more, last area of chip was more little.Information code element to variable node partly adopts different memory method of partitions with the verification code element.In order to simplify the structure of encoder, the row weight is set to 2 and also only arranges two block storages in the verification code element of variable node (being called for short PN), and the every degree of depth is R _M-1.Removing C _M-R _MOutside the verification code element partly adopt fixed pattern to distribute, and submatrix value K=0, this distribution also can reduce the quantity of memory and simplify variable node information and the switching network of check-node information.C _M-R _MThe code element at place is then general because the constraint of encoder must be arranged in other memory.Information code element of variable node (IN) and C _M-R _MPart is by M _b-2 block storages are stored, and the depth capacity of every block storage is

Minimum-depth is

And require this M _b-2 block storage degree of depth summations equal C _M-R _M+ 1.Variable information code element and C _M-R _MPlace's code element from left to right is stored in each block storage successively continuously, and after the arrangement of lastblock memory had been expired, the information of then inciting somebody to action continuous code element after this left next block storage in, and the like.Fig. 6 has showed that briefly a kind of fixed pattern distribution example of simple check information node section and memory are piecemeals how.Arthmetic statement is as follows, and wherein NOT_EMPTY represents subcycle matrix non-NULL.

A) all submatrix values of initialization basic matrix H are-1.

B) produce variable node verification code element fixed pattern.

for i＝0 to R _M do

H(i，C _M-R _M+i+1)＝0

H(i，C _M-R _M+i)＝0

end for

H(R _M/2，C _M-R _M)＝0

H(0，C _M-R _M)＝NOT_EMPTY

H(R _M-1，C _M-R _M)＝NOT_EMPTY

C) information code element of continuous variable node is distributed to M _b-2 memories.Use MD _iThe degree of depth of representing i memory is used M _i ^jRepresent the i block storage, the address is a j place corresponding variable node.

t＝0

for i＝0 to M _b-2 do

for j＝0 to MD _i do

$M_i^j=t$

t＝t+1

end for

end for

(2), produce the position distribution of the non-empty matrix of variable node information code element part after the satisfied constraint at random.

When realizing the hardware of ldpc decoder, must satisfy following three constraints.

The memory of information node adopted dual-ported memory when a) hardware of ldpc decoder was realized, so each block storage allows to read simultaneously and write data at most.So each row of check matrix is divided in the submatrix of same block storage a non-NULL can only be arranged in the 1st step.

B) since hardware realize Min-Sum algorithm mentioned above may be in a plurality of clock cycle complete operation, the variable node information of reading from memory of next clock cycle will not be up-to-date information and cause convergence rate to descend, so clock cycle that will be required according to whole algorithm, and constrain in the information that reads certain variable node and in the time Mc of constraint, can not read the information of this variable node, so being separated by, each row of matrix should not have two non-empty matrix in the memory constraints number of cycles Mc.

C) can not be greater than d based on the LDPC decoding algorithm requirement row of layer scheduling to highest weighting _MaxSo the non-NULL matrix position of a certain row can not be greater than d in matrix _Max

So check matrix produces the non-NULL matrix position at random in variable node information code element part after satisfying above-mentioned three constraints, do not satisfy constraint and then generate at random again.Accompanying drawing 7 has been showed the matrix example that this step produced.Arthmetic statement is as follows, M _i(t, k) expression i block storage is capable corresponding to the t of matrix, the value of k row.

For t＝0 to R _M do

insert＝1

While insert do

Generate P randomly

If P∈M _i and M _i(t，)＝-1 then

For k＝i-1 to i-Mc do

If M _i(，k)≠-1 break

End for

If k＝i-Mc-1then

If ∑ M _i(，k)≤d _max then

Insert＝0

End if

End if

End if

End while

H(t，P)＝NOT_EMPTY

End for

3 variable information node section ranks exchange at random.

The present invention partly carries out the random column exchange to the information code element of the variable node of matrix, and all row are carried out the random row exchange.

Because the strong more then decoding performance of check matrix randomness of LPDC is good more, and the two steps operation of front causes decreased performance owing to hard-wired constraint makes matrix structureization, so the ranks that carry out at random exchange the performance that can promote decoding.For information code element (IN) part that exchange can the randomization variable node at random of row, can improve decoding performance to a certain extent even in the system that has, can omit corresponding interleaver to save area.Exchange can be so that the check code metamessage of variable node be distributed in information code element part as much as possible to row at random, and the decoding of each check-node subclass is similar to the decode procedure of an independent high code check like this.According to the constraint of first two steps, continuous information code element need be stored in the corresponding memory before the row exchanges, will note to be used for forming the relation of input symbols and corresponding memory so be listed as correspondence position before and after the exchange at random; Because, need decipher different layers successively in when decoding based on layer scheduling algorithm, the decoding convergence rate is the most obvious,, the front and back correspondence position of row exchange selects the different row decodings of advancing when forming each iteration so need noting.As shown in Figure 8.

4, produce data at random at the non-NULL matrix position, make that the average ring of whole matrix is maximum.

Because the Fourth Ring will cause the serious decline of performance,, make average ring at least more than six so must eliminate the Fourth Ring.The big more then decoding performance of the average ring of H matrix is good more, also can optimize decoding performance so seek maximum average number of rings under identical constraint.

This check matrix is owing to be constraint with the memory piecemeal with avoiding read/write conflict exactly when the design verification matrix, so can significantly reduce the memory block number, the decoder architecture of realization is very simple.Because the matrix design method that this paper proposes is to be listed as to weight limit d _MaxAs constraints, realize decoding so can adopt based on layer scheduling algorithm, therefore the convergence rate of decoding is very fast, and can adopt the hardware configuration shown in the accompanying drawing 3 to greatly reduce hardware complexity, and throughput improves 1 times nearly.Owing to during this paper design matrix, ranks are carried out at random exchange at random accordingly, make that the degree of randomization of matrix position is very high, and produce the submatrix data at random and seek maximum average ring, so decoding performance can improve greatly.

Description of drawings

The check matrix example of a simple LDPC sign indicating number of Fig. 1.

The Tanner figure of Fig. 2 check matrix correspondence shown in Figure 1.

Fig. 3 is based on the ldpc decoder structure of layer scheduling.

The ldpc decoder structure of the common dispatching algorithm of Fig. 4.

Three kinds of citation forms of Fig. 5 submatrix.

The stationary distribution of the piecemeal of Fig. 6 submatrix and check information part.

The capable layering of Fig. 7, row piecemeal non-NULL matrix position distributes.

Fig. 8 ranks are the distribution after the combination distribution at random.

Fig. 9 signal to noise ratio and Packet Error Ratio, the curve chart of the error rate.

Number in the figure: 1, memory based on storage of variables nodal information in the layer scheduling structure, 2, based on the switching network from the variable node to the check-node in the layer scheduling structure, 3, based on code check node processing unit in the layer scheduling structure, 4, based on layer scheduling structure middle controller, 5, FIFO based on variable information in the layer scheduling structure, 6, based on the code check node processing functional module in the layer scheduling structure, 7, based on the check-node information-storing device in the layer scheduling structure, 8, variable node processing unit in the common dispatching algorithm structure, 9, variable node processing unit in the common dispatching algorithm structure, 10, check-node information in the common dispatching algorithm structure is to the switching network of variable node information, 11, variable node information in the common dispatching algorithm structure is to the switching network of check-node information, 12, code check node processing unit in the common dispatching algorithm structure, 13, check node memory in the common dispatching algorithm structure.

Embodiment

To realize that code length is 1200, submatrix is 30 * 30 below, and code check is that 3/4 LDPC sign indicating number is that example describes:

Hard-wired constraints is: d _Max=4, M _b=10.

Shown in step 1 and accompanying drawing 6, matrix has 300 row, 1200 row, and wherein preceding 900 classify information code element as, and back 300 is classified the verification code element as.Every row divides 40 submatrixs, and preceding 30 belong to information code element, and back 10 belong to the verification code element.Whenever show 10 submatrixs.

Shown in step 2 and accompanying drawing 7, be followed successively by from the degree of depth of first block storage to the, eight block storages: 3444 44 44.The 9th and the tenth the degree of depth is 9.The submatrix information of the 30th variable node is because row are 3 to weight, thus can not be stored in the 9th and the tenth block storage, and store by the 8th block storage.

Shown in step 3 and accompanying drawing 8, establish the variable node renewal and only need one-period, under the condition that satisfies constraint, generate non-NULL submatrix distribution patterns at random.Row heavily is distributed as λ (x)=0.8x ¹⁰+ 0.2x ⁹Column weight distribution is ρ (x)=0.51x ²+ 0.48x ³+ 0.01x ⁴

Shown in step 4 and accompanying drawing 8, information code element partly carries out the random column conversion.The 1st, 2,3,4,6,7,8 row carry out the random row conversion.

Generation by Fig. 7 to the row corresponding relation of the variable node of Fig. 8 is:

28，10，3，2，15，9，1，19，5，12，17，23，6，24，13，21，14，0，16，26，4，

7，18，25，20，22，11，27，8，29，30。

Then the explanation: behind the rank transformation in Fig. 8 matrix the information of the submatrix position of the 28th, 10,3 in the variable node will store by M1, the 3rd, 2,15,9 submatrix information will be stored by M2, and the like.

Generation by Fig. 7 to the corresponding relation of the check-node of Fig. 8 is:

0，8，4，7，3，5，2，1，6，9。

Then select the above-mentioned row decoding of advancing successively by above-mentioned successively in when decoding.

Produce following check matrix at last and see Table 1, the displacement numerical value K of each numeric representation submatrix wherein represents empty matrix with-1,0 representation unit battle array)

Table 1

Line number	Data
		1	13，-1，-1，-1，0，26，-1，-1，-1，-1，-1，-1，-1，-1，-1，8，-1，-1，-1，-1，-1， -1，-1，-1，-1，25，25，-1，9，-1，10，0，-1，-1，-1，-1，-1，-1，-1，-1
2	-1，5，-1，-1，-1，-1，24，-1，-1，23，-1，-1，-1，5，-1，-1，-1，-1，17，-1，-1， -1，-1，2，23，-1，-1，6，-1，-1，-1，0，0，-1，-1，-1，-1，-1，-1，-1，
		3	15，-1，22，-1，1，-1，-1，-1，-1，-1，-1，19，-1，10，8，-1，3，-1，-1，-1，-1，-1 ，-1，-1，-1，-1，12，-1，-1，-1，-1，-1，0，0，-1，-1，-1，-1，-1，-1，
4	-1，-1，-1，22，-1，12，-1，-1，-1，-1，26，-1，21，16，8，-1，-1，-1，-1，-1， 6，-1，-1，-1，-1，23，-1，-1，-1，-1，-1，-1，-1，0，0，-1，-1，-1，-1，-1
		5	-1，-1，13，-1，-1，-1，-1，6，11，-1，21，24，-1，-1，-1，-1，-1，-1，-1，-1，28， -1，22，-1，-1，-1，29，-1，-1，-1，-1，-1，-1，-1，0，0，-1，-1，-1，-1
6	-1，-1，-1，-1，-1，-1，22，-1，-1，-1，-1，-1，-1，-1，-1，-1，-1，-1，8，4，-1， -1，-1，9，10，-1，-1，20，-1，7，0，-1，-1，-1，-1，0，0，-1，-1，-1
		7	-1，25，-1，-1，-1，-1，-1，-1，-1，4，0，-1，6，-1，-1，14，-1，9，-1，-1，-1，-1， -1，-1，9，-1，-1，-1，27，-1，-1，-1，-1，-1，-1，-1，0，0，-1，-1
8	-1，-1，-1，1，-1，22，-1，15，22，-1，-1，-1，-1，-1，-1，-1，-1，-1，-1，-1，0，1 5，21，-1，-1，15，-1，-1，-1，-1，-1，-1，-1，-1，-1，-1，-1，0，0，-1
		9	-1，-1，-1，29，-1，-1，-1，-1，-1，-1，-1，-1，19，-1，26，-1，12，13，-1，16，-1 ，5，-1，-1，-1，-1，-1，-1，-1，13，-1，-1，-1，-1，-1，-1，-1，-1，0，0
10	-1，-1，-1，-1，-1，-1，-1，-1，0，13，-1，-1，-1，-1，-1，-1，9，1，-1，-1，-1，23 ，-1，21，-1，-1，8，-1，-1，-1，10，-1，-1，-1，-1，-1，-1，-1，-1，0

When adopting above-mentioned matrix to decipher, adopt the LLR information of 5 bits input, variable node adopts 7 bit quantizations, bit error rate 1e ^-5The corresponding signal to noise ratio in place is 4.5db, sees the signal to noise ratio of accompanying drawing 9 and the curve of the error rate and Packet Error Ratio.

Claims (1)

1, a kind of low-density parity is counted the method for designing of check code matrix, it is characterized in that:

(1) fixed pattern of division of the memory piecemeal of matrix variables node and check information code element distributes

Information code element to variable node adopts different memory method of partitions with the verification code element, simultaneously in order to simplify the structure of encoder, the row weight is set to 2 and arrange two block storages in the verification code element of variable node, adopt fixed pattern to distribute in the check information node section, and submatrix K=0, the information code element part of variable node is by M _b-2 block storages are stored, and are stored in successively in each block storage from left to right;

(2) satisfy the position distribution that produces the non-empty matrix of node variable information code element part after the constraint at random, wherein said being constrained to:

1. each row of check matrix is divided in the first step in the submatrix of same block storage a non-NULL can only be arranged;

2. each row of check matrix are separated by and should not be had two non-empty matrix in the memory constraints number of cycles;

3. a certain row non-NULL matrix position size can not be greater than d in the check matrix _Max,

Wherein, d _MaxBe H rectangular array vector highest weighting;

(3) variable information node section ranks exchange at random

Information code element to the variable node of matrix partly carries out the random column exchange, and all row are carried out random row exchange; Continuous information code element is stored in the corresponding memory before the row exchanges, is listed as correspondence position before and after the exchange at random and will notes to be used for forming the relation of input symbols and corresponding memory; The front and back correspondence position of exchange of going is at random noted and is selected the different row decodings of advancing when forming each iteration;

(4) produce data at random at the non-NULL matrix position, make that the average ring of whole matrix is maximum.

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