WO2021063217A1

WO2021063217A1 - Decoding method and apparatus

Info

Publication number: WO2021063217A1
Application number: PCT/CN2020/116852
Authority: WO
Inventors: 马亮; 魏岳军; 梁璟
Original assignee: 华为技术有限公司
Priority date: 2019-09-30
Filing date: 2020-09-22
Publication date: 2021-04-08
Also published as: CN112583419A

Abstract

A decoding method and apparatus. The method comprises: acquiring an LLR sequence corresponding to a bit sequence to be decoded (401), wherein the LLR sequence comprises 2^w LLRs, the bit sequence is obtained by means of performing polar code encoding on a first bit sequence, and w is an integer greater than or equal to 1; determining an LDPC code check matrix corresponding to the bit sequence (402); on the basis of the LDPC code check matrix corresponding to the bit sequence, using an LDPC code decoder to decode the LLR sequence so as to obtain a first decoding result (403); according to the first decoding result, obtaining a decoding bit sequence (404). By using the described method, for a bit sequence to be decoded that is obtained by means of polar code encoding, the use of an LDPD code decoder to decode an LLR sequence corresponding to the bit sequence is enabled by means of determining an LDPC code check matrix corresponding to the bit sequence, thereby enabling polar code decoding and LDPC code decoding to achieve common mode decoding, and saving on hardware overheads.

Description

Decoding method and device

Cross-references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on September 30, 2019, the application number is 201910944426.5, and the application name is "a decoding method and device", the entire content of which is incorporated into this application by reference .

Technical field

This application relates to the field of communication technology, and in particular to a decoding method and device.

Background technique

The rapid evolution of wireless communication indicates that the fifth generation (5G) communication system in the future will show some new characteristics. The three most typical communication scenarios include enhanced mobile broadband (eMBB) and massive machine connections. Communication (massive machine type communication, mMTC) and high reliability and low latency communication (ultra reliable low latency communication, URLLC), the requirements of these communication scenarios will pose new challenges to existing long term evolution (LTE) technologies. As the most basic wireless access technology, channel coding is one of the important research objects to meet the needs of 5G communication.

Polar code is selected as the control channel coding method in the 5G standard. Polar code is the first and only known channel coding method that can be strictly proven to "reach" the channel capacity. Under different code lengths, Especially for limited codes, Polar codes have better performance. Low density parity check (LDPC) code is selected as the data channel coding method in the 5G standard. LDPC code is a linear block code with a sparse check matrix, which not only has the limit of Shannon (Shannon) Good performance, low decoding complexity and flexible structure.

Since the control channel and the data channel adopt different encoding methods, the information received by the control channel and the information received by the data channel need to be decoded separately, which leads to more complicated implementation and higher hardware overhead.

Summary of the invention

In view of this, the present application provides a decoding method and device for realizing common mode decoding of the information received by the control channel and the information received by the data channel, effectively reducing hardware overhead.

In the first aspect, an embodiment of the present application provides a decoding method, the method includes: obtaining a log-likelihood ratio LLR sequence corresponding to a bit sequence to be decoded, the LLR sequence includes 2 ^w LLRs, and the to-be-translated bit sequence The code bit sequence is obtained by encoding a first bit sequence with a polarization code, the first bit sequence includes information bits; w is an integer greater than or equal to 1, and the low density corresponding to the bit sequence to be decoded is determined Parity check LDPC code check matrix; decode the LLR sequence based on the LDPC code check matrix to obtain a first decoding result; obtain a decoded bit sequence according to the first decoding result.

Using the above method, for the bit sequence to be decoded obtained by polarization code encoding, by determining the LDPC code check matrix corresponding to the bit sequence to be decoded, the LLR sequence corresponding to the bit sequence to be decoded can be used by the LDPC code decoder Perform decoding, so that polarization code decoding and LDPC code decoding can achieve common mode decoding, saving hardware overhead.

In a possible design, decoding the LLR sequence based on the LDPC code check matrix to obtain the first decoding result includes: using an LDPC code layered decoder based on the LDPC code check matrix Decoding the LLR sequence to obtain the first decoding result.

In this way, the LDPC code layered decoding method can improve the decoding performance and reduce the probability of decoding errors.

In a possible design, obtaining the decoded bit sequence according to the first decoding result includes: using a polarization code decoder to decode the first decoding result to obtain the decoded bit sequence .

Using the above method, since the LDPC code decoder is used to decode the LLR sequence to obtain the first decoding result, it is only necessary to use the polarization code decoder to decode the first decoding result. In the prior art using a polarization code decoder to decode the LLR sequence corresponding to the bit sequence to be decoded, the complexity of the polarization code decoder required in the embodiment of the present application can be much less than that of the existing one. The complexity of the polarization code decoder in the technology can effectively reduce the hardware overhead.

In a possible design, determining the LDPC code check matrix corresponding to the bit sequence to be decoded includes: determining a polarization code factor graph corresponding to the bit sequence to be decoded, where the polarization code factor graph includes 2 ^w *(w+1) nodes; determine the LDPC code Tanner graph according to the check relationship between different nodes in the polarization code factor graph, and the Tanner graph includes 2 ^k *(k+1) Variable nodes and 2 ^k * k check nodes, each of the variable nodes corresponds to 2 ^p nodes in the polarization code factor graph, k is an integer greater than or equal to 1, and p is an integer greater than or equal to 0 , W=p+k; the LDPC code check matrix corresponding to the bit sequence to be decoded is determined according to ^{the 2 k} *(k+1) variable nodes and the 2 ^{k *k check nodes.}

In this way, by analyzing the check relationship between different nodes in the polarization code factor graph, the polarization code factor graph can be deformed to obtain the LDPC code Tanner graph, and then the LDPC code check matrix corresponding to the bit sequence to be decoded can be obtained.

In a possible design, determining the LDPC code check matrix corresponding to the bit sequence to be decoded ^{according to the 2 k} *(k+1) variable nodes and 2 ^{k *k check nodes includes:} The 2 ^k * (k + 1) variable nodes and 2 ^k * k check nodes determine a first check matrix; perform one or more of the following operations on the first check matrix to obtain the LDPC code Check matrix: row swap, column swap, row merge, column merge, row delete, column delete.

In this way, by performing the above operations on the first check matrix, the obtained LDPC code check matrix conforms to the polarization code decoding method and has serial characteristics in the decoding process, so as to facilitate the use of the LDPC code layered decoding method. Decoding to improve decoding performance.

In a possible design, the LDPC code check matrix corresponding to the bit sequence to be decoded is a quasi-cyclic QC-LDPC code check matrix.

In a possible design, the determined LDPC code check matrix is:

Wherein, the LDPC code check matrix includes a first layer and a second layer, the first layer includes a first row, and the second layer includes a second row.

In a possible design, the w is an integer greater than or equal to 2; the determined LDPC code check matrix is:

Wherein, the LDPC code check matrix includes a first layer, a second layer and a third layer, the first layer includes a first row and a second row, and the second layer includes a third row and a fourth row, The third layer includes a fifth row and a sixth row.

In a possible design, w is an integer greater than or equal to 3; the determined LDPC code check matrix is:

Wherein, the LDPC code check matrix includes a first layer, a second layer, a third layer, and a fourth layer, the first layer includes the first row to the fourth row, and the second layer includes the fifth row to the fourth layer. Eight rows, the third layer includes the ninth row to the twelfth row, and the fourth layer includes the thirteenth row to the sixteenth row.

In a possible design, w is an integer greater than or equal to 4; the determined LDPC code check matrix is:

Wherein, the LDPC code check matrix includes the first layer to the fifth layer, the first layer includes the first row to the eighth row, the second layer includes the ninth row to the sixteenth row, and the first layer includes the ninth row to the sixteenth row. The third layer includes the seventeenth row to the twenty-fourth row, the fourth layer includes the twenty-fifth row to the thirty-second row, and the fifth layer includes the thirty-third row to the fortieth row.

In a second aspect, the present application provides a decoding device, which has the function of implementing the method described in the first aspect and any one of the possible designs of the first aspect. The function can be realized by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above-mentioned functions.

In a possible design, when part or all of the functions are realized by hardware, the decoding device includes: an input interface circuit for obtaining the LLR sequence corresponding to the bit sequence to be decoded; and a logic circuit for executing The method described in the first aspect and any one of the possible designs of the first aspect; an output interface circuit for outputting a decoded bit sequence.

Optionally, the decoding device may be a chip or an integrated circuit.

In a possible design, when part or all of the function is realized by software, the decoding device includes: a memory for storing a program; a processor for executing the program stored in the memory, when When the program is executed, the decoding device can implement the method described in any one of the foregoing first aspect and the first aspect.

Optionally, the foregoing memory may be a physically independent unit, or may be integrated with the processor.

In a possible design, when part or all of the functions are implemented by software, the decoding device includes a processor. The memory for storing the program is located outside the decoding device, and the processor is connected to the memory through a circuit/wire for reading and executing the program stored in the memory.

In a third aspect, an embodiment of the present application provides a communication system. The communication system includes a network device and a terminal device. Both the network device and the terminal device can perform any of the above-mentioned first aspect or any one of the first aspects. The method described in the design.

In a fourth aspect, an embodiment of the present application provides a computer storage medium storing a computer program, and the computer program includes instructions for executing the method described in the first aspect or any one of the possible designs of the first aspect.

In a fifth aspect, a computer program product containing instructions is provided, which when running on a computer, causes the computer to execute the method described in the first aspect or any one of the possible designs of the first aspect.

Description of the drawings

FIG. 1a is a schematic diagram of a polarization channel unit provided by an embodiment of the application;

FIG. 1b is an example of a polarization code factor diagram (8 LLRs) provided by an embodiment of the application;

FIG. 1c is a schematic diagram of the SC decoding calculation process provided by an embodiment of the application;

FIG. 1d is a schematic diagram of a decoding path in the SCL decoding method provided by an embodiment of this application;

Figure 1e is a schematic diagram of a decoding calculation process provided by an embodiment of the application;

Figure 1f is an example of a Tanner graph of an LDPC code provided by an embodiment of the application;

FIG. 2 is a schematic diagram of a network architecture to which an embodiment of this application is applicable;

FIG. 3a is a schematic diagram of a polarization code encoding and decoding process provided by an embodiment of the application;

FIG. 3b is a schematic diagram of the need to separately decode the information received by the control channel and the information received by the data channel according to an embodiment of the application;

3c is a schematic diagram of common mode decoding of information received by a control channel and information received by a data channel using the decoding method provided by an embodiment of the present application;

FIG. 4 is a schematic flowchart corresponding to the decoding method provided by an embodiment of this application;

FIG. 5a is a schematic diagram of updating multiple layers of the LDPC check matrix in an iterative process;

Fig. 5b is a Tanner graph obtained according to the factor graph shown in Fig. 1b;

FIG. 5c is an example of a polarization code factor diagram (16 LLRs) provided by an embodiment of the application;

FIG. 5d is an example of a Tanner diagram corresponding to a 2*2 polarization code butterfly network unit provided by an embodiment of the application;

Fig. 6 is a logical schematic diagram of a decoding process provided by an embodiment of the application;

Fig. 7 is a schematic diagram of the SCL decoder shown in Fig. 6;

FIG. 8 is a possible exemplary block diagram of a device involved in an embodiment of this application;

FIG. 9 is a schematic structural diagram of a decoding device provided by an embodiment of this application;

FIG. 10 is a schematic structural diagram of another decoding device provided by an embodiment of this application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

First, the polarization code, polarization code decoding, and LDPC code and LDPC code decoding involved in the embodiments of the present application are introduced.

(1) Encoding of polarization codes

The coding strategy of the polarization code uses the noise-free channel to transmit useful information for the user, and the all-noise channel transmits the agreed information or does not transmit information. Polarization code is a linear block code, its generator matrix is G _N , and its encoding process is

Is a binary row vector with length N (ie code length); and

Here

B _N is an N×N transposed matrix, such as a bit reverse transposed matrix; among them, B _N is an optional quantity, and the calculation process of _{generating the matrix G N} can omit the calculation of _{B N.}

Defined as the Kronecker product _{of log 2} N matrices F _2,

Are the encoded bits (also called codewords),

After multiplying with the generator matrix G _N , the encoded bits are obtained, and the multiplication process is the encoding process.

During the encoding process of the polarization code,

A part of the bits are used to carry information, which is called a set of information bits.

The other part of the bits is set to a fixed value agreed by the receiving end and the sending end in advance, which is called a fixed bit set or frozen bit set (frozen bits), and the set of indexes is used

Complement

Said. The encoding process of the polarization code is equivalent to:

Here,

Is the set _{of G N}

The sub-matrix obtained by the rows corresponding to the index in,

Is the set _{of G N}

The index corresponding to those rows in the sub-matrix.

for

The set of information bits in, the number is K;

for

The fixed bit set in, whose number is (NK), is a known bit. These fixed bits are usually set to 0, but as long as the receiving end and the sending end agree in advance, the fixed bits can be set arbitrarily. Therefore, the encoding output of the polarization code can be simplified as:

(2) Decoding of polarization codes

There are many decoding methods for polarization codes, such as serial cancellation (successive cancellation, SC) decoding method, serial cancellation list (successive cancellation list, SCL) decoding method, and probability propagation (belief propagation, BP) decoding method. Code method. The various decoding methods of the polarization code can be calculated based on the butterfly network of the polarization code (also known as the factor graph). The structure of the factor graph is related to the structure of the polarization code. For example, the graph 1a is a schematic diagram of a polarized channel unit, u ₁ u ₂ is the input, and the encoded x ₁ x ₂ can be written as

x ₁ = u ₁ + u ₂

x ₂ = u ₂

Among them, "+" means modulo 2 plus.

After the operation of the polarization unit as shown in the figure above, two new channels (W1 and W2) are obtained. The channel capacity of one channel decreases, and the channel capacity of the other channel increases. Therefore, as long as the polarization unit is repeatedly and iteratively called, the channel capacity of some channels can be theoretically close to 1, and the channel capacity of another part of the channels can be close to 0, as long as the channel capacity is close to 1. Information bits, place known bits (freeze bits) on the channel whose channel capacity is close to 0, theoretically, error-free transmission can be realized. The polarized unit network after repeated cascading can be called a butterfly network or a factor graph. As shown in Figure 1b, the LLR sequence includes 2 ³ = 8 LLRs, namely LLR0, LLR1, LLR2, LLR3, LLR4, LLR5, LLR6, LLR7, the factor graph contains 3+1=4 layers (respectively layer0, layer1, layer2, layer3), each layer includes 2 ³ nodes, a total of 2 ³ (3+1)=32 nodes ( The gray circle shown in the figure), each intersecting unit in the figure represents a polarization unit shown in Fig. 1a.

Among them, the SC decoding method refers to calculating the LLR of each decoding bit one by one according to the LLR sequence corresponding to the bit sequence to be decoded, and making a bit-by-bit decision. When the decoded bit is an information bit, if the LLR of the decoded bit>0, then the decoded bit is 0, if the LLR of the decoded bit<0, then the decoded bit is 1; when the decoded bit is a fixed bit When, no matter what the LLR is, the decoding result is set to 0. Figure 1c is a schematic diagram of the SC decoding calculation process. Taking 4 decoding bits as an example, there are 8 calculation nodes in Figure 1c, of which there are 4 F nodes, 4 G nodes, F and G nodes respectively correspond to F operations Calculate with G. The operation of the F node requires the 2 LLR inputs on the right side, and the operation of the G node requires the 2 LLR inputs on the right side and the output of the previous stage as inputs. The output can only be calculated after the input items are calculated.

Among them, F operation adopts simplified operation, and the formula of F operation is:

F(a,b)=sign(a)sign(b)min(|a|,|b|);

G operation adopts simplified operation, and the formula of G operation is:

According to the above calculation rules, starting from the right in Figure 1c, the decoded bits obtained by sequential calculation are ①→②→③→④, and the decoding is completed.

The SCL decoding method means that according to the LLR sequence corresponding to the bit sequence to be decoded, when decoding each information bit, the decoding results corresponding to 0 and 1 are saved as two branch decoding paths (referred to as path splitting). Figure 1d is a schematic diagram of the decoding path in the SCL decoding method. As shown in Figure 1d, each layer represents 1 decoding bit. If the decoding result is 0, it follows the left subtree development path. If the decoding result If the value is 1, the path is developed along the right subtree. When the total number of decoding paths exceeds the preset path width L (usually L=2, 4, 8, 16 or 32), the path metric (PM) is selected. The L paths with the best value of) are saved and the paths are continued to be developed to interpret the subsequent decoded bits. The PM value among them is used to judge the quality of the path, and the PM value is calculated by LLR. For each level of decoding bits, sort the PM values of the L paths from small to large, and filter the correct paths through the PM value, and repeat until the last bit is decoded.

Next, the decoding operation will be introduced in conjunction with Figure 1e. As shown in Figure 1e, the right side is the LLR input side, or called the codeword side; the left side is the information side, or called the decoding bit side. _yi is the information to be decoded, and u _i is the decoded bit. From the beginning of decoding, the levels are s=4, s=3, s=2, s=1, and s=0 in sequence. Assuming that the length of the information to be decoded is N=16, if the SCL decoding method is adopted, at the level of s=4, the 16 LLRs corresponding to the information to be decoded are subjected to F/G operation, and the information on the level of s=3 is obtained. 8 LLRs. Then the 8 LLRs on the level of s=3 continue to perform F/G operations, and 4 LLRs on the level of s=2 are obtained, and the 4 LLRs on the level of s=2 continue to perform F/G operations, and s= The two LLRs on the level of 1, and the two LLRs on the level of s=1 continue the F/G operation to obtain one LLR on the level of s=0, and the path is split bit by bit on the level of s=0. At the beginning of decoding, the LLR is read in from the codeword side, and the probability is passed to obtain the LLR value of the first decoded bit. The LLR value is judged to obtain the decoded result of the first decoded bit. The decision bit value of the decoded bit is used as the input of the second decoded bit, and the calculation of the second decoded bit is performed until all the decoded bits on the s=0 level are calculated. The decoded bits include fixed bits and information bits. The fixed bit position has a decision bit value of 0 regardless of the LLR; the decision bit value of the information bit position can have two types, 0 and 1, so it can be split into two paths.

The BP decoding method refers to the butterfly network architecture based on the polarization code. It uses the confidence propagation formula to decode all input LLRs of the polarization code in parallel, and achieves high parallelism decoding through multiple iterations to convergence.

(3) LDPC code check matrix

The LDPC code is a linear block code, which is determined by a sparse matrix H with m rows and n columns, where H is composed of

elements

0 and 1. Since most of the elements in the matrix are 0, except for a few elements, which are 1, Called sparse matrix, sparse matrix H can also be called LDPC code check matrix. H satisfies the following conditions: row weight (number of 1 in each row), column weight (number of 1 in each column) and code length The ratio of is far less than 1; any two rows (columns) have at most one 1 at the same position; the number of any linearly independent columns should be as large as possible.

Quasi-cycle (QC)-LDPC codes are a subclass of LDPC codes, and their check matrix H has a cyclic characteristic. The QC-LDPC code check matrix H can usually be expressed as the following array:

Among them, each matrix A _{i, j} is a circulant matrix of size Z×Z. If the number of rows and columns of the check matrix H are denoted as M=ρZ and N=cZ, respectively, the packet length of the information sequence to be transmitted is K=NM. The sending end needs to use a check matrix to encode the information sequence group to be transmitted, and the receiving end also needs to decode based on the check matrix. The design process of QC-LDPC codes involves three important concepts: circular permutation matrix (CPM), base graph and base matrix.

There are many ways to construct the check matrix of QC-LDPC codes. One possible way to construct the check matrix of quasi-cyclic LDPC codes is: first construct a base matrix B of size ρ×c, for example:

The fundamental pattern of the QC-LDPC code is a matrix with the same size as the base matrix, and the element is not 0 or 1: "1" means that the shift value of the corresponding position of the base matrix is not equal to -1; "0" means the corresponding position of the base matrix The shift value of is -1. For example, the base model diagram of the base matrix in the above example is:

Then, each non-"-1" element in the base matrix B is expanded into a cyclic permutation matrix of size Z×Z, and the "-1" element is expanded into an all-zero matrix of size Z×Z. Assuming P ⁱ × Z represents a cyclic permutation matrix Z, also referred to as a sub-base matrix circulant matrices, i of P ⁱ is referred to as the shift value. E.g:

Take Z=8 as an example:

It can be seen that P ⁰ is the unit matrix, and each cyclic permutation matrix P ^{i is} actually obtained by cyclically shifting the unit matrix by i bits to the right. Furthermore, for a given Z, Z a total of P ^i, i.e. i∈ {0,1,2, .., Z- 1}. Each P ⁱ (0≤i <Z) for the base matrix B to expand the value of element i.

In this way, according to different code rates, different parts of the base matrix B can be intercepted and expanded into the corresponding check matrix. Among them, a check matrix of (ρZ)×(cZ) can be obtained at most; thus, according to the different check matrices obtained, Encode and decode the information sequence to be transmitted under different code rates.

(4) Tanner diagram

The LDPC code check matrix can be defined by the Tanner graph corresponding to the LDPC code check matrix. For example, an example of an LDPC code check matrix and its corresponding check equation is:

Among them, "+" means modulo 2 plus.

The Tanner graph corresponding to the check matrix can be represented as shown in Figure 1f. Each circular node in Figure 1f is a variable node, representing a column in the check matrix H, and each square node is a check node, representing a check In a row of the matrix H, each edge connecting the check node and the variable node in Fig. 1f represents that there is a non-zero element at the intersection of the row and the column corresponding to the two nodes.

(5) The various numerical numbers such as first and second involved in the embodiments of the present application are only for easy distinction for description, and are not used to limit the scope of the embodiments of the present application, and do not indicate a sequence. "And/or" describes the association relationship of the associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone. "At least one" means one or more. At least two refers to two or more. "At least one" or similar expressions refers to any combination of these items, including any combination of single item (a) or plural items (a). For example, at least one of a, b, or c (a, kind) can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple A.

And, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects, and are not used to limit the order, timing, priority, or importance of multiple objects. degree.

Figure 2 is a schematic diagram of a network architecture to which an embodiment of the application is applicable. The network architecture may include at least one network device 100 (only one is shown) and one or more terminal devices 200 connected to the network device 100.

The network device 100 may be a device that can communicate with the terminal device 200. The network device 100 may be any device with a wireless transceiving function. Including but not limited to: base stations (for example, base station NodeB, evolved base station eNodeB, base stations in the fifth generation (5G) communication system, base stations or network equipment in future communication systems, and access nodes in WiFi systems , Wireless relay node, wireless backhaul node), etc. The network device 100 may also be a wireless controller in a cloud radio access network (cloud radio access network, CRAN) scenario. The network device 100 may also be a small station, a transmission reference point (TRP), and so on. Of course, the application is not limited to this.

The terminal device 200 is a device with wireless transceiver function that can be deployed on land, including indoor or outdoor, handheld, wearable or vehicle-mounted; it can also be deployed on water (such as ships, etc.); it can also be deployed in the air (such as airplanes, airplanes, etc.). Balloons and satellites are classy). The terminal equipment may be a mobile phone (mobile phone), a tablet computer (Pad), a computer with wireless transceiver function, virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, industrial control ( Wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grid, and transportation safety Wireless terminals, wireless terminals in smart cities, wireless terminals in smart homes, and so on. The embodiments of this application do not limit the application scenarios. Terminal equipment can sometimes be referred to as user equipment (UE), access terminal equipment, UE unit, UE station, mobile station, mobile station, remote station, remote terminal equipment, mobile equipment, UE terminal equipment, terminal equipment, Wireless communication equipment, UE agent or UE device, etc.

It should be noted that the network architecture illustrated above can be applied to communication systems of various wireless access technologies, for example, 5G communication systems and other possible communication systems.

The system architecture and business scenarios described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. Those of ordinary skill in the art will know that with communication With the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

In the network architecture shown in Figure 2, in order to combat interference in information transmission, the sending end device (such as the network device 100) can encode the information bits (such as polarization code encoding or LDPC code encoding); accordingly, the receiving end The device (such as the terminal device 200) can perform decoding (if the transmitting end device uses polarization code encoding, the receiving end device performs polarization code decoding; if the transmitting end device uses LDPC code encoding, the receiving end device performs LDPC code decoding Code) to get information bits. Exemplarily, taking the polarization code encoding and decoding as an example, the polarization code encoding and decoding process involved in the communication process between the transmitting end device and the receiving end device is shown in FIG. 3a, including: step 301, the transmitting end device obtains the encoded input bits Sequence (a bit sequence input for coding), the coding input bit sequence can include information bits and fixed bits. Step 302: The sender device performs verification (for example, cyclic redundancy check (CRC)) encoding to obtain a verification codeword. Step 303: The sending end device performs an interleaving operation on the check coded codeword. Step 304: The transmitting end device performs polarization code encoding on the check code word after the interleaving operation to obtain a bit sequence output for coding. Step 305: The transmitting end device maps the coded output bit sequence into modulation symbols, and processes and sends the coded output bit sequence through the channel. Step 306: The receiving end device obtains the LLR sequence corresponding to the bit sequence to be decoded, where the LLR sequence includes multiple LLRs. In step 307, the receiving end device performs polarization code decoding according to the LLR sequence. Step 308: The receiving end device performs a de-interleaving operation on the decoded sequence. Step 309: The receiving end device judges whether the decoding result is successfully decoded through the CRC check. It should be noted that Figure 3a is only a simple example. In specific implementation, other possible steps can be added to Figure 3a, such as radio network temporary identity (RNTI) scrambling and rate matching. , Descrambling, de-rate matching, etc., which are not specifically limited.

Taking a 5G communication system as an example, the network device 100 and the terminal device 200 may transmit control information through a control channel, and may transmit data information through a data channel. Taking the network device 100 as the transmitting end device and the terminal device 200 as the receiving end device as an example, the control channel can be a physical downlink control channel (PDCCH). For example, the network device 100 can send to the terminal device 200 through the PDCCH Downlink control information (downlink control information, DCI); the data channel may be a physical downlink shared channel (PDSCH), for example, the network device 100 may send data information to the terminal device 200 through the PDSCH.

However, since the control channel and the data channel use different encoding methods, for example, the control channel adopts the polar code encoding method, and the data channel adopts the LDPC code encoding method. Therefore, the receiving end device (such as the terminal device 200) responds to the information received by the control channel. The information received from the data channel and the data channel need to be decoded separately. As shown in Fig. 3b, the terminal device 200 inputs the information received from the control channel to the polarization code decoder for decoding to obtain the decoding result 1, and the data The information received by the channel is input to the LDPC code decoder for decoding to obtain the decoding result 2. Since the polarization code decoder and the LDPC decoder respectively correspond to different hardware structures, the hardware overhead is relatively high and the cost is relatively high. Similarly, when the terminal device 200 is used as the transmitting end device and the network device 100 is used as the receiving end device, the same problem exists.

Based on this, the embodiments of the present application provide a decoding method for realizing common mode decoding of the information received by the control channel and the information received by the data channel, thereby effectively reducing hardware overhead. Exemplarily, the method deforms the polarization code factor graph corresponding to the bit sequence to be decoded to have a structure similar to the LDPC code check matrix, so that the LDPC code decoder can be used to decode the bit sequence corresponding to the bit sequence. The LLR sequence is decoded. Using this method, as shown in Figure 3c, the receiving end device (such as the terminal device 200) can input the information received from the control channel into the LDPC code decoder for decoding to obtain the decoding result 3, and then based on the decoding result 3. Obtain the decoding result 1 (for example, input the decoding result 3 into the polarization code decoder to obtain the decoding result 1), and input the information received from the data channel into the LDPC code decoder for decoding to obtain the decoding Result 2. Since the LDPC code decoder is used to decode the LLR sequence, the structural complexity of the polar code decoder in Fig. 3c can be less than that of the polar code decoder in Fig. 3b, thereby reducing the hardware Overhead.

It should be noted that the decoding method provided by the embodiments of the present application may be executed by the receiving end device or a chip set in the receiving end device, where the receiving end device may be the network device 100 shown in FIG. 2, or also It may be the terminal device 200 illustrated in FIG. 2.

FIG. 4 is a schematic diagram of a process corresponding to the decoding method provided by an embodiment of the application. The following describes the method executed by the receiving end device as an example. As shown in Fig. 4, the method includes:

Step 401: Obtain a log-likelihood ratio LLR sequence corresponding to the bit sequence to be decoded. The LLR sequence may include 2 ^w LLRs.

Exemplarily, the bit sequence to be decoded is obtained by encoding a first bit sequence with a polarization code. The first bit sequence is the bit sequence to be encoded as shown in FIG. 3a, and the first bit sequence may include information bits. , Can also include frozen bits.

In the embodiment of this application, the bit sequence to be decoded may include 2 ^w bits to be decoded (the bits to be decoded may include information bits to be decoded and frozen bits to be decoded), and 2 ^w bits to be decoded Each bit to be decoded in corresponds to an LLR.

Exemplarily, the receiving end device may calculate the LLR corresponding to each bit to be decoded according to the noise variance of the channel. In an example, the LLR corresponding to the bit to be decoded can be calculated by the following formula:

Among them, t represents the bit to be decoded, LLR(t) represents the LLR corresponding to the bit to be decoded, p(t|0) represents the probability that the bit to be decoded is 0, and p(t|1) represents the bit to be decoded The probability that the bit value is 1, and σ represents the noise variance of the channel.

For example, 2 ^w = 4, the 4 bits to be decoded are t ₁ , t ₂ , t ₃ , t ₄ , and the LLRs of the 4 bits to be decoded are: LLR(t ₁ )=1.5, LLR( t ₂ )=2, LLR(t ₃ )=-1, LLR(t ₃ )=-3. In this way, the LLR sequence is [1.5, 2, -1, -3].

Incidentally, 2 ^w can be understood as the length of the mother code of polarization, if the transmission side apparatus is not performed when the transmission rate matching bit sequence, the receiver device may receive from the transmitting side apparatus 2 ^w th bits to be decoded ; If the sending end device performs rate matching (such as puncturing and/or shortening) when sending the bit sequence, the receiving end device can receive N'from the sending end device (N' can be less than 2 ^{The value of w} is not specifically limited) bits to be decoded, and the rate matching is performed according to the N'bits to be decoded to obtain 2 ^w bits to be decoded. In other words, the above 2 ^w LLRs may include LLRs corresponding to punctured and/or truncated bits.

Step 402: Determine the LDPC code check matrix corresponding to the bit sequence to be decoded.

Here, the LDPC code check matrix corresponding to the bit sequence to be decoded is the first check matrix described below or the target LDPC code check matrix, where the target LDPC code check matrix is performed on the first check matrix One or more of the following operations: row swap, column swap, row merge, column merge, row delete, column delete. In the embodiment of the present application, the LDPC code check matrix corresponding to the bit sequence to be decoded is taken as the target LDPC code check matrix as an example for description.

Step 403: Use an LDPC code decoder to decode the LLR sequence based on the LDPC code check matrix corresponding to the bit sequence to be decoded to obtain a first decoding result.

Exemplarily, the LDPC code decoder may be an LDPC code hierarchical decoder or other possible LDPC code decoders (may be referred to as an LDPC code non-hierarchical decoder), which is not specifically limited. For example, when the LDPC code check matrix corresponding to the bit sequence to be decoded is the first check matrix described below, an LDPC code non-hierarchical decoder can be used; when the LDPC code check matrix corresponding to the bit sequence to be decoded When it is the target LDPC code check matrix, the LDPC code layered decoder can be used. Using the LDPC layered decoder, the target LDPC check matrix can be divided into multiple layers according to rows. During each iteration, the rows in each layer can be updated in parallel, and the rows in different layers can be updated serially, as shown in Figure 5a. Show. Among them, parallel update refers to the check node update and variable node update of all check formulas in the specified range at the same time; serial update refers to the check node of the check formulas in the specified range in the order of the check formulas in the specified range. Update and update of variable nodes. Using LDPC code layered decoding method can improve decoding performance and reduce the probability of decoding errors.

Step 404: Obtain a decoded bit sequence according to the first decoding result.

Exemplarily, a polarization code decoder is used to decode the first decoding result to obtain a decoded bit sequence. Among them, the first decoding result can be understood as the soft values output by the LDPC code decoder (that is, the LLR sequence decoded by the LDPC decoder), and these soft values are input into the polar code decoder for further decoding. In turn, the decoded bit sequence is obtained.

Further, the process of decoding through the LDPC code decoder and the polarization code decoder can be an iterative process, for example, the LLR sequence corresponding to the bit sequence to be decoded is input into the LDPC code decoder, LDPC code decoder Output the decoded result a1; input the decoded result a1 into the polarization code decoder, and the polarization code decoder outputs the decoded result b1; input the decoded result b1 into the LDPC code decoder, and the LDPC code decoder outputs the decoded result Code result a2; input the decoding result a2 into the polarization code decoder, and the polarization code decoder outputs the decoding result b2; and so on, after multiple iterations, the polarization code decoder can output the decoded bits sequence. Wherein, the number of iterations may be related to the number of LLRs in the LLR sequence corresponding to the bit sequence to be decoded. It can be seen that in communication devices that include both an LDPC code decoder and a polar code decoder (such as network equipment and terminal equipment in a 5G communication system), most of the decoding operations of the polar code can pass LDPC The decoder is implemented, so that the complexity of the polarization code decoder is greatly reduced.

In the embodiment of the present application, for the bit sequence to be decoded obtained by polarization code encoding, by determining the LDPC code check matrix corresponding to the bit sequence to be decoded, the LDPC code decoder can be used to decode the bit sequence corresponding to the bit sequence to be decoded. The LLR sequence is decoded, so that the polarization code decoding and the LDPC code decoding can achieve common mode decoding; further, because the LDPC code decoder is used to decode the LLR sequence to obtain the first decoding result, so , You only need to use the polarization code decoder to decode the first decoding result, that is, most of the decoding operations of the polarization code can be realized by the LDPC decoder, which is compared with the polarization code used in the prior art. For the code decoder to decode the LLR sequence corresponding to the bit sequence to be decoded, the complexity of the polar code decoder required in the embodiment of the present application can be much less than that of the polar code decoder in the prior art , Which can effectively reduce hardware overhead.

Exemplarily, in the foregoing step 402, there may be multiple implementation manners for the receiving end device to determine the target LDPC code check matrix corresponding to the bit sequence to be decoded. For example, in a possible implementation manner, multiple polarization code factor graphs can be deformed in advance through the process of determining the target LDPC code check matrix described below to obtain multiple LDPC code check matrices, and store them in In the storage medium accessible to the receiving end device, in step 402, the receiving end device can determine the target LDPC code check matrix from the multiple LDPC code check matrices according to the number of LLRs included in the LLR sequence, and further It is also possible to determine the target LDPC code check matrix according to the number of nodes in the polarization code factor graph corresponding to a variable node in the Tanner graph. For example, the number of LLRs is 16, and one variable in the Tanner graph The number of nodes in the polarization code factor graph corresponding to the node is 2, and then it can be determined that the target LDPC code check matrix is the target LDPC code check matrix shown in Example 3 below. In another possible implementation manner, in step 402, the receiving end device may also determine the target LDPC code check matrix according to the number of LLRs included in the LLR sequence through the process of determining the target LDPC code check matrix described below. Censor matrix.

The process of determining the target LDPC code check matrix will be described in detail below.

In the embodiment of the present application, the receiving end device can obtain the polarization code factor graph corresponding to the bit sequence to be decoded according to the number of LLRs in the LLR sequence, and then according to the check relationship between different nodes in the polarization code factor graph, Determine the LDPC code Tanner graph, and determine the first check matrix according to the LDPC code Tanner graph, and then obtain the target LDPC code check matrix according to the first check matrix. It can be seen that the process of determining the target LDPC code check matrix includes two parts: (1) determining the first check matrix; (2) obtaining the target LDPC code check matrix according to the first check matrix. The two parts are described separately below.

(1) Determine the first check matrix

Exemplarily, when the LLR sequence includes 2 ^w LLRs, the obtained polarization code factor graph may include w+1 layers, each layer includes 2 ^w nodes, and thus a total of 2 ^w (w+1) nodes. For example, the number of LLRs in the LLR sequence is 4 (w=2 at this time), the corresponding factor graph includes 3 layers, and a total of 12 nodes; for example, the number of LLRs in the LLR sequence is 8 (w= 3), the corresponding factor graph includes 4 layers, a total of 32 nodes; for example, the number of LLRs in the LLR sequence is 16 (w=4 at this time), then the corresponding factor graph includes 5 layers, a total of 80 Nodes.

The variable nodes in the Tanner graph can be determined according to the nodes in the factor graph. For example, a variable node in the Tanner graph can correspond to 2 ^p (p is an integer greater than or equal to 0) nodes in the factor graph. When p is equal to 0, a variable node in the Tanner graph can correspond to a node in the factor graph, that is, each node in the factor graph can be regarded as a variable node in the Tanner graph; when p is greater than 0 (for example, p = 1) One variable node in the Tanner graph can correspond to two nodes in the factor graph, that is, every two nodes in the factor graph can be regarded as a variable node in the Tanner graph.

In an example of this implementation (Example 1), a variable node in the Tanner graph can correspond to a node in the factor graph. See the factor graph shown in Figure 1b. The factor graph includes a total of 32 nodes. The Tanner graph includes 32 variable nodes. There is a certain check relationship between different nodes in the factor graph, such as x ₀ + x ₄ = x ₅ , and then x ₀ + x ₄ + x ₅ = 0, where x ₀ represents node 0 and x ₄ represents Node 4 and x ₅ represent node 5. Therefore, if node 0 corresponds to variable node 0 in the Tanner graph, node 4 corresponds to variable node 4, and node 5 corresponds to variable node 5, variable node 0, variable node 4, and variable node 5 can be Connect with the same check node (for example, check node 0). Furthermore, based on the check relationship between different nodes in the factor graph, a Tanner graph as shown in Figure 5b can be obtained. In Figure 5b, the circular node is the variable node in the Tanner graph, and the square node is the check node in the Tanner graph. Then write the Tanner graph in the form of a base model graph, as shown below:

Further, the first check matrix (referred to as LDPC code check matrix 1 for ease of description) is obtained according to the above-mentioned base model graph, as shown below:

Each row of the LDPC code check matrix 1 obtained above is in the order from top to bottom, corresponding to each square node in the Tanner graph shown in Fig. 5b in the order from right to left and from top to bottom, for example, LDPC code The first row in the check matrix 1 corresponds to the square node at the upper right corner of the Tanner graph (that is, check node 0). Each column of the LDPC code check matrix 1 obtained above is in the order from left to right, corresponding to each circular node in the Tanner graph shown in Figure 5b from right to left and from top to bottom, for example, LDPC code The first column of check matrix 1 corresponds to the circular node at the upper right corner of the Tanner graph (that is, variable node 0).

It can be seen that, in this example, if the factor graph includes 2 ^w (w+1) nodes, the corresponding Tanner graph includes 2 ^w (w+1) variable nodes and 2 ^w *w check nodes, Furthermore, the corresponding first check matrix includes 2 ^w (w+1) columns and 2 ^w *w rows.

In another example of this implementation (referred to as example 2), one variable node in the Tanner graph can correspond to multiple nodes in the factor graph, and one variable node in the Tanner graph can correspond to 2 nodes in the factor graph (I.e. p = 1) as an example, refer to the factor graph shown in Figure 5c. The factor graph includes 80 (2 ⁴ (4+1) = 80, ie w = 4) nodes, and the corresponding Tanner graph includes 32 (2 ³ (3+1)=32, that is, k=wp=3) variable nodes. In Fig. 5c, each dashed ellipse represents a variable node, and one variable node corresponds to two nodes in the factor graph. According to the check relationship between the 32 variable nodes, 24 (2 ³ *3=24) check nodes connected to the 32 variable nodes can be obtained. In this case, only the 4 layers on the right side of the factor graph are transformed, that is, the part contained by the dotted circle in the figure. For layer1 to layer4 of the factor graph, if every two adjacent nodes are regarded as a whole, the part that needs to be deformed is completely equivalent to the connection relationship of a factor graph in Figure 1b. The first check matrix obtained after layer1 to layer4 of the schematic factor graph is deformed (for ease of description, it is called LDPC code check matrix 2), as follows:

Each element in the LDPC code check matrix 2 obtained above represents a 2*2 sub-matrix, where -1 represents a 2*2 all-zero matrix, and 0 represents a 2*2 identity matrix, that is, LDPC The code check matrix 2 has a QC structure and is a QC-LDPC code check matrix.

Regarding the above example 1 and example 2, it can be seen that in the above example 1, a variable node of the Tanner graph includes a node in the factor graph, so that the complete factor graph can be deformed to obtain the LDPC code check matrix 1; in this case Next, the LDPC code check matrix 1 is not a QC-LDPC code check matrix, that is, the LDPC code check matrix obtained when the complete factor graph is deformed is not a QC-LDPC code check matrix. In Example 2, a variable node of the Tanner graph includes multiple nodes (such as 2) in the factor graph, so that a part of the factor graph is deformed to obtain the LDPC code check matrix 2, which can be seen from Figure 9 In the figure, layer1 to layer4 are deformed, but layer0 is not deformed; in this case, the obtained LDPC code check matrix is a QC-LDPC code check matrix.

It should be noted that: in the above example 2, a variable node of the Tanner graph includes 2 (p = 1) nodes in the factor graph as an example for description. When the value of p is other values, the above method can be referred to. . Among them, when p=1, each element in the obtained LDPC code check matrix represents a 2*2 sub-matrix, when p=2, each element in the obtained LDPC code check matrix Both represent a 4*4 sub-matrix. When p=3, each element in the obtained LDPC code check matrix represents an 8*8 sub-matrix. In other words, when a variable node in the Tanner graph includes 2 ^p (p is an integer greater than or equal to 0) nodes in the factor graph, each element in the resulting LDPC code check matrix represents a 2 ^p *2 The sub-matrix of ^p. Exemplarily, when a variable node in the Tanner graph corresponds to multiple nodes in the polarization code factor graph (that is, p is greater than or equal to 1), the obtained target LDPC code check matrix can all be QC-LDPC code calibration The test matrix has quasi-circular characteristics.

(2) Obtain the target LDPC code check matrix according to the first check matrix

Exemplarily, one or more of the following operations may be performed on the first check matrix: row swap, column swap, row merge, column merge, column delete. For example, by performing one or more operations on the first check matrix to obtain the target LDPC code check matrix, the target LDPC code check matrix can be divided into multiple layers for decoding using an LDPC layered decoder . Wherein, the first check matrix may be an LDPC code check matrix directly obtained by Tanner obtained by deforming the factor graph, such as the LDPC code check matrix 1 obtained in the above example 1 or the LDPC code check matrix obtained in the above example 2. Test matrix 2.

In an example, row transformation may be performed on the first check matrix to obtain the second check matrix; column merging and deletion are performed on the second check matrix to obtain the target LDPC code check matrix.

The row transformation, column merging, and deletion are explained separately below.

① Line transformation

Since the polarization code decoding method has serial characteristics in the decoding process, row transformation of the first check matrix can be considered to meet the serial characteristics of the polarization code decoding method.

Exemplarily, the serial characteristics of the polarization code decoding method in the decoding process are specifically expressed as: ①In the factor graph, different layers are calculated layer by layer, and the next layer is calculated after the previous layer is calculated; ② In a factor graph, calculations in the same layer include upper node calculations and lower node calculations. Usually, it is necessary to perform upper node calculations first, and then perform lower node calculations. Figure 5d is an example of a Tanner graph corresponding to a 2*2 polarization code butterfly network unit. In Figure 5d, C0, C1, C2, and C3 represent variable nodes, and R0 and R1 represent check nodes; among them, the upper node operation is also It can be called F operation, which refers to the calculation of the upper left node in the 2*2 polarization code butterfly network unit, as shown in Figure 5d, the calculation of node C2; the lower node operation can also be called G operation, It refers to the calculation of the node in the lower left corner in the 2*2 polarization code butterfly network unit, as shown in Figure 5d, the calculation of node C3. Since the check nodes contained in each layer of the factor graph correspond to the rows in the check matrix of the LDPC code, in order to meet the above serial characteristics, the following two conditions need to be met: Condition 1, in the check matrix of the LDPC code The check lines of the same layer in the corresponding factor graph are arranged consecutively, and the check lines of different layers in the corresponding factor graph are arranged continuously from left to right (or from right to left) and top to bottom in the factor graph; condition 2 , In a group of check lines at the same level in the corresponding factor graph, arrange the check lines corresponding to the upper node operation before the corresponding lower node check lines. According to the above process of determining the first check matrix, it can be seen that the first check matrix satisfies condition 1, so the order of the rows in the first check matrix (that is, row exchange) can be adjusted to satisfy condition 2, and thus meet the above serial characteristics .

In an example, the row swapping of the first check matrix may be: assuming that the first check matrix has 2 ^w *w rows (that is, the first row to the second ^w *w row), and the second ^w *i +1 -th to 2 ^w * (i + 1) row lines corresponding to the factor graph on the second node operation is adjusted to 2 ^w * i + 1 row to 2 ^{^w} * i + 2 ^w in order from top to bottom ^-1 row, adjust the row corresponding to the lower node operation in the factor graph from ^{the 2nd w} *i+1 row to the 2nd ^w ^{*(i+1) row from top to bottom to the 2nd w} *i+2 ^{line w-1} +1 to line 2 ^w *(i+1), where i=1, 2,...,w-1.

For example, taking the LDPC code check matrix 2 as an example, the Tanner graph of the corresponding factor graph is shown in FIG. 5b. Among them, the 1st to 8th rows in the LDPC check matrix 2 correspond to the check nodes between layer2 and layer3 in the factor graph; the 9th to 16th rows in the LDPC check matrix 2 correspond to the difference between layer1 and layer2 in the factor graph The check node between layer 0 and layer 1 in the LDPC code check matrix 2 corresponds to the check node between layer 0 and layer 1 in the factor graph. It can be seen that the check lines of the same layer in the corresponding factor graph in the LDPC check matrix 2 are arranged consecutively, and the check lines of different layers in the corresponding factor graph are consecutive from right to left and top to bottom in the factor graph. Permutation, that is, the above condition 1 is satisfied; but because the condition 2 is not satisfied, the LDPC code check matrix 2 can be row-swapped to satisfy the condition 2.

Exemplarily, the first to fourth rows in the LDPC code check matrix 2 correspond to the upper node operation of the check node between the factor graph layer2 and layer3, and the fifth to eighth rows in the LDPC code check matrix 2 correspond to the factor graph layer2 and The next node operation of the check node between layer3, this part meets the condition 2, and no row exchange is required.

Row

9, 10, 13, and 14 of the LDPC check matrix 2 correspond to the upper node operation of the check node between layer1 and layer2, and

rows

11, 12, 15, and 16 of the LDPC check matrix 2 correspond to the factor graph. The lower node operation of the check node between layer1 and layer2 does not meet condition 2. Therefore, the

original lines

9, 10, 13, and 14 can be adjusted to

lines

9, 10, 11, and 12, and the

original lines

11, 12, and 12 can be adjusted. Line 15,16 is adjusted to

line

13,14,15,16 to satisfy condition 2.

The 17th, 19th, 21st, and 23rd rows in the LDPC check matrix 2 correspond to the upper node operation of the check node between layer0 and layer1, and the 18th, 20th, 22nd and 24th rows in the LDPC check matrix 2 correspond to the factor graph. The lower node operation of the check node between layer0 and layer1 does not meet condition 2. Therefore, the original lines 17, 19, 21, and 23 can be adjusted to lines 17, 18, 19, and 20, and the original lines 18, 20, and 20 can be adjusted. Lines 22 and 24 are adjusted to lines 21, 22, 23, and 24 to satisfy condition 2.

Finally, after the above row transformation, the second parity check matrix that satisfies condition 1 and condition 2 is obtained, as shown below:

②Column merge

First, the row weight and column weight of the LDPC check matrix are explained: the row weight of the LDPC check matrix indicates the number of non-negative elements in a row in the LDPC check matrix; the column weight of the LDPC check matrix indicates the LDPC check matrix The number of non-negative elements in a column of the matrix. It should be noted that, here is an example in which all 0 elements in the LDPC check matrix are represented by -1, but other representation forms are not excluded.

Since all rows of the LDPC check matrix with a row weight equal to 2 pass the information of the variable node connected to it to another variable node, the two check nodes (two columns) connected to the row with the row weight equal to 2 can be connected. Combine to reduce the size of the LDPC check matrix, thereby reducing invalid operations in the decoding process.

Assuming that the two columns to be merged in the second check matrix are a and b, the merging process includes the following steps:

Step 1. Add modulo 2 of column b to column a, that is, add modulo 2 between the value of column b and the value of column a, and use the value obtained by modulo 2 addition to update the value of column a; Step 2, delete b Column, or set all elements in column b to -1 to obtain the third check matrix.

For example, in the above second matrix, only two elements in the 5th row have the value 0, and the row weight is equal to 2, and then the two check nodes connected to the row with the row weight equal to 2 can be connected (the 5th column and The 12th column) is combined, that is, the 5th column and the 12th column are added modulo 2, and the value of the 5th column is updated with the value obtained by the modulo 2 addition, and the following matrix is obtained:

Furthermore, all the elements in the 12th column are set to -1 to obtain the third check matrix, as shown below:

③Delete: row delete and column delete

For example, delete all rows with a row weight equal to 0 and columns with a column weight equal to 0 in the third check matrix, that is, delete the 5th row and the 12th column.

Understandably, in the above description of column merging, the two check nodes (two columns) connected to one of the rows with the row weight equal to 2 are combined as an example for description. If all rows in the second check matrix are resized If the rows equal to 2 are deformed, the target LDPC code check matrix can be obtained, as shown below:

It should be noted that the above is based on the modification of all rows of the second check matrix with a weight equal to 2 as an example. In other possible embodiments, since the last 2 ^w columns in the LDPC code check matrix correspond to The check node is the check node corresponding to the decoded bits in the factor graph. Considering that some decoding algorithms need to use the order of these check nodes, when doing column merging, the last 2 ^w columns may not participate in the column merging operation. The target LDPC code check matrix obtained in this situation is as follows:

The target LDPC code check matrix obtained through the above operations can be adapted to the layered decoding algorithm of the LDPC code, and the check formulas in the same layer in the target LDPC code check matrix can be calculated in parallel without affecting the calculation performance.

Several possible target LDPC code check matrix examples are given below.

Example 1: The LLR sequence includes 2 ^w LLRs, and when w is an integer greater than or equal to 1, the target LDPC code check matrix can be:

Wherein, the target LDPC code check matrix includes a first layer and a second layer, the first layer includes a first row, and the second layer includes a second row.

In Example 1, for example, when the LLR sequence includes 2 LLRs, and a variable node in the Tanner graph corresponds to a node in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained; for another example, When the LLR sequence includes 2 ^w = 4 LLRs, and a variable node in the Tanner graph corresponds to 2 nodes in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained; for another example, when the LLR sequence When 2 ^w = 8 LLRs are included, and a variable node in the Tanner graph corresponds to 4 nodes in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained.

Example 2: The LLR sequence includes 2 ^w LLRs, and when w is an integer greater than or equal to 2, the target LDPC code check matrix can be:

Wherein, the target LDPC code check matrix includes a first layer, a second layer, and a third layer. The first layer includes the first row and the second row, the second layer includes the third row and the fourth row, and the third layer includes The fifth and sixth rows.

In Example 2, for example, when the LLR sequence includes 2 ^w = 4 LLRs, and a variable node in the Tanner graph corresponds to a node in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained; For another example, when the LLR sequence includes 2 ^w = 8 LLRs, and a variable node in the Tanner graph corresponds to 2 nodes in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained; for another example, When the LLR sequence includes 2 ^w = 16 LLRs, and a variable node in the Tanner graph corresponds to 4 nodes in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained.

Example 3: The LLR sequence includes 2 ^w LLRs, and when w is an integer greater than or equal to 3, the target LDPC code check matrix can be:

The target LDPC code check matrix includes the first layer, the second layer, the third layer, and the fourth layer. The first layer includes the first row to the fourth row, and the second layer includes the fifth row to the eighth row. The third layer includes the ninth to twelfth rows, and the fourth layer includes the thirteenth to sixteenth rows.

In Example 3, for example, when the LLR sequence includes 2 ^w = 8 LLRs, and a variable node in the Tanner graph corresponds to a node in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained; For another example, when the LLR sequence includes 2 ^w = 16 LLRs, and a variable node in the Tanner graph corresponds to 2 nodes in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained; another example, When the LLR sequence includes 2 ^w = 32 LLRs, and a variable node in the Tanner graph corresponds to 4 nodes in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained.

Example 4: The LLR sequence includes 2 ^w LLRs, and when w is an integer greater than or equal to 4, the target LDPC code check matrix can be:

Among them, the target LDPC code check matrix includes the first layer to the fifth layer, the first layer includes the first row to the eighth row, the second layer includes the ninth row to the sixteenth row, and the third layer includes the seventeenth row. To the twenty-fourth row, the fourth layer includes the twenty-fifth row to the thirty-second row, and the fifth layer includes the thirty-third row to the fortieth row.

In Example 4, for example, when the LLR sequence includes 2 ^w = 16 LLRs, and a variable node in the Tanner graph corresponds to a node in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained; For another example, when the LLR sequence includes 2 ^w = 32 LLRs, and a variable node in the Tanner graph corresponds to 2 nodes in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained; another example, When the LLR sequence includes 2 ^w =64 LLRs, and one variable node in the Tanner graph corresponds to 4 nodes in the polarization code factor graph, the target LDPC code check matrix shown above can be obtained.

It should be noted that in other possible embodiments, the target LDPC code check matrix can also be expressed in other forms. For example, the target LDPC code check matrix shown in Example 1 can also be expressed in the form of a table as shown below :

In the above table, the elements marked with values in the check matrix of the target LDPC code are recorded. The first column of the table represents the current row number, the second column represents a corresponding column number in the row number, and the third column Indicates the value of the corresponding element. For example, the above table indicates: in the 0th row, the 0th column, the 1st column, and the 2nd column have values, and their values are 0, 0, 0 respectively; in the 1st row, the first Two columns, column 0 and column 3, have values, and their values are 0,0 respectively.

Based on the above steps 401 to 404, an example of the decoding process will be described below with reference to FIG. 6.

Figure 6 is a logical schematic diagram of the decoding process provided by an embodiment of the application. As shown in Figure 6, the decoding process can be implemented by cascading an LDPC code decoder and an SCL decoder, where the SCL decoder It can be an SCL2 (that is, the path width is 2) decoder, as shown in Figure 7. The part in the dashed box in Figure 6 represents the LDPC code decoder that supports the target LDPC code matrix, which includes two parts: the target LDPC code matrix is calculated from the top to the bottom and the bottom is calculated from the bottom to the top. Taking the target LDPC code matrix shown in Example 2 above as an example, its specific implementation may include:

Step 1. Obtain the LLR sequence. The LLR sequence includes 8 LLRs.

Step 2: Input 8 LLRs into the LDPC decoder. The 8 LLRs correspond to the first 4 columns of the matrix in Example 2 from left to right. Perform the minimum sum of the target LDPC check matrix from top to bottom row by row (Min -Sum) or Sum-Product (Sum-Product) decoding until the last line.

Step 3: Output the two LLRs corresponding to the first column of the LLRs corresponding to the last 4 columns of the target LDPC code check matrix (here LLRs refer to the LLRs decoded in step 2), and input them to the SCL decoding器(L=2).

Step 4. The SCL decoder performs SCL decoding on the two input LLRs to obtain two decoding paths. Each path contains 2 output bits. After the two paths obtained by SCL decoding are saturated according to the decoding results, It is fed back to the LDPC decoder; all subsequent operations include at least 2 paths.

Step 5. Perform Min-Sum or Sum-Product decoding on the target LDPC code check matrix from bottom to top row by row until the first row; then perform Min-Sum on the target LDPC code check matrix row by row from top to bottom Or Sum-Product decoding until the last line.

Step 6. Output the two LLRs corresponding to the second column among the LLRs corresponding to the last 4 columns of the target LDPC code check matrix, and input them into the SCL decoder.

Step 7. The SCL decoder performs SCL decoding on the two LLRs of the two input paths to obtain four new decoding paths. Each path contains 2 output bits. The SCL decoder selects the most reliable 2 among them. After updating their parent paths, the two decoding paths are fed back to the LDPC decoder.

Step 8. Perform Min-Sum or Sum-Product decoding on the target LDPC code check matrix from bottom to top row by row until the first row; then perform Min-Sum on the target LDPC code check matrix row by row from top to bottom Or Sum-Product decoding until the last line.

Step 9. Output the two LLRs corresponding to the third column among the LLRs corresponding to the last four columns of the target LDPC code check matrix, and input them into the SCL decoder.

Step 10. The SCL decoder performs SCL decoding on the two LLRs of the two input paths to obtain four new decoding paths. Each path contains 2 output bits. The SCL decoder selects the most reliable 2 among them. After updating their parent paths, the two decoding paths are fed back to the LDPC decoder.

Step 11. Perform Min-Sum or Sum-Product decoding on the target LDPC code check matrix from bottom to top row by row until the first row; then perform Min-Sum on the target LDPC code check matrix row by row from top to bottom Or Sum-Product decoding until the last line.

Step 12: Output the two LLRs corresponding to the fourth column among the LLRs corresponding to the last four columns of the target LDPC code check matrix, and input them into the SCL decoder.

Step 13. The SCL decoder performs SCL decoding on the two LLRs of the two input paths to obtain four new decoding paths. Each path contains 2 output bits. The SCL decoder selects the most reliable 2 among them. Among them, one decoding path that can pass the CRC check is selected as the decoded bit sequence for output. If both paths pass the CRC check, the more reliable one is selected for output as the decoded bit sequence.

According to the decoding process described in Figure 6, it can be seen that by determining the target LDPC code check matrix, the cascaded LDPC code decoder and SCL decoder can be used to achieve decoding, so that polarization code decoding and LDPC can be decoded. Code decoding can be common-mode decoding, which effectively saves hardware overhead.

It can be understood that, in order to realize the above-mentioned functions, the decoding device may include hardware structures and/or software modules corresponding to each function. Those skilled in the art should easily realize that in combination with the units and algorithm steps of the examples described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed by hardware or computer software-driven hardware depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In the case of an integrated unit (module), FIG. 8 shows a possible exemplary block diagram of a device involved in an embodiment of the present application, and the device 800 may exist in the form of software. The apparatus 800 may include:

The obtaining module 801 obtains the log-likelihood ratio LLR sequence corresponding to the bit sequence to be decoded, the LLR sequence includes 2 ^w LLRs, and the bit sequence to be decoded is obtained by encoding the first bit sequence with a polarization code , The first bit sequence includes information bits; w is an integer greater than or equal to 1; the decoding module 802 is configured to determine the low-density parity check LDPC code check matrix corresponding to the bit sequence to be decoded; The LLR sequence is decoded based on the LDPC code check matrix to obtain a first decoding result; and a decoded bit sequence is obtained according to the first decoding result.

In a possible design, the decoding module 802 is specifically configured to: use an LDPC code layered decoder to decode the LLR sequence based on the LDPC code check matrix to obtain the first decoding result.

In a possible design, the decoding module 802 is specifically configured to decode the first decoding result using a polarization code decoder to obtain the decoded bit sequence.

In a possible design, the decoding module 802 is specifically configured to: determine a polarization code factor graph corresponding to the bit sequence to be decoded, and the polarization code factor graph includes 2 ^w *(w+1) nodes ; According to the check relationship between different nodes in the polarization code factor graph, determine the LDPC code Tanner graph, the Tanner graph includes 2 ^k * (k + 1) variable nodes and 2 ^k * k check Nodes, each of the variable nodes corresponds to 2 ^p nodes in the polarization code factor graph, k is an integer greater than or equal to 1, p is an integer greater than or equal to 0, w=p+k; The 2 ^k *(k+1) variable nodes and the 2 ^k *k check nodes determine the LDPC code check matrix corresponding to the bit sequence to be decoded.

In a possible design, the decoding module 802 is specifically configured to: determine a first check matrix ^{according to the 2 k} *(k+1) variable nodes and 2 ^{k *k check nodes;} A check matrix performs one or more of the following operations to obtain the LDPC code check matrix: row swap, column swap, row merge, column merge, row delete, column delete.

In a possible design, the determined LDPC code check matrix is:

It should be noted that the division of the modules by the decoding device shown in FIG. 8 in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, there may be other division methods. In addition, in the present application The functional units in the various embodiments may be integrated into one processing unit, or may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

As shown in FIG. 9, an embodiment of the present application also provides a decoding device 900, which is used to execute the decoding method shown in FIG. 4. Part or all of the decoding method shown in FIG. 4 can be implemented by hardware or software. When implemented by hardware, the decoding device 900 includes: an input interface circuit 901 for obtaining a sequence of bits to be decoded Corresponding LLR sequence; logic circuit 902, used to implement the decoding method shown in FIG. 4; output interface circuit 903, used to output the decoded bit sequence.

Optionally, the decoding device 900 may be a chip or an integrated circuit during specific implementation.

Optionally, when part or all of the decoding method shown in FIG. 4 is implemented by software, as shown in FIG. 10, the decoding device 1000 includes: a memory 1001 for storing programs; a processor 1002 for The program stored in the memory 1001 is executed, and when the program is executed, the decoding apparatus 1000 can implement the decoding method shown in FIG. 4.

Optionally, the foregoing memory 1001 may be a physically independent unit, or may be integrated with the processor 1002.

Optionally, when part or all of the decoding method shown in FIG. 4 is implemented by software, the decoding apparatus 1000 may also only include the processor 1002. The memory 1001 for storing programs is located outside the decoding device 1000, and the processor 1002 is connected to the memory 1001 through a circuit/wire for reading and executing the programs stored in the memory 1001.

The processor 1002 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.

The processor 1002 may further include a hardware chip. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

The memory 1001 may include a volatile memory (volatile memory), such as a random-access memory (random-access memory, RAM); the memory 1001 may also include a non-volatile memory (non-volatile memory), such as a flash memory (flash memory). memory), a hard disk drive (HDD) or a solid-state drive (SSD); the memory 1001 may also include a combination of the foregoing types of memories.

The embodiment of the present application also provides a computer storage medium storing a computer program, and the computer program includes a decoding method for executing the decoding method provided in the foregoing method embodiment.

The embodiments of the present application also provide a computer program product containing instructions, which when run on a computer, cause the computer to execute the decoding method provided by the foregoing method embodiments.

Any decoding device provided in the embodiments of the present application may also be a chip.

Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, this application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

This application is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of this application. It should be understood that each process and/or block in the flowchart and/or block diagram, and the combination of processes and/or blocks in the flowchart and/or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing equipment to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing equipment are generated It is a device that realizes the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device. The device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment. The instructions provide steps for implementing the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A decoding method, characterized in that the method includes:

Obtain a log-likelihood ratio LLR sequence corresponding to the bit sequence to be decoded, the LLR sequence includes 2 w LLRs, and the bit sequence to be decoded is obtained by encoding the first bit sequence with a polarization code, the The first bit sequence includes information bits; w is an integer greater than or equal to 1;

Determining a low-density parity-check LDPC code check matrix corresponding to the bit sequence to be decoded;

Decoding the LLR sequence based on the LDPC code check matrix to obtain a first decoding result;

Obtain a decoded bit sequence according to the first decoding result.
The method according to claim 1, wherein decoding the LLR sequence based on the LDPC code check matrix to obtain a first decoding result comprises:

Using an LDPC code layered decoder to decode the LLR sequence based on the LDPC code check matrix to obtain the first decoding result.
The method according to claim 1 or 2, wherein obtaining a decoded bit sequence according to the first decoding result comprises:

A polarization code decoder is used to decode the first decoding result to obtain the decoded bit sequence.
The method according to any one of claims 1 to 3, wherein determining the LDPC code check matrix corresponding to the bit sequence to be decoded comprises:

Determining a polarization code factor graph corresponding to the bit sequence to be decoded, where the polarization code factor graph includes 2 w *(w+1) nodes;

According to the check relationship between different nodes in the polarization code factor graph, 2 k *(k+1) variable nodes and 2 k *k check nodes in the Tanner graph are determined, and each of the variable nodes is Corresponding to the 2 p nodes in the polarization code factor graph, k is an integer greater than or equal to 1, p is an integer greater than or equal to 0, w=p+k;

The LDPC code check matrix corresponding to the bit sequence to be decoded is determined according to the 2 k *(k+1) variable nodes and the 2 k *k check nodes.
The method according to claim 4, wherein the LDPC code check corresponding to the bit sequence to be decoded is determined according to the 2 k *(k+1) variable nodes and 2 k *k check nodes The matrix includes:

Determine the first check matrix according to the 2 k *(k+1) variable nodes and 2 k *k check nodes;

Perform one or more of the following operations on the first check matrix to obtain the LDPC code check matrix: row swap, column swap, row merge, column merge, row delete, column delete.
The method according to any one of claims 1 to 5, wherein the LDPC code check matrix corresponding to the bit sequence to be decoded is a quasi-cyclic QC-LDPC code check matrix.
The method according to any one of claims 1 to 6, wherein the determined LDPC code check matrix is:

Wherein, the LDPC code check matrix includes a first layer and a second layer, the first layer includes a first row, and the second layer includes a second row.
The method according to any one of claims 1 to 6, wherein the w is an integer greater than or equal to 2;

The determined LDPC code check matrix is:

Wherein, the LDPC code check matrix includes a first layer, a second layer and a third layer, the first layer includes a first row and a second row, and the second layer includes a third row and a fourth row, The third layer includes a fifth row and a sixth row.
The method according to any one of claims 1 to 6, wherein w is an integer greater than or equal to 3;

The determined LDPC code check matrix is:

Wherein, the LDPC code check matrix includes a first layer, a second layer, a third layer, and a fourth layer, the first layer includes the first row to the fourth row, and the second layer includes the fifth row to the fourth layer. Eight rows, the third layer includes the ninth row to the twelfth row, and the fourth layer includes the thirteenth row to the sixteenth row.
The method according to any one of claims 1 to 6, wherein w is an integer greater than or equal to 4;

The determined LDPC code check matrix is:

Wherein, the LDPC code check matrix includes the first layer to the fifth layer, the first layer includes the first row to the eighth row, the second layer includes the ninth row to the sixteenth row, and the first layer includes the ninth row to the sixteenth row. The third layer includes the seventeenth row to the twenty-fourth row, the fourth layer includes the twenty-fifth row to the thirty-second row, and the fifth layer includes the thirty-third row to the fortieth row.
A decoding device, characterized in that the decoding device comprises:

Memory, used to store programs;

The processor is configured to execute the program stored in the memory, and when the program is executed, the processor is configured to execute the method according to any one of claims 1-10.
The device according to claim 11, wherein the decoding device is a chip or an integrated circuit.
A decoding device, characterized in that it comprises:

Input interface circuit for obtaining the LLR sequence corresponding to the bit sequence to be decoded;

A logic circuit, configured to execute the method according to any one of claims 1 to 10 based on the acquired LLR sequence;

The output interface circuit is used to output the decoded bit sequence.
A chip, characterized in that it comprises:

Memory, used to store programs;

The processor is configured to execute the program stored in the memory, and when the program is executed, the processor is configured to execute the method according to any one of claims 1-10.
A chip, characterized in that it comprises:

Input interface circuit for obtaining the LLR sequence corresponding to the bit sequence to be decoded;

A logic circuit, configured to execute the method according to any one of claims 1 to 10 based on the acquired LLR sequence;

The output interface circuit is used to output the decoded bit sequence.
A computer-readable storage medium, wherein computer-readable instructions are stored in the computer storage medium, and when the computer reads and executes the computer-readable instructions, the computer executes any one of claims 1 to 10 The method described in the item.
A computer program product, characterized in that when a computer reads and executes the computer program product, the computer is caused to execute the method according to any one of claims 1-10.