CN107919874A

CN107919874A - Basic code check node processing for the decoded syndrome computation of nonbinary LDPC code

Info

Publication number: CN107919874A
Application number: CN201710804051.3A
Authority: CN
Inventors: C·马尔尚; E·布蒂永
Original assignee: Universite de Bretagne Sud
Current assignee: Universite de Bretagne Sud
Priority date: 2016-09-09
Filing date: 2017-09-08
Publication date: 2018-04-17
Anticipated expiration: 2037-09-08
Also published as: US10560120B2; EP3293885A1; KR102061938B1; KR20180028981A; US20180076830A1; EP3293885B1; CN107919874B

Abstract

The embodiment of the present invention provides the code check node processing unit realized in a kind of decoder for decoded signal, the code check node processing unit is configured as receiving at least three input message and generates at least one output message, wherein the code check node processing unit includes：Syndrome calculator (31), it is configured with least two basic check node processors (311) and determines one group of syndrome from described at least three input message, and each syndrome includes symbol, the degree of reiability associated with the symbol and binary vector；Correlated elements (33), it is configured as determining one group of candidate components from one group of syndrome in association with least one output message, each candidate components include symbol and the degree of reiability associated with the symbol, and one group of candidate components contain one or more pairs of components of same-sign；And selecting unit (35), it is configured as determining at least one output message by including the component of distinct symbols from one group of candidate components selection associated with least one output message.

Description

Basic code check node processing for the decoded syndrome computation of nonbinary LDPC code

Technical field

The present invention relates generally to digital communication, more particularly, to carries out decoded side to the signal encoded using error correcting code Method and equipment.

Background technology

Error correcting code allows to detect and corrects by interchannel noise, interference or transmit the phase in its storage or from transmitted from transmitter to receiver Between influence data any infringement caused by mistake.The detection and/or correction of mistake are depended on during cataloged procedure to original Data add redundant data.

There is provided in many data transfers and storage system and equipment using error correcting code in noisy insecure biography The reliable and possible error-free transmission of numerical data on defeated channel.These technologies are faced with huge demand, and are used for Various applications, including for example in wireless self-organization network (such as in 802.11 Plays of Wi-Fi), in radio communication system System (for example, 3G, 4G/LTE, 5G and more than these), the Transmission system based on optical fiber and digital video broadcasting (such as In DVB-C2, DVB-S2X and DVB-T2 Plays) in voice and multimedia transmission.

Liner code belongs to error correcting code classification.They are characterized in that the linear characteristic of code word, according to the characteristic, two or more Any linear combination of multiple code words is code word.

According to first linear " convolutional encoding " method using convolutional code, cataloged procedure is based on symbol-by-symbol compiling data Code.

According to second linear " block coding " method, coded treatment is based on compiling data by the symbolic blocks of fixed size Code.Exemplary linear block code includes Hamming code (Hamming codes), Reed Solomon code (Reed-Solomon Codes), Turbo code and low-density checksum (LDPC) code.

Error correcting code is probably binary system or nonbinary.In Galois Field (Galois Fields) GF (q) of q=2 ranks The code of upper construction is binary code.Therefore, the various components (hereinafter referred to as " symbol ") of any code word belong to value set { 0,1 }. In q>The code constructed on the Galois Field GF (q) of 2 ranks is non-binary.Therefore, various symbols take the value in GF (q).

Given linear characteristic, any linear error correction code can be by usually by the G generator matrixes represented and usually using H tables The parity matrix shown represents, by relation G.H^t=0 link.The entry of generator and parity matrix belongs to structure on it Build the domain of code.Parity matrix defines the parity check constraint for being designed to be met by code word.Especially, LDPC code by Sparse Parity-check Matrix including zero number of entries more much higher than non-zero number of entries is specified.

It can represent (i.e. so-called based on the figure of the code associated with the parity matrix of foundation code " Tanner figures ") data encoded using linear error correction code are decoded to perform.The figure of linear error correction code represents to include Two group nodes：It is referred to as first group node of " variable node " and is referred to as second group node of " check-node ".Variable node It is connected together with check-node by side chain.Variable node and check-node form processing unit.Each variable node and odd even The row of check matrix are associated.Each check-node is associated with the row of parity matrix, i.e., related to parity check equation Connection.Connection between variable node and check-node is the non-zero entry by parity matrix come definite.

Iterative decoder can be used for decoding the data encoded using linear block error.Given expression for example communicates The noise sequence of the coded identification of the output of channel, iterative decoder handle noise sequence during successive ignition, make it every Closer to original coded identification sequence in secondary iteration.

Tanner figures represent to can be used for realizing iterative decoding.Therefore, decoding process can be by via connecting it in figure The iteration of message of the different edges between the processing unit associated with variable node and check-node exchange to perform. Each variable node processing unit or code check node processing unit receive input message from the node accordingly connected in figure, and And after processing inputs message, it is single that output message is transmitted at least one processing corresponding with the connecting node in figure Member.If meeting all parity check constraints, so that decoded code word is returned, or by reaching maximum iteration and discontented All parity check constraints of foot, then decoding process stopping.

Transmission message between different variable node processing units and code check node processing unit carries and coded identification phase Associated information.Message can include symbol and measure the measurement (hereinafter referred to as " degree of reiability ") of the reliability of symbol.Symbol Number degree of reiability can for example corresponding to its estimation probability density function, measure the symbol be equal to for encode code Structural domain in the probability being each worth.

Earlier iterations decoding algorithm is designed to binary code and is applied to binary system LDPC code.They are that " and product " is calculated Method (also referred to as " belief propagation " or " message transmission " algorithm) and " minimum and " algorithm, they are all in " N.Wibereg, H- A.Loeliger and R.Kotter, Codes and Iterative Decoding on General Graphs, European Transactions on Telecommunications and Related Technologies,special issue on Disclosed in Turbo Coding, June nineteen ninety-five ".They provide near optimal performance in terms of decoded in error probability.

Iterative decoding algorithm designed for nonbinary code is subject to the inspiration of " and product " algorithm.For nonbinary code Exemplary iterative decoder includes " multi-system (q-ary) and product " algorithm of such as following discloses：

- " M.Davey and D.MacKay, Low-density parity check codes over GF (q), IEEE Communications Letters, volume 2, the 6th, the 165-167 pages, in June, 1998 ",

- " D.J.C.Mackay and M.Davey, Evaluation of Gallager Codes for Short Block Length and High Rate Applications, In Proceedings of IMA Workshop on Codes, Systems and Graphical Models, 1999 ", and

- " L.Barnault and D.Declercq, Fast decoding algorithm for LDPC overGF (q), In Proceedings of IEEE Information Theory Workshop, the 70-73 pages, in April, 2003 ".

Some iterative decoding algorithms are calculated based on logarithmic scale, are dropped by the way that product computing is converted to simple summation operation Low computation complexity.This decoding scheme includes：

- in " H.Sadjadpour, Maximum A Posteriori Decoding Algorithms For Turbo Codes, In Proceedings of SPIE, volume 4045,2000 " disclosed in ' the decoding of max-log-map'turbo codes Device,

- in " D.Declercq and M.Fossorier, Decoding algorithms for non-binary LDPC codes over GF, IEEE Transactions on Communications, volume 55, the 4th, the 633rd -643 " extension minimum and " (EMS) nonbinary LDPC code decoder disclosed in page, in April, 2007 ", and

- in " V.Savin, Min-max decoding for non-binary LDPC codes, In Proceedings Of IEEE International Symposium on Information Theory, page 960-964, in July, 2008 " Disclosed in ' min-max (min-max) ' nonbinary LDPC code decoder.

Log-domain meter of the EMS algorithms based on the message exchanged between variable node processing unit and code check node processing unit Calculate.Since the maximum complexity of EMS algorithms is the calculating that is performed by code check node processing unit, so EMS algorithms are to processing Messages application is sorted and blocked, further to mitigate the computation complexity of code check node processing unit and memory requirement.According to The order of the degree of reiability associated with the symbol being included in the input message received performs prioritisation of messages.Perform message Block to retain most reliable symbol in given input and/or output message.

Can be according to various frameworks, to the rank of the code check node processing unit of the input message after sorting and blocking Output message calculated.Existing framework includes " forward-backward " framework and the framework based on syndrome.

In " forward-backward " framework, the calculating that is performed by code check node processing unit be divided into be related to it is multiple basic Multiple serial computings of code check node processing unit (hereinafter referred to as " basic check node processor ").Each basic check-node Processor handles two or more input message to produce in follow-up phase then by remaining basic check node processor The intermediary message used.The intermediary message of calculating is ranked up based on the degree of reiability associated with solution code sign.It is in addition, every A basic check node processor performs the elimination of redundancy to suppress the message for including same-sign, while keeps including most reliable Redundant symbol message.The exemplary algorithm of basic code check node processing includes：

- " E.Boutillon and L.Conde-Canencia, Bubble check：a simplified algorithm for elementary check node processing in extended min-sum non-binary LDPC decoder, Electronics Letters, volume 46, the 9th, the 633-634 pages, in April, 2010 " disclosed in ' Bubble check ' algorithms, and

- " E.Boutillon, L.Conde-Canencia and A.Al Ghouwayel, Design of a GF (64)- LDPC Decoder based on the EMS algorithm, IEEE Transactions on Circuits and Being referred to as disclosed in Systems, volume 60, the 10th, the 2644-2656 pages, in October, 2013 " " L-Bubble verifications " ' the modified version of Bubble check ' algorithms.

Bubble-check and L-Bubble check algorithms are based on subtracting from two input message and are saved by basic verification The search space for the optimal intermediate result that point processor calculates.

In the framework based on syndrome, code check node processing unit realizes the decoding based on syndrome.From sequence and cut The input message having no progeny, which calculates output message, needs two steps.In the first step, code check node processing unit is calculated and is related to The class value for being known as " syndrome " of all input message.In the second step, solution is performed in association with each output message Relevant operation.Decorrelation operation from the syndrome calculated in cancelling previously from the reception as the output message calculated The contribution for the input message that the variable node processing unit of person receives.Framework based on syndrome is disclosed in：

-“P.Schlafer,N.When,M.Alles,T.Lehnigk-Emden and E.Boutillon,Syndrome based check node processing of high order NB-LDPC decoders,In Proceedings of The International Conference on Telecommunications, the 156-162 pages, in April, 2015 "；

- " P.Schlafer et al., A new Architecture for High Speed, Low Latency NB- LDPC Check Node Processing, In Proceedings of IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, in August, 2015 ".

Framework based on syndrome allows parallel computation, this is particularly advantageous for high-order Galois Field.However, utilize This framework, computation complexity are dominated by the verification quantum count calculated, and the verification quantum count calculated is with input message Quantity increase and increase.

Forward-backward framework allow reduce hardware cost.However, it introduces high latency, cause the reduction of throughput of system. Framework based on syndrome causes the complexity of height, mainly due to caused by the increase of the verification quantum count of calculating. The actual realization for solving the framework based on syndrome in code system needs substantial amounts of calculating and storage resource, calculates with storage resource simultaneously It is always not available.Especially, some actual realizations of the framework are not suitable for the solution of the nonbinary code with high code-rate Code.

Therefore, it is necessary to develop in EMS decoders, particularly usually in any iterative decoding based on Tanner figures The framework of the efficient and low complex degree for the code check node processing unit realized in device.

The content of the invention

In order to solve the problems, such as these and other, there is provided it is a kind of realize in a decoder be used for signal carry out it is decoded Code check node processing unit.Code check node processing unit is configured as receiving at least three input message and generates at least one Output message.Code check node processing unit includes：

- syndrome calculator, it is defeated from described at least three to be configured with least two basic check node processors Enter message and determine one group of syndrome.Each syndrome include symbol, the degree of reiability associated with the symbol and two into System vector；

- correlated elements, are configured as determining from one group of definite verification in association with least one output message One group of candidate components of son.Each candidate components include symbol and the degree of reiability associated with the symbol.One group of candidate Component contains one or more pairs of components of same-sign；With

- selecting unit, is configured as by from the one group candidate components associated with least one output message Selection includes the components of distinct symbols to determine at least one output message.

According to some embodiments, at least one basic check node processor can be configured as from first message and second Message determines intermediary message, and the first message and second message are derived from least three input message of reception.It is middle Message can include one or more components and the intermediate binary associated with each component vector.Each component can include Symbol and the degree of reiability associated with the symbol.Can be with addition, being included in one or more of intermediary message component It is ordered as the degree of reiability of the symbol of given order.In these embodiments, syndrome calculator can be configured as root One group of syndrome is determined according to the intermediary message determined from all input message.

According to some embodiments, there is provided code check node processing unit can be for carrying out decoded decoder to signal Middle realization, the signal are encoded using at least one error correcting code.Disappear from least three each of input message received Breath can include one or more components, and each component includes symbol and the degree of reiability associated with the symbol.So Embodiment in, at least one basic check node processor can be configured as by the structure at least one error correcting code Domain is made using add operation to determine to be included in the symbol in the component of intermediary message.Add operation can be applied to be included in Symbol in the component of one message and the symbol being included in the component of second message.

According to some embodiments, at least one basic check node processor can be configured as by given algebraically Structure application add operation determines to be included in the degree of reiability in the component of intermediary message.Add operation can be applied to wrap Include the degree of reiability in the component of first message and the degree of reiability being included in the component of second message.

In certain embodiments, given generation can be selected in the group being made of real number field, integer field and natural number field Table structure.

According to some embodiments, syndrome calculator can be additionally configured to be included within least three input message Each component is associated with initial binary value.Therefore, each component of first message and second message can with from initial two Binary vector is associated derived from hex value.In such embodiments, at least one basic check node processor can be with It is configured as determining the intermediate binary vector associated with the component of intermediary message by the vectorial cascade operation of application.Vector Cascade operation can be applied to the binary vector associated with the component of first message and associated with the component of second message Binary vector.

In certain embodiments, the component being included in each input message can be according to the symbol being included in these components Number the given order of degree of reiability be ranked up.In such embodiments, syndrome calculator can be configured as by Component including most reliability symbols is associated with the initial binary value equal to predefined first value, and by residual components It is associated with the initial binary value equal to predefined second value.

According to one embodiment, predefined first value can be equal to zero, and predefined second value can be equal to 1.

In addition, the binary vector being included in each syndrome can include multiple bits, each bit disappears with output Manner of breathing associates.In such embodiments, correlated elements can be configured as by being selected in identified one group of syndrome Select and be included therein syndrome of the bit associated with given output message equal to the binary vector of predefined first value To determine the one group candidate components associated with given output message.

According to one embodiment, basic check node processor can be realized with serial frame.

According to another embodiment, basic check node processor can be realized with setting framework.

According further to another embodiment, basic check node processor can be realized with mixed architecture, the mixed architecture Including some the basic check node processors realized with serial frame and to set some basic check nodes of framework realization Manage device.

According to some embodiments, selecting unit can be configured as by the reliable of the symbol in one group of candidate components Property measurement come from the one group candidate components associated with least one output message selection include the predetermined quantities of distinct symbols Component determine at least one output message.

In certain embodiments, at least one error correcting code can be Nonbinary Error-correcting Codes.

Additionally provide and at least one output message is calculated at a kind of code check node processing unit realized in a decoder Method.Decoder is configured as decoding signal.Code check node processing unit is configured as receiving at least three and inputting disappearing Breath.This method includes：

- from described at least three input message determine one group of syndrome.Each syndrome includes symbol, associated with symbol Degree of reiability and binary vector；

- with least one output message in association determine one group of candidate components from this group of syndrome.Each candidate Component includes symbol and the degree of reiability associated with the symbol.This group of candidate components contain a pair of same-sign Or multipair component；And

- by selecting to include distinct symbols from one group of candidate components associated with least one output message Component determines at least one output message.

Additionally provide and a kind of disappear for calculating at least one output at the code check node processing unit realized in a decoder The computer program of breath.Decoder is configured as decoding signal.Code check node processing unit is configured as receiving at least Three input message.The computer program product includes：

Non-transitory computer-readable storage media and the instruction being stored in non-transitory computer-readable storage media, Instruction is when executed by the processor so that processor：

- from least three input message determine one group of syndrome.Each syndrome include symbol, it is associated with symbol can By property measurement and binary vector；

Advantageously, various embodiments allow to reduce involved in the calculating of the output message at code check node processing unit The quantity of the syndrome of calculating.As a result, the code check node processing unit realized in error-correcting code decoder can be significantly decreased The computation complexity at place.

In addition, various embodiments allow from decoded concurrency and the line of basic code check node processing based on syndrome The two-fold advantage of property complexity.Such combination allows hard-wired cost, the handling capacity for reducing code check node processing unit Improve and silicon area is saved.

After investigating attached drawing and being described in detail, further advantage of the invention will be clear for technicians.

Brief description of the drawings

Be incorporated to and form the attached drawing of the part of this specification together with general description of the invention given above and under The detailed description for the embodiment that face provides together illustrates various embodiments of the present invention.

Fig. 1 is the block diagram of the exemplary application of the invention in accordance with some embodiments to communication system；

Fig. 2 is the block diagram of iterative decoder in accordance with some embodiments；

Fig. 3 is the block diagram for the structure for showing code check node processing unit in accordance with some embodiments；

Fig. 4 is the block diagram for the structure for representing basic code check node processing unit according to an embodiment of the invention.

Fig. 5 is the syndrome meter represented according to the embodiment that multiple basic check node processors are realized in serial frame Calculate the block diagram of the structure of device；

Fig. 6 is represented according to multiple basic check node processors to set the syndrome calculator of the embodiment of framework realization Structure block diagram；

Fig. 7 is the check node for representing some embodiments according to the serial implementation using basic check node processor Manage the block diagram of the structure of unit.

Fig. 8 is to describe in accordance with some embodiments decode based on the syndrome using multiple basic check node processors to exist The flow chart of the method for output message is determined at code check node processing unit；

Fig. 9 is the component for illustrating the two input message in accordance with some embodiments handled by basic check node processor Matrix represent figure；

Figure 10 is the component for illustrating the two input message according to the embodiment handled by basic check node processor The figure that matrix represents；

Figure 11 is point for illustrating the two input message handled by basic check node processor according to another embodiment Measure the figure that the matrix of quantity represents；

Figure 12 is the school that the use for illustrating according to some embodiments of the present invention is related to multiple basic check node processors Test the figure of the frame error ratio of subsolution code acquisition；

Figure 13 is the quantity for illustrating basic check node processor according to some embodiments of the present invention and basic verification The form of the complexity of the Number Forms of the input/output of modal processor；And

Figure 14 is the syndrome represented according to the embodiment that multiple basic check node processors are realized in mixed architecture The block diagram of the structure of calculator.

Embodiment

The embodiment provides the signal being used for being encoded using error correcting code of the computation complexity with reduction Carry out decoded apparatus, method, and computer program product.Especially, various embodiments provide for using non-two into The signal of error correcting code coding processed carries out the improved framework for the code check node processing unit realized in decoded iterative decoding algorithm.

Method, equipment and computer program product according to various embodiments can be in various types of digital data transfers Realize, and can be used in different types of application with storage system, such as wired, wireless and optic communication, solid state data Storage device, magnetooptic recording, DTV and video broadcasting.

Some embodiments of the present invention are described below in reference numeral communication system, the purpose being merely to illustrate. However, those skilled in the art will readily appreciate that, various embodiments of the present invention can be integrated in other kinds of system (example As wired, wirelessly, acoustics, optics and molecular system etc.) in.

In addition, exclusively for the purposes of illustration, it is following to some embodiments of the present invention progress that linear block error will be referred to Illustrate, but to will readily appreciate that various embodiments of the present invention can be applied to any kind of linear by those skilled in the art Code (including convolutional code), is applied more generally to any kind of error correcting code.

With reference to figure 1, exemplary realization of the present invention in digital communication system 100 is shown.Communication system 100 can be with Including transmitter apparatus 10 and receiver device 12.Transmitter apparatus 10 (hereinafter referred to as " transmitter ") is configured as via transmission Data message is transmitted to receiver device 12 (hereinafter referred to as " receiver ") by channel 11.

According to some embodiments of the present invention, transmitter 10 can include error correcting code (ECC) encoder 103, it is configured For the digital input data block 101 represented by u is encoded into code word c using linear block error.Receiver 12 can be configured To receive the noise copy p of coded data or code word by transmission channel 11.Receiver 12 can include error-correcting code decoder 123, it is configured as the estimation using digital output data block 125 as original figure input block 101To convey.

Digital input data 101 can be compressed in advance before being encoded by ECC encoder 103.Gulped down suitable for increase information Any source code scheme (not shown in figure 1) for the amount of spitting can be used for performing compression.The data encoded by ECC encoder 103 can Further to be modulated by modulator 105.Modulator 105 can be configured as by coded data be mapped to analog signal s and by its It is mapped on transmission channel 11.

Receiver 12 can include being configured as the homologous processing unit for performing negative function.It can include demodulator 121, it is configured as the solution that signal p is received by being performed before ECC decodings are carried out by ECC decoder 123 from transmission channel Transfer generation signal y.Demodulator 121 can be configured as the signal that will be received or channel output mobile backs into base band simultaneously Perform low-pass filtering, sampling and quantization.It can be further decompressed being solved by ECC using any source decoder (not shown in figure 1) Code 123 decoded data of device.ECC decoder 123 can be configured as realize according to various embodiments of the present invention be related to it is more The iterative decoding algorithm of a code check node processing unit.

In application of the present invention in the wired communication system of such as computer network system, transmitter 10 and/or reception Machine 12 can be configured as any equipment operated in cable network.Example devices in this applications include connection To the computer of small area or large area cable network, router or interchanger.In addition, in this applications, transmission channel 11 It can be for ensuring that any kind of physical cables that data are transmitted between the equipment of different connections.

In the present invention in the wireless of such as ad hoc deployed wireless networks, wireless sensor network and radio communications system etc In the another application of communication system, what transmitter 10 and/or receiver 12 can be configured as working in wireless environments appoints The fixation of what type or mobile wireless device.Include laptop computer, tablet meter suitable for the example devices of this application Calculation machine, mobile phone, robot, IoT equipment, base station etc..Transmission channel 11 can be suitable for appointing for such application What wireless propagation medium.In addition, transmission channel 11 can accommodate multiple transmitters 10 and receiver 12.In such embodiment In, multiple access technology and/or network coding technique can be applied in combination with error correcting code.Exemplary multiple access technology includes time division multiple acess (TDMA), frequency division multiple access (FDMA), CDMA (CDMA) and space division multiple access (SDMA).

In another application of the present invention in the optical communication system such as system based on optical fiber, transmitter 10 and receiver 12 can be arranged to send and receive any optical transceiver equipment for the data message propagated by optical link respectively.Example Property optical communication system include polarization point multiplexing (PMD) and mode division multiplexing (MDM) system.

For any kind of wired (such as based on optical fiber), wireless or deep space is (for example, satellite, telescope, space exploration Device etc.) communication system, transmission channel 11 can be any noisy channel.Noise is probably the thermal noise due to system component Or the interference intercepted by antenna is radiation-induced.Other exemplary noise sources include switching, manual interruption, electric spark and sudden strain of a muscle Electricity.In certain embodiments, overall noise can be modeled by additive white Gaussian noise (AWGN).

In addition, another application in digital mass-memory unit according to the present invention, transmission channel 11 can be such as Modeled by erasure channel, binary symmetric channel or Gaussian channel.In this applications, transmission channel 11 can be any class The storage device of type, it may be sent to that and (that is, write) and receive from it and (that is, reads).

Transmitter 10 and receiver 12 can be equipped with individual antenna or mutiple antennases.Especially, there are multiple transmittings And/or in the case of reception antenna, Space Time Coding and decoding technique can be used in combination with Error Correction of Coding and decoding.

In addition, coded data can be sent on one or more frequency bands.When coded data is sent over a plurality of bands, Modulator 105 can use the multi-carrier modulation lattice of such as OFDM (Orthogonal Frequency Division Multiplexing) and FBMC (filter bank multi-carrier) Formula.

According to various embodiments, ECC encoder 103 can realize byThe linear block error specified；N and k points Zhi Dai not the length of code word and the length of coded data block.ECC encoder 103 correspondingly encodes the message vector u that length is k For code word c, c is the vector that length is n.Therefore, code word c includes n element, also referred to as " symbol ".In n symbol, n-k Symbol corresponds to redundant symbol, also referred to as " parity check symbol ".The function of additional parity symbol is to allow receiver 12 Detect and any mistake occurred during the transmission may be corrected.

For the liner code constructed on Galois Field, usually represented with GF (q), wherein q >=2 represent the radix of code, symbol Number take the value in GF (q).Therefore, code word c is the vector of each n symbol for belonging to GF (q).If symbol belongs to GF (2), Then code is " binary system ".On the contrary, work as q>When 2, code is defined as " nonbinary ".

Liner codeIt can use by the G generator matrixes represented and the parity matrix represented by H with matrix Form represents.Using the row symbol of vector, the size of generator matrix G is k × n, and the size of parity matrix is (n-k) xn.Two matrixes pass through relation G.H^t=0 link.In addition, the entry of two matrixes belongs to corresponding Galois Field.Use square Matrix representation, any code word c meet equation c.H^t=0.The equation is also referred to as " parity check equation ".It, which is defined, is designed as by appointing What code word is come n parity check constraint meeting.

It is associated with matrix expression, the bipartite graph for being known as " Tanner figures " can be usedTo represent liner code The figure includes n variable node and n-k check-node.Each variable node i ∈ { 1,2 ..., n } and parity matrix Row are associated.Each check-node j ∈ { 1,2 ..., n-k } are associated with the row of parity matrix, i.e., with even-odd check side Journey is associated.If the entry H of parity matrix_ijNot equal to zero, i.e., if H_ij≠ 0, then variable node i be connected to verification Node j.Expression is connected to the set of neighbours' check-node of variable node i.Similarly,Expression is connected to school Test the set of the adjacent variable node of node j.(level (degree) for being equivalent to check-node j) corresponds to set to variable node iRadix (cardinality) (equivalent to setRadix).

Some embodiments will be carried out with reference to using the ECC encoder 103 that nonbinary LDPC code encodes data It is described below, the purpose being merely to illustrate.However, the person skilled in the art will easily understand various embodiments of the present invention Suitable for other nonbinary codes, and it is commonly available to binary system and nonbinary linear block error and nonbinary Turbo codes.

For illustrative purposes, ECC decoder 123 realizes nonbinary LDPC code decoder, for using nonbinary LDPC code decodes the data encoded by ECC encoder 103.ECC decoder 123 can realize that such as extension is minimum and calculates Any iteration nonbinary LDPC code decoder of method or min-max algorithm etc.

According to the application-specific of EMS algorithms, various embodiments of the present invention provide the iterative decoding mistake using EMS algorithms Efficient and low complex degree the realization of code check node processing unit involved in journey.Description of the invention is carried out with reference to EMS algorithms. However, those skilled in the art will readily appreciate that, various embodiments are suitable for such as any of min-max decoding algorithm and change For nonbinary LDPC code decoder.

With reference to figure 2, the iteration nonbinary LDPC decoder 123 according to some embodiments using EMS algorithms is shown Structure.

Iterative decoder 123 can be configured as from the noise sequence y that receives and determine code word c that transmitter 10 launches EstimationIt can handle signal in iteration several times, make it in each iteration closer to the code word c sent.

Iterative decoder 123 can be configured as based on the code used at transmitter 10Tanner charts Show to determine estimationTherefore, iterative decoder 123 can include n variable node processing unit 217 and n-k check-node Processing unit 215.Each variable node processing unit 217 is mapped to a variable node in Tanner figures.Each verification section Point processing unit 215 is mapped to a check-node in Tanner figures.Variable node processing unit 217 and code check node processing Unit 215, which can be configured as, iteratively exchanges message to estimate most reliable code word from noise sequence y

It can be configured as corresponding to the variable node processing unit 217 of variable node i from setVerification section Point processing unit 215 receives input message.Variable node processing unit 217 can be additionally configured to handle these input message simultaneously Output message is delivered to setAt least one code check node processing unit 215.

Similarly, can be configured as corresponding to the code check node processing unit 215 of check-node j from set's Variable node processing unit 217 receives input message.Code check node processing unit 215 can be additionally configured to handle these inputs Output message is simultaneously delivered to set by messageAt least one variable node processing unit 217.

It can be held according to a variety of dispatching techniques to realize by various variable node processing units and code check node processing unit Capable processing.

According to the first implementation, all variable node processing units 217 can be configured as to be operated in the first round, so Code check node processing unit 215, which can be configured as renewal, afterwards will be sent to the message of variable node.This specific scheduling quilt Referred to as " flooding scheduling ".Especially, code check node processing unit 215, which can be configured as, serially or parallelly operates, wherein from 2 It can be operated at the same time to n-k code check node processing unit 215.

According to the second implementation based on " level scheduling ", code check node processing unit 215 can be configured as serially Operation, renewal are connected to all variable node processing units 217 of code check node processing unit 215.Especially, one group of verification section Point processing unit 215 can be configured as parallel work-flow, the variable node processing unit 217 of all connections be updated, as long as not depositing Variable node processing unit 217 in collision is (for example, when two code check node processing units 215 are connected to identical variable During endpoint processing unit 217).

According to the 3rd implementation based on " vertical scheduling ", variable node processing unit 217 can be configured as serially Ground operates, and updates all code check node processing units 215 being connected with them.

The exchange of message can be initialized by variable node processing unit 217.If the signal of processing meets even-odd check Equation, or if reaching maximum iteration in the case where being unsatisfactory for all parity check constraints, it can be terminated. Under the previous case (if the signal of processing meets parity check equation), iterative decoder 123 can be configured as delivering Estimation of the signal as original code word after processing.In the latter case (if being unsatisfactory for all parity check constraints Situation is issued to maximum iteration), then iterative decoder 123 can be configured as statement decoding failure, but still export most The code word of an iterative estimate afterwards.

As shown in Fig. 2, iterative decoder 123 can also include the storage unit for being configured as the sequences y that storage receives 211.Iterative decoder 123 can also include processing unit 213, it is configured as based on the reception loaded from storage unit 211 To sequences y determine the initial value of output message delivered by variable node processing unit 217.

The message exchanged between variable node processing unit 217 and code check node processing unit 215 can carry and symbol Associated information.Set is sent to from variable node processing unit 217 corresponding with variable node iIn with verification save The message of the corresponding code check node processing units 215 of point j is by U_iRepresent.Similarly, from check-node corresponding with check-node j Processing unit 215 is sent to setIn variable node processing unit 217 corresponding with variable node i message by V_i Represent.

According to some embodiments, the length of the message of exchange can be equal to the rank for the Galois Field for being used to construct liner code. Therefore, the message U each exchanged_iAnd V_iCan be that the length of the code constructed on GF (q) is the vector of q.

With in the relevant other embodiment of soft-decision decoding, the message of exchange can carry symbol and measurement symbol is reliable The value of the measurement (hereinafter referred to as " degree of reiability ") of property.The value of degree of reiability is related with the reliability of symbol.Such In embodiment, each message U_iAnd V_iCan include vectors (hereinafter referred to as " component ") of the q to value, component include symbol and its The value of degree of reiability.Therefore, each component of message correspondingly corresponds to a pair of of value, including：

The value of symbol in-GF (q), and

- degree of reiability.

In certain embodiments, the degree of reiability of symbol can correspond to represent estimating for the symbol of the correct probability of symbol Count probability density function.Especially, degree of reiability can be represented in log-domain by log-likelihood ratio (LLR) value.

The calculating that the computation complexity of decoding process is performed by code check node processing unit 215 dominates.Using EMS algorithms In the one embodiment for decoding nonbinary LDPC code, the computation complexity of the processing performed by code check node processing unit 215 It can reduce without sacrificing decoding error performance.

With reference to figure 3, the block diagram of code check node processing unit 215 according to some embodiments of the present invention is shown.Verification Endpoint processing unit 215 and level d_jCheck-node j be associated.Code is represented this means corresponding check-node is connected to D in Tanner figures_jA variable node.Therefore, code check node processing unit 215 can be configured as with d_jA connection The d that variable node is associated_jOne or more of a variable node processing unit 217 variable node processing unit 217 exchanges Message.Therefore, in given iteration, code check node processing unit 215, which can be configured as, receives d_jIt is a input message and Generate at least one output message.Input or output message are to include the vector of q component, and each component includes symbol and its can By property measurement.Input message may be sorted and/or block.

For the ease of the understanding described below to some embodiments, will focus on using in code check node processing unit Processing at the code check node processing unit of symbol at level.Therefore, the code check node processing unit 215 shown in Fig. 3 can have Be configured as receive byThe d of expression_jThe level d of a input message_j, and generate byThe d of expression_jA output message.The level of code check node processing unit 215 can be by d_j>=3 advantageously provide.

According to some embodiments using EMS algorithms, being delivered to the message of code check node processing unit 215 can be sorted With block, only to keep n_{M, in}A most reliable component, wherein n_{M, in}Strictly it is less than q (n_{M, in}＜＜ q).Sequence can be with The given order (such as by increase order or reduction order) of the degree of reiability associated with symbol performs.In addition, sequence It can be held with break-in operation by variable node processing unit 217 or reception message code check node processing unit 215 as input OK.

By with reference to the sequence using the input message received based on code check node processing unit 215 and the soft output solution blocked Some embodiments of code are described below, the purpose being merely to illustrate.In such embodiments, message U is each inputted_iIt is It is U including form_i=(U_i[0], U_i[1] ..., U_i[n_{M, in}- 1] n)_{M, in}The vector of a component, and each output message V_i It is that to include form be V_i=(V_i[0], V_i[1] ..., V_i[n_{M, out}- 1] n)_{M, out}≥n_{M, in}The vector of a component.For j= 0 ..., n_{M, in}- 1 componentIncluding byThe symbol of expression, Yi JiyouTable The degree of reiability that the symbol shown is associated.The component of each input message can be ranked up so that including most reliable The component of symbol corresponds to component U_i[0], wherein i=1 ..., d_j, andWherein j=0 ..., n_{M, in}-2。

With reference to figure 3, code check node processing unit 215 can contain at least two basic check node processors 311 syndrome calculator 31.Especially, the code check node processing unit 215 of level dj can include d_j- 1 basic verification section Point processor 311.Each basic check node processor 311, which can be configured as from first message and second message, determines centre Message, first message and second message are derived from input message.By U '_tThe intermediary message of expression can include quantity n_tIt is a The component of sequence and the intermediate binary associated with each component vector, are included in the component in given intermediary message according to it The given order of the degree of reiability of the symbol included is ranked up.

Syndrome calculator 31 can be configured as to be determined by S={ S from all input message₁, S₂..., S_NSRepresent One group of NS syndrome.More specifically, syndrome calculator 31 can be configured as by handle it is all input message come from by The intermediary message that check node processor 311 calculates determines verification subclass.For r=1 ..., NS, byThe syndrome of expression can include byGF (q) symbols of expression, it is associated with the symbol simultaneously It is expressed asDegree of reiability and byThe binary vector of expression.

Syndrome is calculated using basic check node processor 311, it is possible to reduce the decoded computation complexity of syndrome. In fact, by using basic check node processor 311, reduce the number of the syndrome of calculating for determining output message Amount, so that using the decoded concurrency of syndrome, while mitigating computation complexity, computation complexity is often as High quantity is calculated caused by syndrome.In addition, basic check node processor 311 provides sequence in the intermediary message calculated Component (order for depending on the degree of reiability of symbol).As a result, the row routinely applied after syndrome computation can be eliminated Sequence operates, so as to reduce the computation complexity needed for sequencer procedure and reduce cost of implementation.

According to some embodiments, the quantity of syndrome NS can be greater than or equal to the number of the component in each input message Amount, and the order of Galois Field can be depended on.

For example, in GF (64), the quantity of syndrome can be by NS=3n_{M, out}=9n_{M, in}Provide, in each output message Including the quantity of component be generally equal to n_{M, out}=20.

In another example for considering GF (256), the quantity of syndrome can be by NS=3n_{M, out}=25n_{M, in}Provide, The quantity for the component that each output message includes is generally equal to n_{M, out}=60.

In addition, in another example of GF (1024), the quantity of syndrome can be by NS=3n_{M, out}=45n_{M, in}Provide, The quantity for the component that each output message includes is generally equal to n_{M, out}=150.

According to some embodiments, each basic check node processor 311 can be configured as by being included in first Symbol in the component of message and the add operation on the symbol application Galois Field being included in the component of second message To determine to be included in the symbol in the component of intermediary message.

In addition, each basic check node processor 311 can be configured as by the component to being included in first message In degree of reiability and the given Algebraic Structure of degree of reiability application that is included in the component of second message on plus Method computing determines the degree of reiability associated with the symbol in the component for being included in intermediary message.

, can be in the domain by real number according to some embodimentsThe domain of integerWith the domain of natural numberSelected in the group of composition Select Algebraic Structure.

For example, in the hardware realization and software of quantization are realized, each basic check node processor 311 can be configured For by integer fieldOr natural number fieldOn using add operation determine the symbol phase included with the component of intermediary message Associated degree of reiability, reduces complexity.

According to some embodiments, syndrome calculator 31 can be additionally configured to initial binary value and input message U_i The each component U included_i[j] is associated, wherein i=1 ..., d_jAnd j=0 ..., n_{M, in}-1。

According to some embodiments, syndrome calculator 31 can be configured as according to degree of reiabilityTo initial value With componentIt is associated.Especially, syndrome calculator 31 can be configured as to the component including most reliability symbols with Initial binary value equal to predefined first value is associated, and to residual components with being equal to predefined second value Initial binary value is associated.

According to some embodiments, predefined first value can be equal to zero (' 0 '), and predefined second value can wait In one (' 1 ').In such embodiments, with component U_i[j] associated binary value can be byRepresent, and It can be given by：

Consider the input message after sequence, conditional equality (1) shows, if the symbol being included in the component is most may be used The symbol leaned on, then be endowed the value of bit ' 0 ' with the associated initial binary value of component being included in input message.

According to other embodiment, predefined first value can be equal to one (' 1 '), and predefined second value can wait In one (' 0 ').Therefore, if the symbol being included in the component is most reliable symbol, with being included in input message The initial binary value that component is associated can be equal to bit ' 1 ', i.e.,

Therefore, the first message and each component of second message handled by given basic check node processor 311 Can with derived from initial binary value binary vector it is associated.In such embodiments, each basic check-node Processor 311 can be configured as by the application binary vector associated with the component of first message and with second message The vector for the binary vector that component is associated is cascaded to determine the intermediate binary vector associated with the component of intermediary message.

Especially, basic check node processor 311 can be configured as from two input message determine intermediary message and The intermediate binary vector associated with each component of intermediary message, first message and second message are respectively equal to the first input Message and the second input message.

In order to illustrate calculating of the basic check node processor 311 to intermediary message, input message will be equal to reference to processing First message and second message be described below.Fig. 4 shows the basic check node processor according to this embodiment 311.Therefore, basic check node processor 311 can be configured as the input message of processing first U_lWith the second input message U_p, Wherein l and p ≠ l arrives d 1_jIndex set in change.Each include symbol and its n of degree of reiability from the two_{M, in} The input message of a component, basic check node processor 311, which can be configured as, to be determined to include number n_tA componentU '_tThe intermediary message of expression, and with each component U '_t[j] determines table in association It is shown asIntermediate binary vector., can be according to given according to the degree of reiability for the symbol being included therein Order is ranked up the component of intermediary message so that for all j=0 ..., n_t- 2,

According to some embodiments, basic check node processor 311 can be configured as comes from first message by processing U_lQuantity n_l≤n_{M, in}Component and/or from second message U_pQuantity n_p≤n_{M, in}Component determine intermediary message.

According to wherein first message and second message some embodiments different from input message, that is, correspond in framework The intermediary message delivered by previous basic check node processor 311, from the quantity n of the component of first message processing_lAnd/or From the quantity n of the component of second message processing_pThe component that can correspond to previously to have been delivered by basic check node processor 311 Quantity.In other words, the quantity of the component handled by given basic check node processor 311 can depend on being included in by The quantity of the component in intermediary message before the basic check node processor processing of previous stage in framework.

According to some embodiments, basic check node processor 311 can be configured as according to three steps come determine in Between message U '_t。

In the first step, basic check node processor 311 can be configured as from first message U_lComponent and Two message U_pComponent determine one group of auxiliary output component.Output component is aided in be known as " bubble (Bubble) ".By B_t[u] [v] table The bubble shown refers to from being included in first message U_lIn component U_l[u] and it is included in second message U_pIn component U_p[v] is obtained Bubble.U is indexed in 0,1 ..., n_lChange in -1, index v is in 0,1 ..., n_pChange in -1.Bubble includes a pair of of data, bag Include：

- byThe symbol of expression, and

- byRepresent its degree of reiability, and with this to it is associated byRepresent Binary vector.The sum of bubble is therefore by n_l×n_pProvide.

According to some embodiments, basic check node processor 311 can be configured as by the structural domain in error correcting code I.e. on Galois Field GF (q) auxiliary output component B is determined using add operation_tThe symbol of [u] [v]Addition is transported Calculation is applied to be included in first message U_lComponent U_lSymbol in [u]Be included in the second processed message U_p Component U_pSymbol in [v]So that：

In equation (2), operatorRepresent the add operation on Galois Field.

According to some embodiments, basic check node processor 311 can be configured as by first message U_lPoint Measure U_lIncluded degree of reiability in [u]And to second message U_pComponent U_pIncluded reliability degree in [v] AmountIn given Algebraic Structure auxiliary output component B is determined using add operation_tThe degree of reiability of [u] [v]So that：

According to some embodiments, basic check node processor 311 can be configured as by the vectorial cascade operation of application Come with aiding in output component B_t[u] [v] determines intermediate binary vector in associationVectorial cascade operation can With applied to first message U_lComponent U_l[u] associated binary vectorWith with second message U_pComponent U_p[v] associated binary vectorSo that：

In equation (4), operator | | cascade operation is represented, it is provided from two or more input scalars or vector is in The list of vector form, the element of list are equal to cascade and input.

In the second step, basic check node processor 311 can be configured as the symbol included according to these components Number degree of reiability given order to identified n_l×n_pA auxiliary output component is ranked up.

In third step, basic check node processor 311 can be configured as in n_l×n_pThe auxiliary output of a sequence Selection includes the n of most reliability symbols in component_tA component, it provides intermediary message U '_tWith the n included with the intermediary message_tIt is a The binary vector that each component of component is associated.

In addition, the quantity n for the component being included in intermediary message_tN can be less than_l×n_p。

What the quantity of basic check node processor 311 can depend on using at syndrome calculator realizes framework.

According to some embodiments, syndrome calculator 31 can include the multiple basic check-nodes realized with serial frame Processor 311.

Fig. 5 shows the structure for the syndrome calculator 31 for realizing serial frame.Therefore, for level d_jCheck node Unit 215 is managed, syndrome calculator 31 can include d_j- 1 basic check node processor 501-l, wherein l=1 ..., d_j- 1.Especially, syndrome calculator 31 can include basic check node processor 501-1, it is configured as by handling two Input message U₁And U₂To determine intermediary message and the intermediate binary associated with each component of intermediary message vector.It is remaining Basic check node processor 501-l (wherein l=2 ..., d_j- 1) can be configured to disappear by handling an input Breath and basic check node processor 501-a (wherein a=1 ..., the l- previously operated by the previous stage in serial frame 2) a definite intermediary message come determine intermediary message and the intermediate binary associated with each component of intermediary message to Amount.

According to some other embodiments, syndrome calculator 31 can include with parallel architecture (hereinafter referred to as " tree framework ") The multiple basic check node processors realized.In such embodiments, syndrome calculator 31 can include at least one Basic check node processor 311, it is configured as determining intermediary message by handling two input message and with centre disappearing The intermediate binary vector that each component of breath is associated.Remaining basic check node processor 311 can be configured as logical Cross two input message of processing or by handling in advance by two basic check-nodes of the stages operating before tree framework Two definite intermediary messages of processor 311 determine intermediary message and the centre two associated with each component of intermediary message System vector.

Fig. 6 shows the level d for realizing tree framework_jThe structure of=8 syndrome calculator 31.As shown in the figure, parallel architecture Including 3 stages (hereinafter referred to as " layer ").The basic check node processor 601 for being included in first layer can be configured as each Intermediary message is determined by handling two input message.Being included in basic check node processor 603 at the second layer can be with Each it is configured as determining by handling two intermediary messages delivered by the basic check-node 601 in the first layer of framework Intermediary message.Being included in the basic check node processor 605 at third layer can each be configured as by handling by framework The second layer in two intermediary messages delivering of basic check-node 603 determine intermediary message.

According to some other embodiments, syndrome calculator 31 can include the multiple basic verifications realized with mixed architecture Modal processor 311, mixed architecture are mixed with serial frame and tree framework, as shown in figure 14.In such embodiments, school Testing sub- calculator 31 can include：At least one basic check node processor 141, is configured as disappearing by handling two inputs Breath is vectorial to determine intermediary message and the intermediate binary associated with each component of intermediary message, and at least one basic Check node processor 143, is configured to by handling input message and the basic verification by the previous stage positioned at mixed architecture The intermediary message that modal processor 141 generates determines intermediary message and the centre two associated with each component of intermediary message System vector.

Framework, syndrome calculator are realized regardless of the basic check node processor 311 in verification sub-decoder 31 can be configured as basis delivers from the last basic check node processor 311 in the frameworks that all input message obtain Intermediary message determine the set S={ S of NS syndrome₁, S₂..., S_NSIn each syndrome

For example, in the embodiment using serial implementation as shown in Figure 5, can be from by basic check node processor 501-d_jThe intermediary message of -1 delivering determines the verification subclass.

In another example realized using tree, as shown in fig. 6, can be from the basic school of the final stage positioned at tree framework Test modal processor 605 delivering intermediary message come determine verify subclass.

Therefore, it is included in syndrome S_rSymbol in (wherein r=1 ..., NS)It can be expressed as inputting according to the following formula The function for the symbol that message includes：

In equation (5), for i=1 ..., d_jEach index u_iIn set { 0,1 ..., n_{M, in}- 1 } change in.

In addition, and symbolAssociated degree of reiabilityThe difference point of input message can be expressed as according to the following formula The function for the degree of reiability that amount includes：

In addition, it is included in syndrome S_rIn binary vectorIt can be written as and input each component of message The function of associated initial binary value, it is such as identified according to the following formula by syndrome calculator 31：

According to equation (7), it is included in syndrome S_rIn binary vectorIncluding d_jA bit.

Code check node processing unit 215 can also include correlated elements 33, it is configured as and each output message V_i Determined in association from identified NS verification subclass S by V '_iThe one group of candidate components represented.Each candidate components include Symbol and the degree of reiability associated with the symbol.

According to some embodiments (shown in Fig. 3), correlated elements 33 can include d_jA basic correlated elements 313-i, Wherein i=1 ..., d_j, each basic correlated elements 313-i and output message V_iIt is associated and is configured as basis and is included in The binary vector in each syndrome in verification subclass S determines this group of candidate components V '_i.Referred to as abandon binary system The binary vector of vectorial (DBV) therefore can serve to indicate that syndrome should be dropped for which exports edge, with And therefore do not selected by correlated elements 33.More specifically, basic correlated elements 313-i can be configured as by really Selection includes binary vector in fixed verification subclass S Syndrome come determine with each output message V_iOne group of associated candidate components V '_iSo that with output message V_iAssociated BitEqual to specified value.It can be tested using the reading for the bit being included in the binary vector in syndrome Card or the selection for not verifying syndrome, to determine the one group candidate components associated with given output message.Therefore, Mei Geji This correlated elements 313-i can be configured as to be determined from the symbol and its degree of reiability being included in selected syndrome One group of candidate components V '_i, candidate components are corresponding to the component being included in the syndrome of empirical tests.

According to embodiment, basic correlated elements 313-i can be configured as by identified verification subclass S Selection includes binary vectorSyndrome come determine with it is every A output message V_iOne group of associated candidate components V '_iSo that with output message V_iAssociated bitEqual to zero (‘0’)。

According to another embodiment, basic correlated elements 313-i can be configured as by identified syndrome Selection includes binary vector in set SSyndrome come Determine and each output message V_iOne group of associated candidate components V '_iSo that with output message V_iAssociated bitEqual to one (' 1 ').

According to some realities for the serial frame that basic check node processor 311 is used wherein in syndrome calculator 31 Example is applied, correlated elements 33 can be simplified, and can include d_j- 1 elementary solution relevant unit 313-i, wherein i= 1 ..., d_j-1。

Fig. 7 is the block diagram for the structure for showing code check node processing unit 215 in accordance with some embodiments, wherein decorrelation list Member 73 includes d_j- 1 basic correlated elements 713-i, wherein i=1 ..., d_j- 1, basic correlated elements 713-i is configured For with output messageOutput message V_iOne group of candidate components V ' is determined in association_i.In such reality Apply in example, the basic check node processor 711-d of penultimate that can be from by serial frame_jThe intermediary message of -2 generations Definite and output messageThis group of associated candidate componentsWithout performing decorrelation step.Can so it do, because The basic check node processor 711-d of penultimate_jThe intermediary message of -2 deliverings is not included previously from input messageWill be by The input message that the variable node processing unit 217 being sent to receivesContribution.As a result, in such embodiments, no Need to determine and output message using decorrelation stepThis group of associated candidate components, so as to cause check node Manage the simpler structure of unit 215.

Code check node processing 215 can also include selecting unit 35, it is configured as according to this group of candidate components V '_iMiddle bag The degree of reiability of the symbol included, by from this group of candidate components V '_iIt is middle to select the component for including distinct symbols each to determine Output message V_i.Therefore, selecting unit 35 can be configured as from this group of candidate components V ' including redundant symbol_iIn component Retaining includes the component of most reliable distinct symbols.

According to some embodiments, selecting unit 35 can be configured as by according to this group of candidate components V '_iInclude The degree of reiability of symbol come from output message V_iThis group of associated candidate components V '_iMiddle selection predetermined quantity n_{M, out}Point Measure to determine each output message V_i.Therefore, selecting unit 35 can be first configured in one group of candidate components V '_iMiddle execution Redundancy eliminates, for retaining in the component including same-sign (that is, in the component including redundant symbol) including most reliable The component of symbol.In the second step, selecting unit 35 can be configured as the symbol included according to the candidate components of processing Degree of reiability to select predetermined quantity n from handled candidate components_{M, out}Component so that including most reliable difference The n of symbol_{M, out}A component is chosen.

According to some embodiments, the selecting unit 35 realized in various code check node processing units 215 can be configured To select identical predefined quantity n_{M, out}Component determine output message.

According to other embodiment, the selecting unit 35 realized in various code check node processing units 215 can be configured To select different predefined quantity n_{M, out}Component determine output message.In such embodiments, these output messages 217 recipient of variable node processing unit can be configured as and perform break-in operation to retain phase in the message of each reception With the component of quantity.

In certain embodiments, the predetermined quantity n of component_{M, out}It can depend on the quantity for the component that input message includes n_{M, in}。

The predetermined quantity n of component_{M, out}It might also depend on the domain that code is constructed, and/or the decoding of iterative decoding procedure The order of iteration, and/or signal-to-noise ratio, and/or calculating and the storage capacity of code check node processing unit 215.

In some other embodiments, the quantity n of component_{M, out}It can depend on the combination of previously cited factor.

For example, for the Galois Field on GF (64), the quantity n of component_{M, out}May be according to n_{M, out}=3n_{M, in}And with input The quantity for the component that message includes is related.For the Galois Field on GF (1024), the quantity n of component_{M, out}Possible basis n_{M, out}=15n_{M, in}It is and related with the quantity for the component that input message includes.

Fig. 8 is to describe basis to perform wherein at code check node processing unit using multiple basic check node processors Verified in some decoded embodiments of syndrome for carry out realizing in decoded EMS algorithms to nonbinary LDPC code The flow chart of the method for output message is determined at endpoint processing unit.

Carried out the soft output decoder represented by log-likelihood ratio (LLR) value in log-domain and degree of reiability is referred to Some embodiments are described below, the purpose being merely to illustrate.However, those skilled in the art will readily appreciate that, can make The reliability of symbol is measured with other kinds of decoding and degree of reiability.

The method that output message is calculated at code check node processing unit is performed in the iterative decoding procedure of EMS algorithms Message exchange a part.It can be handled with perform decoding, to be represented by application belief propagation decoding rule from by vectorial y The noise sequence received determine the estimation of original code word cCode word c may at transmitter use in Galois Field Constructed on GF (q)The nonbinary LDPC code specified is encoded, wherein q ＞ 2.

For the sake of clarity, it will focus mainly on and some embodiments carried out the step of code check node processing unit performs It is described below.It will consider to be configured as receiving d below_jInput message that is a ranked and blockingIt is and raw Into d_jA output messageLevel d_jCode check node processing unit.

Step 801 can be performed to receive input message from the variable node of the connection in corresponding Tanner figures.Therefore, D can be received_jA input messageInputting message can be saved by variable node processing unit or verification in advance Point processing unit is ranked up and blocks.Therefore, each input message can be included to be included in the reliability in each component The n of the given order sequence of measurement_{M, in}＜＜ q components.

Wherein LLR be measure symbol reliability measurement specific embodiment in, most reliable symbol be have most The symbol of small LLR value.Therefore, message U is each inputted_iCan be according to U_i=(U_i[0], U_i[1] ..., U_i[n_{M, in}- 1]) with vector Symbol writes so that each component(wherein j=0 ..., n_{M, in}- 1) include by The symbol of expression, and it is associated with symbol byThe LLR measurements of expression so that carry the component pair of most reliability symbols Should be in component U_i[0], wherein i=1 ..., d_j, wherein for each 0≤u ＜ v≤n_{M, in}- 1,

Step 803 can be performed with by initial binary value and input message U_i(wherein i=1 ..., d_j) include it is every A component U_i[j] (wherein j=0 ..., n_{M, in}- 1) it is associated.

According to some embodiments, with component U_i[j] associated initial value can depend on degree of reiabilityIt is special Not, the initial binary value equal to predefined first value can be associated with the component including most reliability symbols, and waits Can be associated with remaining component in the initial binary value of predefined second value.

According to some embodiments, predefined first value can be equal to zero (' 0 '), and predefined second value can wait In one (' 1 ').Therefore, with component U_i[j] it is associated byThe initial binary value of expression can be according to equation (1) Determine, i.e. if the symbol that the component includes is most reliable symbol, with being included in input message U_iIn component U_i [j] associated initial binary valueBit ' 0 ' can be taken.

According to other embodiment, predefined first value can be equal to one (' 1 '), and predefined second value can wait In zero (' 0 ').Therefore, if the symbol being included in the component is most reliable symbol, with being included in input message The initial binary value that component is associated can be equal to bit ' 1 ', i.e.,

Step 805 can be performed to determine to include NS from input message using multiple basic check node processors 311 A syndrome by S={ S₁, S₂..., S_NSRepresent one group of syndrome.Syndrome(wherein R=1 ..., NS) can include byThe symbol of expression, it is associated with symbol and byThe LLR measurements of expression, Yi JiyouThe binary vector of expression.

According to some embodiments, the quantity NS of the syndrome in verification subclass S can be greater than or equal to each input and disappear The quantity of component in breath.For example, on GF (64), verification quantum count can be by NS=3n_{M, out}=9n_{M, in}Provide.

According to some embodiments, the verification subclass can be determined according to the intermediate result determined from all input message S。

By U '_tThe intermediary message of expression can include quantity n_tA ranking component and the centre two associated with each component System vector, be included in the component in given intermediary message be ranked into the symbol being included therein degree of reiability it is given Sequentially.Can by processing, first message and second message determine intermediary message derived from the input message, input message Quantity is advantageously at least equal to three.In addition, each component being included in first message and second message can be associated with from Binary vector derived from the initial binary value that the component of input message is associated.

Therefore, can be by being included in the symbol in the component of handled first message and being included in handled the Symbol in the component of two message determines to be included in the symbol in the component of intermediary message on Galois Field using add operation Number.

Furthermore, it is possible to by pair to LLR that the component of first message is associated measurement and related with the component of second message Add operation in the given Algebraic Structure of LLR measurement applications of connection is associated come the symbol for determining with being included in intermediary message LLR is measured.

, can be by real number field according to some embodimentsInteger fieldWith natural number fieldAlgebraically is selected in the group of composition Structure.For example, in the embodiment that hardware quantifies to realize or software is realized is related to, add operation can be in integer fieldIt is or natural Number fieldUpper execution.

Furthermore, it is possible to pass through the application binary vector associated with the component of first message and the component with second message The vector of associated binary vector is cascaded to determine the intermediate binary vector associated with the component of intermediary message.

For by handling respectively by U_lAnd U_p(wherein l and p ≠ l are from 1 to d_jIndex set in change) represent two Intermediary message determined by a input message, can determine by U ' from the component of input message_tThe intermediary message of expression.Can be from The initial binary value associated with each component of input message determines the centre associated with each component of intermediary message Binary vector.Therefore, intermediary message U '_tIt can include n_tA component U '_t[j] (wherein j=0 ... n_t- 1) and with each point Measure U '_t[j] associated intermediate binary vectorFor j=0 ... n_t- 1 componentIt can include symbolThe LLR measurement associated with symbolCan be with According to including symbol degree of reiability by intermediary message U '_tComponent be ordered as given order so that for institute Some j=0 ... n_t- 2,

, can be by handling the number n from first message according to some embodiments_l≤n_{M, in}A component and/or from The number n of two message_p≤n_{M, in}A component determines intermediary message.

According to some embodiments, intermediary message can be determined by three steps.

In the first step, can be from first message U_lComponent and second message U_pComponent determine the output of one group of auxiliary Component.Output component is aided in be known as " bubble ".By B_tThe bubble that [u] [v] is represented refers to from being included in first message U_lIn component U_l[u] and it is included in second message U_pIn component U_pThe bubble that [v] is obtained.U is indexed in 0,1 ..., n_lChange in -1, index v In 0,1 ..., n_pChange in -1.Bubble can include a pair of of data, this data are included byThe symbol of expression and ByIts LLR measurements represented.It can also include with this to it is associated byRepresent two into System vector.Correspondingly, the sum of bubble is exported by n_l×n_pProvide.

According to some embodiments, it is included in auxiliary output component B_t[u] [v] (wherein u=0,1 ..., n_l- 1 and v=0, 1 ..., n_p- 1) symbol inCan be according to the addition on the Galois Field previously represented in equation (2) come really It is fixed.

According to some embodiments, it is included in auxiliary output component B_t[u] [v] (wherein u=0,1 ..., n_l- 1 and v=0, 1 ..., n_p- 1) the LLR measurements inCan be according to the addition in the real number field such as previously represented in equation (3) To determine.

According to some specific embodiments, such as in the hardware realization and software of quantization are realized, it is included in auxiliary output point Measure B_t[u] [v] (wherein u=0,1 ..., nl-1 and v=0,1 ..., n_p- 1) the LLR measurements inCan be according to whole Number fieldOr natural number fieldOn addition determine, so as to the reduction of implementation complexity.

According to some embodiments, with aiding in output component B_t[u] [v] (wherein u=0,1 ..., n_l- 1 and v=0,1 ..., n_p- 1) associated binary vectorCan according to above in equation (4) represent vectorial cascade operation come Determine.

In n_l×n_pAfter the calculating of a auxiliary output component, sequence step can be performed by each component to include The incremental order of LLR measurements is ranked up these components.

In final step, break-in operation can be performed, with n_l×n_pN is selected in the auxiliary output component of a sequence_tA point Amount, it provides intermediary message U '_tWith with n included in the intermediary message_tEach component in a ranking component be associated two System vector.

According to some embodiments, it is included in the quantity n of the component in intermediary message_tN can be less than_l×n_p。

Verification subclass can be determined from the intermediary message calculated using all input message.

In the embodiment using serial frame, last basic code check node processing that can be from by serial frame The intermediary message of device delivering determines the verification subclass.

, can be from the basic code check node processing of the afterbody positioned at tree framework in the embodiment using parallel architecture The intermediary message of device delivering determines the verification subclass.

Independently of the type for realizing framework of each basic check node processor 311, subclass is verified(wherein r=1 ..., NS) can be represented as the function of input message.

Therefore, it is included in syndrome S_rSymbol in (wherein r=1 ..., NS)It can be expressed as according to equation (5) It is included in input message U_iIn symbolGalois Field on summation, wherein i=1 ..., d_jAnd u_i∈ [0, n_{M, in}-1]。

In addition, it is included in syndrome S_rLLR measurements in (wherein r=1 ..., NS)It can be represented according to equation (6) To be included in input message U_iIn LLR measurementReal number field on summation, wherein i=1 ..., d_jAnd u_i∈ [0, n_{M, in}-1]。

In addition, it is included in syndrome S_rBinary vector in (wherein r=1 ..., NS)Can be according to equation (7) it is expressed as input message U_iAssociated initial binary valueVector cascade, wherein i=1 ..., d_jAnd u_i ∈ [0, n_{M, in}-1].Therefore, it is included in syndrome S_rIn binary vectorIncluding d_jA bit, for i=1 ..., d_jEach binary valueWith output message V_iIt is associated.

Step 807 can be performed, to be determined and each output message V from definite verification subclass_iIt is associated by V '_i The one group of candidate components represented.Step 807 can include application and depend on being included in each syndrome S_rIn binary vectorDecorrelation operation.Therefore, binary vector can indicate abandon for which output message or selection check Son, to determine one group of candidate components.Due to binary vectorIncluding d_jA bit, for i=1 ..., d_jIt is each BitWith output message V_iIt is associated, bitValue can be used for verifying or do not verify syndrome S_rChoosing Select, to determine one group of candidate components V '_i。

More specifically, according to first embodiment, wherein the initial binary value associated with most reliability symbols is equal to ' 0 ' (such as in equation (1)), if bitEqual to zero (' 0 '), then syndrome S_rIt is effective syndrome.It is then possible to select Select including effective syndrome S_rSymbolAnd its LLR measurementsData pair, to form candidate point among candidate components Amount.

It is equal to ' 1 ' another embodiment according to the initial binary value associated with most reliability symbols, if bitEqual to one (' 1 '), then syndrome S_rIt is effective syndrome.It is then possible to select effective syndrome S_rSymbol And its LLR measurementsPair, to form the candidate components in this group of candidate components.

According to some embodiments, decorrelation operation can be performed with using d_jA elementary solution relevant operation come determine with it is each One group of candidate components V ' that output message is associated_i, each elementary solution relevant operation is executable to determine one group and given output The candidate components that message is associated.

According to some other embodiments usually using serial frame, d can be used only_j- 1 elementary solution relevant operation comes Perform decorrelation operation.Can from the intermediary message by the delivering of penultimate basic check node processor come determine with serially One group of candidate components that last basic check node processor in framework is associated.

In step 809, redundancy can be performed to the identified one group candidate components associated with each output message Operation is eliminated, to retain the component for including most reliability symbols corresponding with minimum LLR measurements from the component including same-sign. In other words, the component for producing same-sign value is processed so that point including the redundant symbol associated with minimum LLR measurements Amount is retained.

Step 811 can be performed to generate output message Vi, wherein i=1 ..., d from one group of candidate components of processing_j。 By selecting predefined quantity n from one group of handled candidate components_{M, out}Most reliable component, i.e. by selection include with The n of the associated symbol of minimum LLR measurements_{M, out}A component, it may be determined that output message V_i。

Fig. 9 show according to some embodiments of the present invention include handled by basic check node processor 311 it is every A n_{M, in}The two-dimensional matrix of two input message of=10 components represents.The expression, which corresponds to, includes n_l=n_{M, in}=10 points The first message of amount and including n_p=n_{M, in}The processing of the second message of=10 components.Vertical axis refers to first message Handle component.Trunnion axis refers to the processed component of second message.Each component from first message is with coming from second message The possibility combination of each component represented by gray circles, and be referred to as " bubble ".They correspond to auxiliary output component, i.e., Corresponding to the probable value of the component of the intermediary message determined from first message and second message.The quantity of bubble is represented in basic school Test at modal processor and relate to determining the computation complexity of output message.Fig. 9 corresponds to by tuple (n_l=n_{M, in}=10, n_p =n_{M, in}=10, n_t=10) the basic check node processor represented, last element wherein in tuple correspond to delivering Intermediary message number of components.Basic this of check node processor is configured similarly to S-Bubble and L-Bubble algorithms Used configuration.In the configuration that S-Bubble and L-Bubble algorithms use, first message and second message after processing Input component and the output component being included in definite intermediary message component set { 0 ..., n_{M, in}- 1 } taken in Value.

Figure 10 shows the exemplary bubble obtained according to some embodiments of the present invention, wherein being saved using basic verification Point processor handles the quantity n of second message_pComponent so that n_pLess than n_{M, in}.Therefore, basic check node processor by Tuple (n_l=10, n_p=3, n_t=10) represent.In this example, one group of candidate selected in 18 bubbles is by n_t= 10 provide.

Figure 11 shows the exemplary bubble obtained according to some embodiments of the present invention, wherein basic check node Reason device is configured as the quantity n of processing second message_pComponent so that n_pLess than n_{M, in}.Therefore, basic check node processor By tuple (n_l=10, n_p=5, n_t=20) represent.It should be noted that compared with the result of Figure 10, (35 pairs of the quantity higher of bubble 18)。

Figure 12 is shown according to some embodiments, uses 10 of the message exchange procedure between variable node and check-node Secondary iteration, to be carried out to (576,480) the nonbinary LDPC code built using EMS algorithms under awgn channel on GF (64) The error probability performance that the mode of decoded frame error ratio (FER) is assessed.Four realizations to EMS algorithms have carried out FER assessments：

1、‘FBn_m=20 ' (in fig. 12, n_mRepresent n_{M, in}) refer to using the prior art based on S-Bubble algorithms The embodiment of framework backward forward, wherein using by (n_l=20, n_p=20, n_t=20) the basic check node processor represented.

2nd, ' SB-CN, serial NS=50, n_{M, in}=6, n_{M, ou}T=20 ' refers to some embodiments of the present invention, wherein using The serial implementation of 11 basic check node processors 311 in syndrome calculator 31.Corresponding serial implementation include by Tuple (n_l=6, n_p=6, n_t=25) represent basic check node processor 311 and by tuple (n_l=6, n_p=25, n_t= 50) the basic check node processor 311 represented.Remaining 9 basic check node processors 311 are by tuple (n_l=6, n_p= 50, n_t=50) represent.

' SB-CN, sets NS=50, n_{M, in}=6, n_{M, out}=20 ' refer to some embodiments of the present invention, wherein using verification The tree of 11 basic check node processors 311 in sub- calculator 31 is realized.Corresponding tree realization is included in the first order (i.e. table Show the rank in the tree of Parallel Implementation) by tuple (n_l=6, n_p=6, n_t=25) the 6 basic check node processors represented 311, in the second level by tuple (n_l=25, n_p=25, n_t=50) the two basic check node processors 311 represented, the 3rd Level is by tuple (n_l=50, n_p=50, n_t=50) the three basic check node processors 311 represented, and in most rear class by member Group (n_l=50, n_p=50, n_t=50) the basic check node processor 311 represented.

' SB-CN, serial NS=50, n_{M, in}=6, n_{M, out}=20 standard ECN ' refer to the base at syndrome calculator 31 The serial implementation of this check node processor 311, wherein basic check node processor 311 is performed existing forward to after-frame The traditional operation used in structure.

It should be noted that compared with the operation performed by basic check node processor according to an embodiment of the invention, by The routine operation that basic check node processor performs is related to the redundancy that redundant components are removed from auxiliary output component or bubble Eliminate operation.

The error performance of description the result shows that, the syndrome of the basic check node processor of use of proposition is decoded serial With Parallel Implementation provide with the identical performance of framework backward forward, which show method according to an embodiment of the invention most Dominance.In addition, the basic check node processor that numerical result indicates according to various embodiments verifies substantially relative to conventional The efficiency of the operation used in modal processor.In fact, when applied to syndrome computation, by conventional basic check-node The processing that processor performs can not achieve optimal error performance, and significant damage is particularly presented under high snr value Consumption.This performance loss is due to caused by the redundancy elimination of the level of basic check node processor execution operates.

In addition to error probability performance, with the quantity of basic check node processor (ECN), the number of the input pair of sequence Measure with the total mode of the auxiliary output of basic check node processor to assess the complexity of implemented below：‘FBn_m= 20 ', ' SB-CN, Serial NS=50, n_{M, in}=6, n_{M, out}=20 ', and ' SB-CN, Tree NS=50, n_{M, in}=6, n_M, _ouT=20 '.The results show is in fig. 13.Numerical result shows, according to wherein calculating school using basic check node processor Some embodiments of son are tested, with existing forward backward compared with framework, these drops realized of the decoder based on syndrome Low complexity.Framework according to an embodiment of the invention uses small number of basic check node processor.With it is existing Framework is compared backward forward, and using framework according to some embodiments of the present invention, the quantity of ECN is from 3 (d_j- 2) it is reduced to (d_j- 1).Compared with the conventional decoder based on syndrome, using framework according to some embodiments of the present invention, the school calculated The quantity for testing son is reduced to 3n_{M, out}, and syndrome is ranked up, without additionally being sorted to output.

Therefore, framework according to an embodiment of the invention provides optimal decoding performance, significantly reduces decoding and calculates Complexity and realize hardware cost.

Method described herein and equipment can be realized by various means.For example, these technologies can be soft with hardware Part or its combination are realized.For hardware realization, the treatment element of iterative decoder 123 can be for example according to only hardware configuration (example Such as, in one or more FPGA, ASIC or VLSI integrated circuits with correspondence memory) or according to use VLSI and DSP Both configuration is realized.

Although the embodiment of the present invention is illustrated by various exemplary descriptions, although and in considerable detail Describe these embodiments, but applicant being not intended to limit scope of the following claims or limit in any way In these details.Those skilled in the art will be readily obtained the advantages of extra and modification.Therefore, broader aspect of the invention It is not limited to shown or described detail, exemplary process and illustrative example.

Especially, although performing description to some embodiments of the present invention with reference to the specific implementation of EMS algorithms, It should be noted that the present invention can also be applied to other iterative decoding algorithms of such as min-max algorithm.

Although in addition, with reference to error correcting code some embodiments that the invention has been described for being constructed on Galois Field, It is that those skilled in the art will readily appreciate that, the reality proposed based on the basic code check node processing for syndrome computation Any LDPC code can also be applied to and any be constructed on non-exchange group (such as polynomial code) (such as cyclic code) by applying example Figure error correcting code.

In addition, even if the present invention has the advantages that in the application to communication system, it should be noted that the invention is not restricted to This communication equipment, and can be integrated in many equipment of such as data storage device.

Method described herein can pass through the computer program instructions for the processor for being supplied to any kind of computer To realize, there is execute instruction specify the/machine of the processor of action herein to produce to realize.These computer journeys Sequence instruction can also be stored in the computer-readable medium that computer can be made to work in a specific way.For this reason, it will can count Calculation machine programmed instruction is loaded on computer so that perform series of operation steps, so that computer implemented process is produced, So that performed instruction provides the process for being used for realization the function of specifying herein.

Claims

1. a kind of code check node processing unit for signal realize in decoded decoder, the check node Reason unit is configured as receiving at least three input message and generates at least one output message, wherein the check node Reason unit includes：

- syndrome calculator (31), its be configured with least two basic check node processors (311) from it is described at least Three input message in determine one group of syndrome, each syndrome include symbol, the degree of reiability associated with the symbol, And binary vector；

- correlated elements (33), its be configured as with least one output message in association from one group of syndrome really Fixed one group of candidate components, each candidate components include symbol and the degree of reiability associated with the symbol, one group of time Component is selected to contain one or more pairs of components of same-sign；And

- selecting unit (35), it is configured as by from the one group candidate associated with least one output message Selection includes the components of distinct symbols to determine at least one output message in component.

2. code check node processing unit according to claim 1, the basic check node processor of wherein at least one (311) It is configured as determining intermediary message from first message and second message, the first message and the second message are from described It is derived at least three input message, the intermediary message include one or more components and it is associated with each component in Between binary vector, each component includes symbol and the degree of reiability associated with the symbol, one or more of points Amount is ordered as the degree of reiability of the symbol of given order, and the syndrome calculator (31) is configured as according to from all defeated Enter intermediary message that message determines to determine one group of syndrome.

3. the code check node processing unit according to any one of preceding claims, wherein the signal is using at least What one error correcting code was encoded, each message from described at least three input message includes one or more components, often A component includes symbol and the degree of reiability associated with the symbol, at least one basic check node processor (311) It is configured as determining to be included in the intermediary message by the structural domain application add operation at least one error correcting code Component in symbol, the add operation is applied to the symbol being included in the component of the first message and is included in Symbol in the component of the second message.

4. the code check node processing unit according to any one of preceding claims, wherein at least one verify section substantially Point processor (311) is configured as by determining to be included in the intermediary message to given Algebraic Structure application add operation Degree of reiability in component, the add operation are applied to the degree of reiability being included in the component of the first message And be included in the degree of reiability in the component of the second message, the Algebraic Structure be by real number field, integer field with And selected in the group of natural number field composition.

5. the code check node processing unit according to any one of preceding claims, wherein the syndrome calculator (31) each component for being additionally configured to be included within least three inputs message is associated with initial binary value, Each component of the first message and the second message to derived from the initial binary value binary vector it is related Join, at least one basic check node processor (311) is configured as in determining by the vectorial cascade operation of application and is described Between message component be associated intermediate binary vector, it is described vector cascade operation be applied to the first message point The associated binary vector of amount and the binary vector associated with the component of the second message.

6. code check node processing unit according to claim 5, wherein, it is included in the component in each input message to wrap The given order for including the degree of reiability of the symbol in the component is sorted, and the syndrome calculator (31) is configured as It is associated by the component including most reliable symbol and equal to the initial binary value of predefined first value, and by residue Component is associated with the initial binary value equal to predefined second value.

7. code check node processing unit according to claim 6, wherein predefined first value is equal to zero, and institute Predefined second value is stated equal to one.

8. the code check node processing unit according to any one of preceding claims, wherein, it is included in each syndrome In binary vector include multiple bits, each bit in the multiple bit is associated with output message, the solution phase Pass unit (33) is configured as the syndrome by selecting to include following binary vector in one group of syndrome, comes true The fixed one group candidate components associated with given output message：In the binary vector, disappear with the given output The associated bit of manner of breathing is equal to predefined first value.

9. the code check node processing unit according to any one of preceding claims, wherein the basic check node Managing device (311) is realized with serial frame.

10. the code check node processing unit according to any one of preceding claims 1 to 8, wherein the basic verification Modal processor (311) is realized with setting framework.

11. the code check node processing unit according to any one of preceding claims 1 to 8, wherein the basic verification Modal processor (311) is realized with mixed architecture, and the mixed architecture includes some schools substantially realized with serial frame Test modal processor (311) and to set some basic check node processors (311) of framework realization.

12. the code check node processing unit according to any one of preceding claims, wherein the selecting unit (35) Be configured as by the degree of reiability depending on the symbol in one group of candidate components and from at least one output message The component for the predetermined quantity that selection includes distinct symbols is described at least one to determine in associated one group of candidate components Output message.

13. the code check node processing unit according to any one of preceding claims, wherein at least one error correction Code is Nonbinary Error-correcting Codes.

A kind of 14. side for being used to calculate at least one output message at the code check node processing unit realized in a decoder Method, the decoder are configured as decoding signal, and the code check node processing unit is configured as reception at least three Message is inputted, wherein the described method includes：

- determining one group of syndrome from described at least three input message, each syndrome includes symbol, related to the symbol The degree of reiability and binary vector of connection；

- definite one group of candidate components, each candidate divide from one group of syndrome in association with least one output message Amount includes symbol and the degree of reiability associated with the symbol, and one group of candidate components contain same-sign One or more pairs of components；And

A kind of 15. calculating for being used to calculate at least one output message at the code check node processing unit realized in a decoder Machine program, the decoder are configured as decoding signal, and the code check node processing unit is configured as receiving at least Three input message, computer program product includes the instruction being stored in non-transitory computer-readable storage media, described Instruction is when executed by the processor so that the processor is used for：