Background technology
Continuous development along with mobile communication; LDPC (Lower Density Parity Check; Low-density check) sign indicating number is owing to approach characteristics such as shannon limit, parallel decoding and high-throughput; Become one of current Research of Communication Technology focus, a plurality of communication standards such as DVB-S2, CMMB, wiMax etc. all adopt the LDPC sign indicating number as encoding scheme.Simultaneously, the LDPC sign indicating number on GF (q) (q>2) (is called for short GF (q)-LDPC) and has the binary system of comparing LDPC sign indicating number more performance, good application prospects is arranged, but have the too high shortcoming of decoding complexity.The decoding algorithm of GF (q)-LDPC mainly contains LLR-SPA (Sum-Product algorithm (SPA) in the log-likelihood ratio (LLR) domain), Min-Sum at present.
M-ary LDPC decoding is a kind of message pass-algorithm of operation on Tanner figure, and Fig. 1 is the corresponding Tanner figure of m-ary LDPC, the Tanner figure (the variable node degree is 2 in the legend, and the check-node degree is 4) as shown in Figure 1 that m-ary LDPC is corresponding:
The symbol of using in GF (q)-LDPC decoding algorithm is promptly explained as shown in the table.
Introduce LLR-SPA algorithm, Min-Sum algorithm below.
(1) LLR-SPA decoding algorithm
A, initialization.
With all variable node information initializings is channel information.
B, horizontal step.
At first all variable message are carried out map function,
Calculating for each verification message; Generally adopt forward direction-back to realize to technology, establishing adjacent nodes all in m the check equations is to dope vector is
after
forward direction dope vector is
Utilizing forward direction can get check information with the back to dope vector is calculated as follows.
Fig. 2 is a Core Operation procedure chart; Core Operation procedure chart is as shown in Figure 2; Through two q n dimensional vector ns
are carried out computing, obtain q n dimensional vector n
If α is α the element (0≤α<q) among the GF (q).Then the computational process for α component in
is following:
The Core Operation of LLR-SPA algorithm:
Each verification message to the forward-backward algorithm algorithm is obtained is carried out the inverse transformation operation,
C, vertical step.
Obtain each variable message,
D, hard decision.
Obtain the pseudo-posterior probability vector of each variable node.
The corresponding position of largest component in v variable node being translated into
.
(2) Min-Sum decoding algorithm
The Min-Sum decoding algorithm is just different with LLR-SPA at Core Operation place, only provides the Core Operation of Min-Sum here.
In the practice, generally adopt the arithmetic in LLR territory to be beneficial to realize, LLR-SPA and Min-Sum be all at the enterprising row decoding of log-domain, but refer to that logarithm operates because the calculating of (1) formula relates to, the general using realization of tabling look-up
Calculating.
When utilizing Min-Sum to decipher; Only carrying out simple compare operation can realize through the method that reduces the search volume for the simplification of Min-Sum computation complexity simultaneously; Promptly only consider the part value of two q n dimensional vector ns, thereby formed EMS (Extended Min-Sum) algorithm.
Normalized Min-Sum and Offset Min-Sum are through to the p in (2)
Result αCarry out weighting or increase deviant, can improve the performance of Min-Sum.
The deficiency of prior art is: the decoding algorithm of existing LDPC, and such as LLR-SPA and Min-Sum algorithm.LLR-SPA avoids a large amount of finger logarithm operations through look-up table, but the territory of the GF of multielement LDPC (q) is bigger, and the feasible number of times of tabling look-up is too much, has increased implementation complexity.At present practical algorithm is the LLR-SPA that simplifies, and such as Min-Sum and correction algorithm Normalized Min-Sum and OffsetMin-Sum, but they are obvious with the LLR-SPA gap on performance, so need further to improve performance.
Summary of the invention
The invention provides a kind of interpretation method and device of loe-density parity-check code, cause deciphering complicated problems because of tabling look-up in order to what solve that the LDPC decoding algorithm exists in the prior art.
A kind of interpretation method of loe-density parity-check code is provided in the embodiment of the invention, has comprised the steps: that with all variable node information initializings be channel information, promptly
All variable message are carried out map function,
Wherein,, adopt forward direction-back, establish adjacent nodes all in m the check equations and do to the technology realization for the calculating of each verification message
The forward direction dope vector does
The back to dope vector does
......,
......,
Utilizing forward direction can get check information with the back to dope vector calculates as follows:
In Core Operation step, calculate q n dimensional vector n p
ResultIn α component
The time, relating to calculating
The time, utilize single order Maclaurin MacLaurin progression right
Handle, wherein l
1, l
2For: two operands of max, α<q.
Preferably; The said single order MacLaurin progression that utilizes is handled
, is specially:
Order
Obtain max
*(l
1, l
2) approximate:
Preferably, handling
that obtain is:
Wherein, p
m, p
nIt is LLR (log-likelihood ratio) vector of two q dimensions.
Preferably, handle and to obtain
and comprising:
Represent to calculate α component of output vector at α, q represent the vector length of importing be the q dimension the time, for LLR (log-likelihood ratio) the vector p of two q dimensions of input
mAnd p
n, need calculate the vector p that a q ties up
ResultThe time, for the vector p of q dimension
ResultIn α component
Wherein the account form of α<q is following:
If β+γ=α, wherein said addition carries out in finite field, is the addition of mod (q);
Confirm q to different β and γ,, get p respectively if each (beta, gamma) is right
mIn β component
And p
nIn γ component
Can confirm that to (beta, gamma) q is to
according to q
Respectively q is sued for peace to
and obtain q summed result;
To said q summed result recycle max ' (l
1, l
2) obtain
A kind of code translator of LDPC sign indicating number also is provided in the embodiment of the invention, has comprised:
First decoding module, being used for all variable node information initializings is channel information, promptly
All variable message are carried out map function,
Wherein,, adopt forward direction-back, establish adjacent nodes all in m the check equations and do to the technology realization for the calculating of each verification message
The forward direction dope vector does
The back to dope vector does
......,
......,
Utilizing forward direction can get check information with the back to dope vector calculates as follows:
Second decoding module is used for calculating q n dimensional vector n p in Core Operation step
ResultIn α component
The time, relating to calculating
The time, utilize single order Maclaurin MacLaurin progression right
Handle, wherein l
1, l
2For: two operands of max, α<q.
Preferably; Said second decoding module is further used for utilizing single order MacLaurin progression that
when handling, is specially:
Order
Obtain max
*(l
1, l
2) approximate:
Preferably, said second decoding module is further used for handling
that obtain and is:
Wherein, p
m, p
nIt is LLR (log-likelihood ratio) vector of two q dimensions.
Preferably; When said second decoding module is further used for obtaining in processing
, carry out by following mode:
Represent to calculate α component of output vector at α, q represent the vector length of importing be the q dimension the time, for LLR (log-likelihood ratio) the vector p of two q dimensions of input
mAnd p
n, need calculate the vector p that a q ties up
ResultThe time, for the vector p of q dimension
ResultIn α component
Wherein the account form of α<q is following:
If β+γ=α, wherein said addition carries out in finite field, is the addition of mod (q);
Confirm q to different β and γ,, get p respectively if each (beta, gamma) is right
mIn β component
And p
nIn γ component
Can confirm that to (beta, gamma) q is to
according to q
Respectively q is sued for peace to
and obtain q summed result;
To said q summed result recycle max ' (l
1, l
2) obtain
Beneficial effect of the present invention is following:
Because the present invention in force, in Core Operation step, calculate q n dimensional vector n p
ResultIn α (the individual component of α<q)
The time, relating to calculating
The time, utilize single order Maclaurin MacLaurin progression right
Handle, because this processing mode is higher being similar to of precision, has directly cast out one processing mode with Min-Sum scheduling algorithm of the prior art and compared, the processing scheme in the embodiment of the invention is compared with LLR-SPA, and performance is more approaching.
Simultaneously, because max
*The 2nd of function when handling by the scheme in the embodiment of the invention; Can directly calculate with simple linear function; And need not be as LLR-SPA need be through tabling look-up realization, because it is very slow with respect to linear operation speed to table look-up, if the decoding of the LDPC sign indicating number on the high-order territory simultaneously; Table can be very big, and this makes that also hardware is difficult to realize.Therefore, adopt the scheme in the embodiment of the invention not only can eliminate table lookup operation, reduced implementation complexity.Can also reduce processing delay, improve data processing speed, reduce hardware and realize expense.
Embodiment
Describe below in conjunction with the accompanying drawing specific embodiments of the invention.
At present the decoding algorithm of LDPC sign indicating number is general adopts typical LLR-SPA, but during the decoding of m-ary LDPC sign indicating number, uses the implementation complexity of LLR-SPA too high.The m-ary LDPC sign indicating number generally uses the LLR-SPA of simplification, and like Min-Sum, Offset Min-Sum, Normalized Min-Sum, but their performance LLR-SPA performance loss is bigger.
For this reason, the correction term when proposition is deciphered LLR-SPA in the embodiment of the invention utilizes a simple linear function to approach, and makes its optimal performance that approaches LLR-SPA, has improved decoding speed simultaneously and has reduced implementation complexity simultaneously.
Carry out schematic illustration below earlier.
The LLR-SPA algorithm principle is referring to background technology.In the Core of LLR-SPA algorithm Operation, second can be omitted and decode results not influenced, and therefore only calculates first.
Definition according to the Jacobi logarithm
And there is following character
max
*(l
1,l
2,l
3)=max
*(max
*(l
1,l
2),l
3).
So the calculating to (3) can recycle (4) completion.
Present LLR-SPA when calculating with Jacobi logarithm abbreviation does
(3) (4) (5) are appreciated that as follows:
(3) be the accurate expression of Core Operation.
(3) be to be decomposed into a lot (4) to calculate in fact, once (3) need to calculate q-1 time (4).Such as: need to calculate the q number with, but actually realize through summation in twos.
(5) be that the another kind of of (4) accurately expressed.Because each (4) are easy for calculation not, (5) are split as two parts to (4) and calculate, and a wherein preceding part is only used relatively size, and a back part obtains through tabling look-up.
And through being carried out table lookup operation, (5) second accomplish max at LLR-SPA just
*(l
1, l
2) calculating, thereby caused the excessive problem of number of times of tabling look-up on the high-order territory.
Given this; For head it off; The present invention utilizes single order MacLaurin progression to be similar to second
of (5); Thereby avoided table lookup operation, that is:
Be converted into so (5) are approximate
Therefore the Core Operation that proposes among the present invention is following.
Based on above-mentioned analysis, the present invention proposes a plan as follows in implementing:
Fig. 3 is the interpretation method implementing procedure sketch map of loe-density parity-check code, and is as shown in the figure, comprises the steps:
Step 301, the LDPC sign indicating number is deciphered the step to Core Operation (core operation when utilizing the forward-backward algorithm algorithm) by the Min-Sum method;
When step 302, the component in Core Operation step in the calculating q n dimensional vector n, utilize single order Maclaurin MacLaurin progression to carry out approximate processing.
Concrete, in this step, in Core Operation step, calculate q n dimensional vector n p
ResultIn α (the individual component p of α<q)
Result αThe time, relating to calculating
The time, utilize single order Maclaurin MacLaurin progression right
Handle, wherein l
1, l
2For: two operands of max.
The enforcement of step 301 gets final product referring to the introduction in the background technology or by the prior art processing.
In
step 302; Utilize single order MacLaurin progression that
carried out approximate processing, specifically can for:
Order
Obtain max
*(l
1, l
2) approximate:
Like this, the p that obtains after the approximate processing
Result αFor:
Wherein, p
m, p
nIt is LLR (log-likelihood ratio) vector of two q dimensions.
In the enforcement, further, obtain p in processing
Result αIn, can comprise:
Represent to calculate α component of output vector at α, q represent the vector length of importing be the q dimension the time, for LLR (log-likelihood ratio) the vector p of two q dimensions of input
mAnd p
n, need calculate the vector p that a q ties up
ResultThe time, for the vector p of q dimension
ResultIn α component p
Result α, wherein the account form of α<q is following:
If β+γ=α, wherein said addition carries out in finite field, is the addition of mod (q);
Confirm q to different β and γ,, get p respectively if each (beta, gamma) is right
mIn β component p
m β, and p
nIn γ component p
n γ
Can confirm that to (beta, gamma) q is to (p according to q
m β, p
n γ);
Respectively with q to (p
m β, p
n γ) suing for peace obtains q summed result;
To said q summed result recycle max ' (l
1, l
2) acquisition p
Result α
During the present invention implemented, for the operation of Core Operation, its function can be expressed as follows:
Input need be carried out two q dimension LLR vector p of Core Operation
m, p
nConfirm a q dimension LLR vector p of output
Result
Confirm q dimension LLR vector p
ResultThe time, need ask for p
ResultIn each component.For α p
ResultIn component, corresponding q different (beta, gamma) is right, wherein satisfies β+γ=α.Each (beta, gamma) got p respectively to expression
mIn β component p
m β, and p
nIn γ component p
n γ, can confirm that then q is to (p
m β, p
n γ), with this q to (p
m β, p
n γ) suing for peace obtains q summed result, further to this q summed result recycle max ' (l
1, l
2Thereby) try to achieve p
Resultα component p
Result αAfter the value of α all travels through one time from 0 to q-1, promptly accomplish this Core Operation.
Be that example is described below again with the Computer realizing way.Fig. 4 is a Core Operation flow implementation sketch map, then can realize above-mentioned functions as follows.
The vector p of step 401, two q dimensions of input
m, p
n, p wherein
mBe the channel information of m variable node, p
nBe the channel information of n variable node, be LLR (Log-LikelihoodRatio, the log-likelihood ratio) vector of q dimension;
Step 402, α=0, wherein α is α the component that output vector is calculated in expression;
In this step, α exports since 0 value, the branch weight range of α output vector when calculating from 0 to q-1; Accordingly, a++ representes that then circulation adds in step 408, until α=q;
Step 403, judged whether α<q, be then to change step 404 over to, otherwise change step 409 over to;
In this step, be used to judge whether to have traveled through all p
ResultComponent if traversal finishes, is then exported p
Result, otherwise the calculating of α component is accomplished in continuation.
Step 404, initialization p
Resultα component:
In the initialization, be n dimensional vector n p with q
Resultα component p
Result αInitial value compose and to be p
m 0+ p
n α
In this step, initialization p
Resultα component, expression utilizes any (what choose is first) in q the summing value (referring to the description of a last step) to come this component of initialization here.
In order to calculate the exact value of this component, also need and remaining q-1 summing value l
TempDo the max ' operation of q-1 time circulation.Description referring to following step 407.
Step 405, x=1;
In this step, x is since 1 output, and is corresponding, and x++ representes that then circulation adds in step 7, until x=q, is used for controlling choosing for q-1 summing value of residue.
X<q in x=1 and the step 406 representes to select a remaining q-1 summing value to carry out the max operation, is not difficult to find can travel through q-1 different x value altogether through this mode.
Step 406, judge whether to exist x<q, be then to change step 407 over to, otherwise change step 408 over to;
Step 407,
x++;
Step 406 cooperates with 407, and expression adds x through circulation, so that to p
Result αDo max ' operation with new summing value, simultaneously give p assignment as a result
Result α
Step 408, x++;
Circulation adds x.
Step 409, output p
Result
Based on same inventive concept; A kind of code translator of LDPC sign indicating number also is provided in the embodiment of the invention; Because the principle of this device solves problem is similar with a kind of interpretation method of LDPC sign indicating number, so the enforcement of this device can repeat part and not give unnecessary details referring to the enforcement of method.
Fig. 5 is the code translator structural representation of LDPC sign indicating number, and is as shown in the figure, can comprise in the code translator:
First decoding module 501 is used for by the Min-Sum method LDPC sign indicating number being deciphered the step to Core Operation (core operation when utilizing the forward-backward algorithm algorithm);
Second decoding module 502 is used for calculating q n dimensional vector n p in Core Operation step
ResultIn α component p
Result αThe time, relating to calculating
The time, utilize single order Maclaurin MacLaurin progression right
Handle, wherein l
1, l
2For: two operands of max, α<q.
In the enforcement; Second decoding module can be further used for utilizing single order MacLaurin progression that
when handling, is specially:
Order
Obtain max
*(l
1, l
2) approximate:
Second decoding module can also be further used for handling the p that obtains
Result αFor:
Wherein, p
m, p
nIt is LLR (log-likelihood ratio) vector of two q dimensions.
Second decoding module can also be further used for obtaining p in processing
Result αThe time, carry out by following mode:
Represent to calculate α component of output vector at α, q represent the vector length of importing be the q dimension the time, for LLR (log-likelihood ratio) the vector p of two q dimensions of input
mAnd p
n, need calculate the vector p that a q ties up
ResultThe time, for the vector p of q dimension
ResultIn α component p
Result α, wherein the account form of α<q is following:
If β+γ=α, wherein said addition carries out in finite field, is the addition of mod (q);
Confirm q to different β and γ,, get p respectively if each (beta, gamma) is right
mIn β component p
m β, and p
nIn γ component p
n γ
Can confirm that to (beta, gamma) q is to (p according to q
m β, p
n γ);
Respectively with q to (p
m β, p
n γ) suing for peace obtains q summed result;
To said q summed result recycle max ' (l
1, l
2) acquisition p
Resutl α
For the convenience of describing, the each several part of the above device is divided into various modules with function or the unit is described respectively.Certainly, when embodiment of the present invention, can in same or a plurality of softwares or hardware, realize the function of each module or unit.
The present invention carries out high-precision being similar to LLR-SPA in force at Core Operation place, thereby can utilize linear calculating to eliminate table lookup operation, makes its best performance near LLR-SPA, and the while is near the very little implementation complexity of Min-Sum.
Concrete, the present invention makes in force
Thereby obtain max
*(l
1, l
2) approximate:
It is approximate promptly the Core Operation of LLR-SPA have been carried out high accuracy;
And, handle the p that obtains
Result αFor:
Therefore, the scheme that the present invention provides in implementing is compared with LLR-SPA, and performance is more approaching.
Simultaneously, because max
*The 2nd of function when handling by the scheme in the embodiment of the invention; Can directly calculate with simple linear function; And need not be as LLR-SPA need be through tabling look-up realization, because it is very slow with respect to linear operation speed to table look-up, if the decoding of the LDPC sign indicating number on the high-order territory simultaneously; Table can be very big, and this makes that also hardware is difficult to realize.Therefore, adopt the scheme in the embodiment of the invention not only can eliminate table lookup operation, reduced implementation complexity.Can also reduce processing delay, improve data processing speed, reduce hardware and realize expense.
From the above, the present invention has proposed the high-performance algorithm LLR-SPA in the practice is simplified in implementing, and when possessing the performance same near LLR-SPA, can eliminate table lookup operation, has reduced implementation complexity.Can reduce processing delay, improve data processing speed, reduce hardware and realize expense.
Those skilled in the art should understand that embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt the form of the embodiment of complete hardware embodiment, complete software implementation example or combination software and hardware aspect.And the present invention can be employed in the form that one or more computer-usable storage medium (including but not limited to magnetic disc store, CD-ROM, optical memory etc.) that wherein include computer usable program code go up the computer program of implementing.
The present invention is that reference is described according to the flow chart and/or the block diagram of method, equipment (system) and the computer program of the embodiment of the invention.Should understand can be by the flow process in each flow process in computer program instructions realization flow figure and/or the block diagram and/or square frame and flow chart and/or the block diagram and/or the combination of square frame.Can provide these computer program instructions to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device to produce a machine, make the instruction of carrying out through the processor of computer or other programmable data processing device produce to be used for the device of the function that is implemented in flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame appointments.
These computer program instructions also can be stored in ability vectoring computer or the computer-readable memory of other programmable data processing device with ad hoc fashion work; Make the instruction that is stored in this computer-readable memory produce the manufacture that comprises command device, this command device is implemented in the function of appointment in flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame.
These computer program instructions also can be loaded on computer or other programmable data processing device; Make on computer or other programmable devices and to carry out the sequence of operations step producing computer implemented processing, thereby the instruction of on computer or other programmable devices, carrying out is provided for being implemented in the step of the function of appointment in flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame.
Although described the preferred embodiments of the present invention, in a single day those skilled in the art get the basic inventive concept could of cicada, then can make other change and modification to these embodiment.So accompanying claims is intended to be interpreted as all changes and the modification that comprises preferred embodiment and fall into the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.