CN102176750B - High-performance adaptive binary arithmetic encoder - Google Patents
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Abstract
The invention discloses a high-performance adaptive binary arithmetic encoder which mainly solves the problems of low encoding speed and complicated structure of the existing binary arithmetic encoder. The encoder comprises a probability model storing module, a probability model updating module, an encoding state updating module, a normalization module and register groups, wherein a first register group is inserted between the probability model storing module and the probability model updating module, and a second register group is inserted between the encoding state updating module and the normalization module so as to form a three-level flow structure to improve the encoding speed by sufficiently using the parallelism of hardware; a caching register unit is adopted in the probability model storing module so that the read/write conflict of a probability model memory is effectively avoided; and a prefix zero detection unit is adopted in the normalization module so that the structure of the normalization module is simple and easy to implement with hardware. The high-performance adaptive binary arithmetic encoder disclosed by the invention has the characteristics of high encoding speed and simple structure, and can be applied to the real-time encoding of high-definition videos.
Description
Technical field
The invention belongs to technical field of video processing, relate to the arithmetic encoder structure, can be used for very lagre scale integrated circuit (VLSIC) VLSI design.
Background technology
Following society will be informationalized society.Video after digitized information, the especially digitlization and audio-frequency information have the characteristics of data magnanimity property, cause very big difficulty for the storage and the transmission of information, become to hinder human one of the bottleneck of effective information that obtains and use.Video information has series of advantages, like intuitive, and certainty, high efficiency, popularity or the like, but amount of information is too big.Make video obtain effective application, must solve the problem of compression rates and decoded image quality.The two is two conflicting aspects.Therefore, research and development novel and effective multi-medium data compaction coding method will be a best choice with stored in form and these data of transmission of compressing.Video encoding standard H.264 in, video data is a unit encoding according to macro block, current macro deducts predicted macroblock, obtains residual error macro block.Residual error macro block is carried out conversion, quantification, obtain quantization parameter; Quantization parameter is carried out carrying out entropy coding after the zig-zag scanning; Result behind the entropy coding is delivered to network layer to be transmitted.
Entropy coding is most important to the code efficiency that improves whole system as the key technology in the standard H.264.Entropy coding is made up of two parts, and a coded system that is based on variable length code comprises based on contextual self-adapting changeable long codes CAVLC and index Columbus coding; Another is based on the coded system of arithmetic coding, promptly based on contextual adaptive binary arithmetic coding CABAC.These two kinds of coding methods all are to have utilized adaptive context model to improve the efficient of coding.Compare with CAVLC, CABAC can make code check reduce 9-14%, but computation complexity has increased 25-30%.In practical application, can adopt actual coding method in these two kinds of coding methods as system.
People such as H.Shojania are at article " A High Performance CABAC Encoder " The 3rd International IEEE NEWCAS Conference, and 2005, among the pp.315-319, a kind of binary arithmetic coder structure has been proposed.This structure is carried out multiplexing to normal mode in the binary arithmetic coding and bypass mode, but does not adopt a kind of effective pipeline organization, has reduced the processing speed of binary arithmetic coder, does not reach the coding requirement of HD video.People such as L.F.Li are at article " A CABAC Encoding Core with Dynamic Pipeline " IEEE Asia Pacific Conference on Circuits and Systems; 2006, a kind of binary arithmetic coder based on the dynamic pipeline structure has been proposed among the pp.760-764.Though this structure has adopted dynamic pipeline, simplified the processing complexity of arithmetic encoder, coding rate does not reach Bit data of a clock cycle coding.People such as R.R.Osorio are at article " High Throughput Architecture for CABAC " IEEE Transactions on Circuits and Systems for Video Technology; Pp.16-20; In 2006, a kind of high speed binary arithmetic coder structure has been proposed.This structure can realize the coding rate of 2 Bit datas of a clock cycle coding, but coder structure is too complicated, and has increased the consumption of hardware resource.
Summary of the invention
The objective of the invention is to overcome the defective and the deficiency that exist in the above-mentioned background technology, a kind of high performance self-adaption binary arithmetic coder is provided,, improve coding rate to simplify coder structure.
Realize adaptive binary arithmetic coding device of the present invention, comprising: probabilistic model memory module, probabilistic model update module, encoding state update module, normalization module and registers group, wherein:
The probabilistic model memory module; Comprise and read address-generation unit, write address deposit unit, probabilistic model memory cell, selected cell and buffer memory deposit unit; Read the address of reading that address-generation unit is used to produce the probabilistic model memory cell; This reads the address obtains the probabilistic model memory cell through the write address deposit unit write address; Selected cell is used between probabilistic model memory cell and buffer memory deposit unit, selecting, and this buffer memory deposit unit is used for the probabilistic model that the buffer memory arithmetic coding process upgrades;
The normalization module; Comprise prefix zero detecting unit, the interval shift unit of encoding state, encoding state lower limit shift unit, this prefix zero detecting unit is confirmed the shift count of interval shift unit of encoding state and encoding state lower limit shift unit through the number of prefix zero in detecting between the arithmetic coding state area;
Be inserted with first registers group between said probabilistic model memory module and the probabilistic model update module, be inserted with second registers group between said encoding state update module and the normalization module, form three grades of flowing structures.
Above-mentioned adaptive binary arithmetic coding device; The wherein said address-generation unit of reading; Comprise base address generator, offset address generator and adder, the base address that the base address generator produces probabilistic model inputs to adder, and the offset address that the offset address generator produces probabilistic model inputs to adder; Adder obtains reading the address to base address and offset address addition.
Above-mentioned adaptive binary arithmetic coding device, wherein said probabilistic model memory cell, the dual-port static random access memory ram that is 470 * 7 bits by a size constitutes.
Above-mentioned adaptive binary arithmetic coding device, wherein said buffer memory deposit unit is made up of maximum probability character register and probability status register.
Above-mentioned adaptive binary arithmetic coding device; Wherein said prefix zero detecting unit; Comprise: the full null detector of 4 bits, the full null detector of 2 bits, 1 bit of zero detector and two selectors; The full null detector of this 4 bit is used to detect the 8th bit to the 5 Bit datas between the arithmetic coding state area, and testing result is exported to first selector; The full null detector of this 2 bit is used to detect the 4th bit to the 3 Bit datas between the arithmetic coding state area, and testing result is exported to first selector and second selector respectively; This 1 bit of zero detector is used to detect the 2nd Bit data between the arithmetic coding state area, and testing result is exported to second selector; This first selector is used between full null detector of 4 bits and the full null detector of 2 bits, selecting; This second selector is used between full null detector of 2 bits and 1 bit of zero detector, selecting; The testing result of the selection result of first selector and second selector and 1 bit of zero detector constitutes the output result of prefix zero detecting unit.
Above-mentioned adaptive binary arithmetic coding device; The interval shift unit of wherein said encoding state; Comprise: 4 bit shift units, 2 bit shift units, 1 bit shift unit and three selectors; 4 bit shift units carry out 4 bit left operations to the encoding state interval, and first selector is selected between the output result of 4 bit shift units and encoding state interval, and 2 bit shift units carry out the operation of 2 bit left to the output result of first selector; Second selector is selected between the output result of the output result of 2 bit shift units and first selector, and 1 bit shift unit carries out the operation of 1 bit left to the output result of second selector; Third selector is selected between the output result of the output result of 1 bit shift unit and second selector, and the output result of third selector is as the output result of the interval shift unit of encoding state.
Above-mentioned adaptive binary arithmetic coding device; Wherein said encoding state lower limit shift unit; Select 1 selector to form by seven 1 bit shift units and 8; The first bit shift unit carries out the operation of 1 bit left to the encoding state lower limit, and the second bit shift unit carries out the operation of 1 bit left to the output result of the first bit shift unit, and the tribit shift unit carries out the operation of 1 bit left to the output result of the second bit shift unit; The 4th bit shift unit carries out the operation of 1 bit left to the output result of tribit shift unit; The 5th bit shift unit carries out the operation of 1 bit left to the output result of the 4th bit shift unit, and the 6th bit shift unit carries out the operation of 1 bit left to the output result of the 5th bit shift unit, and the 7th bit shift unit carries out the operation of 1 bit left to the output result of the 6th bit shift unit; 8 select 1 selector that the output result and the encoding state interval of these seven 1 bit shift units are selected, and selection result is as the output result of encoding state lower limit shift unit.
The present invention compared with prior art has the following advantages:
First; The present invention is through adopting the three class pipeline structure; The concurrency that makes full use of hardware resource improves the processing speed and the structure of simplifying encoder of encoder; Make the work that each submodule in the binary arithmetic coder can be continuously, coordinated, improved the degree of concurrence and the coding rate of binary arithmetic coding greatly, can stablize and realize Bit data of a clock cycle coding.
Second; The present invention is through adopting the buffer memory deposit unit; Solved the memory read/write collision problem in the probabilistic model storing process; Making in the process of carrying out binary arithmetic coding can the continual renewal of carrying out probabilistic model, thereby has guaranteed that binary arithmetic coder is in continuous the encoding of each clock cycle.
The 3rd, the present invention utilizes a spot of hardware resource to accomplish the normalization operation through adopting prefix zero detecting unit, the interval shift unit of encoding state and encoding state lower limit shift unit, make the normalization module structure not only simply but also be easy to hardware and realize.
Description of drawings
Characteristic of the present invention and advantage further specify through following accompanying drawing and embodiment:
Fig. 1 is the structured flowchart of the adaptive binary arithmetic coding device of the embodiment of the invention;
Fig. 2 is encoding state update module and a probabilistic model update module structured flowchart in the embodiment of the invention;
Fig. 3 is a probabilistic model memory module configuration block diagram in the embodiment of the invention;
Fig. 4 is a normalized mode block structure block diagram in the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
With reference to Fig. 1, adaptive binary arithmetic coding device of the present invention comprises: probabilistic model memory module, probabilistic model update module, encoding state update module, normalization module and registers group.Be inserted with first registers group between probabilistic model memory module and the probabilistic model update module, be inserted with second registers group between encoding state update module and the normalization module, form three grades of flowing structures.The probabilistic model memory module is positioned at the first order of this pipeline organization, and this module at first produces the address of reading of probabilistic model, from the probabilistic model memory, reads the required probabilistic model of binary arithmetic coding then; The probabilistic model that reads is exported to probabilistic model update module and encoding state update module after depositing through first registers group; Probabilistic model update module and encoding state update module are positioned at the second level of this pipeline organization; The probabilistic model update module is upgraded the probabilistic model of importing and is obtained new probabilistic model, and the encoding state update module is upgraded the current encoder state and obtained new encoding state; Probabilistic model after the renewal is exported to the probabilistic model memory module and is stored, and the encoding state after the renewal is exported to the normalization module after depositing through second registers group; The normalization module is positioned at the third level of this pipeline organization, and this module is carried out the normalization operation to encoding state interval and encoding state lower limit.
Fig. 2 has provided the encoding state update module of arithmetic encoder of the present invention and the structure of probabilistic model update module.Wherein:
The encoding state update module is accomplished the renewal of encoding state, and this renewal comprises the renewal in encoding state interval and the renewal of encoding state lower limit.This module is made up of comparator, first look-up table, adder, first subtracter, second subtracter, first selector and second selector.The interval handling process of upgrading of encoding state is: interval through the encoding state that first look-up table obtains the minimum probability character by encoding state interval and probability state index; Wherein, first look-up table is used to accomplish the multiply operation of encoding state interval and probability state; Then, subtraction is carried out in encoding state interval encoding state is interval and the minimum probability character, and the encoding state that obtains the maximum probability character is interval; At last, the interval encoding state interval of passing through after first selector obtains final updated of encoding state interval by the encoding state of minimum probability character and the maximum probability character.The coded data of input and maximum probability character compare through comparator, and the output of comparator is judged as the selection of this first selector.The handling process that the encoding state lower limit upgrades is: encoding state interval and encoding state lower limit carry out add operation through adder, and the result with first look-up table carries out the encoding state lower limit that subtraction obtains the minimum probability character again; Then, encoding state lower limit and the present encoding state lower limit by this minimum probability character passes through the encoding state lower limit after second selector obtains final updated.The judgement of this second selector is input as the output of above-mentioned comparator.
The probabilistic model update module is accomplished the renewal of probabilistic model, and this renewal comprises the renewal of probability state and the renewal of maximum probability character.This module is by zero arbiter, negate device, second look-up table, and third selector and the 4th selector are formed.The handling process that the probability state upgrades does; Obtain two updating value of probability state by the logical second look-up table of probability state index; Wherein the corresponding present encoding data of first updating value are maximum probability characters, and second corresponding present encoding data of updating value is minimum probability characters.These two updating value obtain final probability state updating value after selecting through third selector.The judgement of third selector is input as the output of above-mentioned encoding state update module comparator.The handling process that the maximum probability character upgrades is that the maximum probability character is carried out inversion operation, the maximum probability character after obtaining upgrading after the output of this negate device and maximum probability character are selected through the 4th selector through the negate device.The probability state carries out the logical AND operation with the output of above-mentioned encoding state update module comparator behind the zero passage arbiter, judge as the selection of the 4th selector then.
Fig. 3 has provided the structure of the probabilistic model memory module of arithmetic encoder of the present invention; It comprises: read address-generation unit, write address deposit unit, probabilistic model memory cell, selected cell and buffer memory deposit unit; Read the address of reading that address-generation unit is used to produce the probabilistic model memory cell; This reads the address obtains the probabilistic model memory cell through the write address deposit unit write address; Selected cell is used between probabilistic model memory cell and buffer memory deposit unit, selecting, and this buffer memory deposit unit is used for the probabilistic model that the buffer memory arithmetic coding process upgrades.Wherein, Read address-generation unit; Comprise base address generator, offset address generator and adder, the base address that the base address generator produces probabilistic model inputs to adder, and the offset address that the offset address generator produces probabilistic model inputs to adder; Adder obtains the address of reading of probabilistic model to base address and offset address addition.
Fig. 4 has provided the structure of the normalization module of arithmetic encoder of the present invention; It comprises: prefix zero detecting unit, the interval shift unit of encoding state and encoding state lower limit shift unit, this prefix zero detecting unit are confirmed the shift count of interval shift unit of encoding state and encoding state lower limit shift unit through the number of prefix zero in detecting between the arithmetic coding state area.Wherein:
Prefix zero detecting unit; Completion is to the detection of the interval prefix zero of arithmetic coding; Obtain the shift count of interval shift unit of encoding state and encoding state lower limit shift unit, this unit is made up of the full null detector of 4 bits, the full null detector of 2 bits, 1 bit of zero detector and two selectors.The full null detector of this 4 bit is used to detect the 8th bit to the 5 Bit datas between the arithmetic coding state area, and testing result is exported to first selector; The full null detector of this 2 bit is used to detect the 4th bit to the 3 Bit datas between the arithmetic coding state area, and testing result is exported to first selector and second selector respectively; This 1 bit of zero detector is used to detect the 2nd Bit data between the arithmetic coding state area, and testing result is exported to second selector; This first selector is used between full null detector of 4 bits and the full null detector of 2 bits, selecting; This second selector is used between full null detector of 2 bits and 1 bit of zero detector, selecting; The testing result of the selection result of first selector and second selector and 1 bit of zero detector constitutes the output result of prefix zero detecting unit.
The interval shift unit of encoding state is accomplished the interval shifting function of encoding state, and the encoding state that obtains after the normalization is interval, and this unit is made up of 4 bit shift units, 2 bit shift units, 1 bit shift unit and three selectors.4 bit shift units carry out 4 bit left operations to the encoding state interval, and first selector is selected between the output result of 4 bit shift units and encoding state interval, and 2 bit shift units carry out the operation of 2 bit left to the output result of first selector; Second selector is selected between the output result of the output result of 2 bit shift units and first selector, and 1 bit shift unit carries out the operation of 1 bit left to the output result of second selector; Third selector is selected between the output result of the output result of 1 bit shift unit and second selector, and the output result of third selector is as the output result of the interval shift unit of encoding state.
Encoding state lower limit shift unit is accomplished the shifting function to the encoding state lower limit, obtains the encoding state lower limit after the normalization, and this unit selects 1 selector to form by seven 1 bit shift units and 8.The first bit shift unit carries out the operation of 1 bit left to the encoding state lower limit; The second bit shift unit carries out the operation of 1 bit left to the output result of the first bit shift unit; The tribit shift unit carries out the operation of 1 bit left to the output result of the second bit shift unit; The 4th bit shift unit carries out the operation of 1 bit left to the output result of tribit shift unit; The 5th bit shift unit carries out the operation of 1 bit left to the output result of the 4th bit shift unit, and the 6th bit shift unit carries out the operation of 1 bit left to the output result of the 5th bit shift unit, and the 7th bit shift unit carries out the operation of 1 bit left to the output result of the 6th bit shift unit; 8 select 1 selector that the output result and the encoding state interval of these seven 1 bit shift units are selected, and selection result is as the output result of encoding state lower limit shift unit.
More than be a preferred embodiment of the present invention, in pairs any restriction of the present invention inadequately, obviously under thought of the present invention and prompting, anyone can make various modifications and variation, but these are all at the row of protection of the present invention.
Claims (5)
1. a high performance self-adaption binary arithmetic coder comprises probabilistic model memory module, probabilistic model update module, encoding state update module, normalization module and registers group, it is characterized in that:
The probabilistic model memory module; Comprise and read address-generation unit, write address deposit unit, probabilistic model memory cell, selected cell and buffer memory deposit unit; Read the address of reading that address-generation unit is used to produce the probabilistic model memory cell; This reads the address obtains the probabilistic model memory cell through the write address deposit unit write address; Selected cell is used between probabilistic model memory cell and buffer memory deposit unit, selecting, and this buffer memory deposit unit is used for the probabilistic model that the buffer memory arithmetic coding process upgrades;
The normalization module; Comprise prefix zero detecting unit, the interval shift unit of encoding state, encoding state lower limit shift unit, this prefix zero detecting unit is confirmed the shift count of interval shift unit of encoding state and encoding state lower limit shift unit through the number of prefix zero in detecting between the arithmetic coding state area;
Be inserted with first registers group between said probabilistic model memory module and the probabilistic model update module, be inserted with second registers group between said encoding state update module and the normalization module, form three grades of flowing structures;
Said probabilistic model memory module is positioned at the first order of this pipeline organization, and this module at first produces the address of reading of probabilistic model, from the probabilistic model memory, reads the required probabilistic model of binary arithmetic coding then; The probabilistic model that reads is exported to probabilistic model update module and encoding state update module after depositing through first registers group; Probabilistic model update module and encoding state update module are positioned at the second level of this pipeline organization; The probabilistic model update module is upgraded the probabilistic model of importing and is obtained new probabilistic model, and the encoding state update module is upgraded the current encoder state and obtained new encoding state; Probabilistic model after the renewal is exported to the probabilistic model memory module and is stored, and the encoding state after the renewal is exported to the normalization module after depositing through second registers group; The normalization module is positioned at the third level of this pipeline organization, and this module is carried out the normalization operation to encoding state interval and encoding state lower limit;
The interval shift unit of said encoding state; Comprise: 4 bit shift units, 2 bit shift units, 1 bit shift unit and three selectors; 4 bit shift units carry out the operation of 4 bit left to the encoding state interval; First selector is selected between the output result of 4 bit shift units and encoding state interval, and 2 bit shift units carry out the operation of 2 bit left to the output result of first selector; Second selector is selected between the output result of the output result of 2 bit shift units and first selector, and 1 bit shift unit carries out the operation of 1 bit left to the output result of second selector; Third selector is selected between the output result of the output result of 1 bit shift unit and second selector, and the output result of third selector is as the output result of the interval shift unit of encoding state.
Said encoding state lower limit shift unit; Select 1 selector to form by seven 1 bit shift units and 8; The first bit shift unit carries out the operation of 1 bit left to the encoding state lower limit; The second bit shift unit carries out the operation of 1 bit left to the output result of the first bit shift unit; The tribit shift unit carries out the operation of 1 bit left to the output result of the second bit shift unit, and the 4th bit shift unit carries out the operation of 1 bit left to the output result of tribit shift unit, and the 5th bit shift unit carries out the operation of 1 bit left to the output result of the 4th bit shift unit; The 6th bit shift unit carries out the operation of 1 bit left to the output result of the 5th bit shift unit, and the 7th bit shift unit carries out the operation of 1 bit left to the output result of the 6th bit shift unit; 8 select 1 selector that the output result and the encoding state interval of these seven 1 bit shift units are selected, and selection result is as the output result of encoding state lower limit shift unit.
2. according to claims 1 described adaptive binary arithmetic coding device; It is characterized in that: read address-generation unit; Comprise base address generator, offset address generator and adder, the base address that the base address generator produces probabilistic model inputs to adder, and the offset address that the offset address generator produces probabilistic model inputs to adder; Adder obtains reading the address to base address and offset address addition.
3. according to claims 1 described adaptive binary arithmetic coding device, it is characterized in that: the probabilistic model memory cell, the dual-port static random access memory ram that is 470 * 7 bits by a size constitutes.
4. according to claims 1 described adaptive binary arithmetic coding device, it is characterized in that: the buffer memory deposit unit is made up of maximum probability character register and probability status register.
5. according to claims 1 described adaptive binary arithmetic coding device; It is characterized in that: prefix zero detecting unit; Comprise: the full null detector of 4 bits, the full null detector of 2 bits, 1 bit of zero detector and two selectors; The full null detector of this 4 bit is used to detect the 8th bit to the 5 Bit datas between the arithmetic coding state area, and testing result is exported to first selector; The full null detector of this 2 bit is used to detect the 4th bit to the 3 Bit datas between the arithmetic coding state area, and testing result is exported to first selector and second selector respectively; This 1 bit of zero detector is used to detect the 2nd Bit data between the arithmetic coding state area, and testing result is exported to second selector; This first selector is used between full null detector of 4 bits and the full null detector of 2 bits, selecting; This second selector is used between full null detector of 2 bits and 1 bit of zero detector, selecting; The testing result of the selection result of first selector and second selector and 1 bit of zero detector constitutes the output result of prefix zero detecting unit.
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| US9210438B2 (en) | 2012-01-20 | 2015-12-08 | Sony Corporation | Logical intra mode naming in HEVC video coding |
| CA3217710A1 (en) * | 2012-05-25 | 2013-11-28 | Sun Patent Trust | Image encoding and decoding using context adaptive binary arithmetic coding with a bypass mode |
| CN105791828B (en) * | 2015-12-31 | 2019-05-31 | 杭州士兰微电子股份有限公司 | Binary arithmetic coder and its coding method |
| CN107343201B (en) * | 2017-06-21 | 2019-11-26 | 珠海市杰理科技股份有限公司 | CABAC coding method and system |
| CN107623524B (en) * | 2017-07-01 | 2020-07-31 | 中山大学 | Hardware-based Huffman coding method and system |
| CN107277553B (en) * | 2017-07-10 | 2020-10-27 | 中国科学技术大学 | Binary arithmetic coder |
| US10735736B2 (en) * | 2017-08-29 | 2020-08-04 | Google Llc | Selective mixing for entropy coding in video compression |
| US9992496B1 (en) * | 2017-11-15 | 2018-06-05 | Google Llc | Bin string coding based on a most probable symbol |
| CN111787325B (en) * | 2020-07-03 | 2022-03-08 | 北京博雅慧视智能技术研究院有限公司 | Entropy encoder and encoding method thereof |
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| CN101489128A (en) * | 2009-01-19 | 2009-07-22 | 山东大学 | JPEG2000 pipeline arithmetic encoding method and circuit |
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